CN104167358A - Semiconductor device manufacture method - Google Patents

Semiconductor device manufacture method Download PDF

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Publication number
CN104167358A
CN104167358A CN201310184801.3A CN201310184801A CN104167358A CN 104167358 A CN104167358 A CN 104167358A CN 201310184801 A CN201310184801 A CN 201310184801A CN 104167358 A CN104167358 A CN 104167358A
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layer
top layer
laying
semi
gate
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CN104167358B (en
Inventor
唐兆云
闫江
唐波
贾宬
王大海
李峻峰
许静
王红丽
徐烨峰
高建峰
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention discloses a semiconductor device manufacture method comprising the following steps: an SOI substrate is provided and comprises a base, a buried oxygen layer and a top layer; a grid electrode groove is formed in the top layer through etching operation, and a gasket layer and a filling layer are formed in the grid electrode groove; the filling layer, the gasket layer and the top layer are etched; an opening through which the buried oxygen layer is exposed is formed; a source region is formed on a part, arranged in the opening, of the top layer; a channel region is formed on a pat, arranged on the bottom part of the grid electrode groove, of the top layer; shallow trench isolation is realized by filling an isolating material in the opening. According to the semiconductor device manufacture method of the invention, the grid electrode groove is formed in the SOI top layer through the etching operation, the channel region at the bottom part of the grid electrode groove is limited, an active region and shallow trench isolation are limited after the grid electrode groove is filled, and therefore the ultrathin SOI semiconductor device is formed, device miniaturization is realized, and device performance is improved.

Description

Method, semi-conductor device manufacturing method
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, more specifically, relate to the transistorized manufacture method of silicon (ETSOI) on a kind of ultrathin insulating body.
Background technology
In current sub-20nm technology, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture, this structural reinforcing grid control ability, suppressed electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure is compared with traditional single grid body Si or SOI MOSFET, can suppress short-channel effect (SCE) and leak to cause induced barrier reduction (DIBL) effect, there is lower junction capacitance, can realize raceway groove light dope, can carry out adjusting threshold voltage by the work function that metal gates is set, can obtain the drive current of approximately 2 times, reduce the requirement for effective gate oxide thickness (EOT).And tri-gate devices is compared with double-gated devices, grid has surrounded channel region end face and two sides, and grid control ability is stronger.Further, loopful has more advantage around nano wire multiple-grid device.These devices, because size is little, complex structure, easily interfere with each other between adjacent raceway groove, and therefore the isolation technology of raceway groove becomes more and more important.
Existing FinFET structure and manufacture method comprise: the 1) FinFET of SOI substrate, utilize the mask etching SOI substrates such as photoresist, automatically stop on oxygen buried layer, remaining top silicon layer forms fin, and isolate adjacent fin because oxygen buried layer can insulate well, therefore carry out isolation channel without extra processing step or structure; 2) the body substrate FinFET of knot isolation, utilize mask etching body silicon substrate to form groove and fin, in groove between fin, deposit fill oxide and carry out the adjacent fin of side direction insulation isolation, angle-tilt ion is injected high dose dopant subsequently, note people doped region in the formation of fin bottom with top different conduction-types, utilizes PN junction to isolate fin and substrate; 3) the body substrate FinFET isolating based on material; utilize mask etching body substrate-like to become groove and fin; in groove between fin, deposition oxide is isolated with side direction; form the side walls such as nitride in fin side so that protection to be provided; carry out thermal oxidation; make not by the fin base section of side wall protection or all oxidized so that the oxide layer that formation connected with each other is horizontal utilizes the oxide layer obtaining to isolate fin and substrate.
In above-mentioned these structures and method, although FinFET structure and the technique of SOI substrate are simple, backing material cost is high, not as body Si substrate is easy to for large-scale production; On body silicon substrate, utilize the FinFET of PN junction isolation to utilize and inject knot isolation, isolation effect is subject to the restriction of implantation dosage, the degree of depth and effect is poor, and injection technology is difficult to control, and easily introduces extra doping to channel region and affects device electric conductivity; Complex process is with high costs on body silicon substrate, to utilize the FinFET of horizontal selective oxidation isolation, and oxidate temperature is high, thereby extra-stress and strain impact conduction are easily introduced in channel region.In addition, these technology are all to make in the process that forms silicon fin conventionally, and when after FinFET adopts, grid technique is manufactured, false grid form the isolation structure of making in silicon fin process before forming, and when experience subsequent technique, insulation property may be impaired.In addition, these current silicon fin trench isolation structures be all conventionally along vertical-channel direction (hereinafter referred to as X-X' direction or second direction, also be the direction that grid lines extend) upper formation, for along between the upper fin of channel direction (hereinafter referred to as Y-Y ' direction or first direction, being also the direction that fin lines extend) and perfect not with the isolation of substrate.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of method, semi-conductor device manufacturing method of novelty, form gate trench by etching in SOI substrate top layer and reduce element height to realize miniaturization, and utilize packed layer to form shallow trench isolation to improve device isolation isolation performance for mask deposition.
Realizing above-mentioned purpose of the present invention, is by a kind of method, semi-conductor device manufacturing method is provided, and comprising: SOI substrate is provided, comprises substrate, oxygen buried layer and top layer; In top layer, etching forms gate trench; In gate trench, form laying and packed layer; Etching packed layer, laying and top layer, form the opening that exposes oxygen buried layer, and the top layer in opening forms active area, the top layer constituting channel district of gate trench bottom; In opening fill insulant form shallow trench isolation from.
Wherein, oxygen buried layer thickness 80～200nm, top layer thickness 30～100nm.
Wherein, laying material comprises silica, TEOS, silicon nitride, silicon oxynitride, amorphous carbon, diamond like carbon amorphous carbon (DLC) and combination thereof, and thickness is 5～30nm; Packed layer material comprises silicon nitride, amorphous carbon, DLC, polysilicon, monocrystalline silicon, amorphous silicon, polycrystal SiGe, polycrystalline Si C and combination thereof, and thickness is 20～50nm.
Wherein, the channel region thickness that the top layer of gate trench bottom forms is 1～20nm.
Wherein, form shallow trench isolation from after further comprise: planarization shallow trench, packed layer are until exposure laying; Top layer dopant implant taking packed layer as mask to both sides, forms source-drain area; Remove packed layer, again expose gate trench; In gate trench, form gate stack.
Wherein, gate stack comprises the gate insulator of the boundary layer of oxide material, high k material, work function regulating course and the resistance adjustment layer of nitride material.
Wherein, wet etching is removed packed layer.
Wherein, remove the laying of gate trench bottom, in gate trench sidewalls, retain laying to be used as grid curb wall.
Wherein, forming gate stack further comprises afterwards: on device, form interlayer dielectric layer; Etching interlayer dielectric layer forms the contact hole in source of exposure drain region; In contact hole, form metal silicide; On metal silicide, form contact plug.
The present invention also provides a kind of semiconductor device, comprising: substrate, has substrate, oxygen buried layer and top layer; Gate stack, is arranged in the active area of top layer; Channel region, is arranged in top layer gate stack below; Source-drain area, is arranged in top layer gate stack both sides; Shallow trench isolation from, be arranged in outside the active area of top layer.
According to method, semi-conductor device manufacturing method of the present invention, in SOI top layer etching form gate trench and define below channel region, fill be limited with after gate trench source region and shallow trench isolation from, form thus ultra-thin SOI semiconductor device, realize the miniaturization of device, improved device performance.
Brief description of the drawings
Describe technical scheme of the present invention in detail referring to accompanying drawing, wherein:
Fig. 1 to Figure 14 is the cutaway view according to the each step of method, semi-conductor device manufacturing method of the present invention.
Embodiment
Also describe feature and the technique effect thereof of technical solution of the present invention in detail in conjunction with schematic embodiment referring to accompanying drawing.It is pointed out that structure like similar Reference numeral representation class, term " first " used in the application, " second ", " on ", D score, " thick ", " thin " etc. can be used for modifying various device architectures and/or manufacturing step.These modify the space, order or the hierarchical relationship that not imply unless stated otherwise institute's modification device architecture and/or manufacturing step.
As shown in Figure 1, provide substrate 1, it can be body Si, SOI, body Ge, GeOI, SiGe, GeSb, can be also III-V family or II-VI compound semiconductor substrate, for example GaAs, GaN, InP, InSb etc.For with existing CMOS process compatible to be applied to large-scale digital ic manufacture, substrate 1 is preferably SOI or SiGe, SiGeOI etc. containing Si material.In a preferred embodiment of the invention, substrate 1 comprises thicker monocrystalline silicon Si substrate 1A, such as the oxygen buried layer 1B of silica material and thinner single crystalline Si top layer 1C, and wherein oxygen buried layer 1B thickness for example and preferably sOI top layer 1C thickness for example and preferably
As shown in Figure 2, at the upper first photoetching offset plate figure PR1 that forms of substrate 1 (particularly SOI top layer 1C).On whole device, apply photoresist layer PR by techniques such as spin coating, spraying, silk screen printings, and utilize predetermined mask plate exposure, development to form the first photoetching offset plate figure PR1, wherein PR1 has near the opening being positioned at center, active area to expose substrate 1 top layer 1C, for limiting the position of gate trench in the future.
As shown in Figure 3, taking the first photoetching offset plate figure PR1 as mask, the top layer 1C of etched substrate 1 is to form gate trench 1G.Can select various anisotropic lithographic methods according to the material difference of top layer 1C, such as plasma dry etching, reactive ion etching (RIE) or Tetramethylammonium hydroxide (TMAH) wet etching etc.The degree of depth (distance between bottom and top) of gate trench 1G is less than the thickness of the top layer 1C of SOI substrate 1, also at least leaves a part for top layer bottom for channel region 1CH in the future.In a preferred embodiment of the invention, the thickness of the gate trench 1G remaining top layer 1C in below (being also channel region 1CH) is preferably, form gate trench 1G and remove the first photoetching offset plate figure PR1 by dry method or wet processing afterwards.
As shown in Figure 4, in gate trench 1G and on top layer 1C, form laying 2.For example form sidewall and the bottom of laying 2 with cover gate groove 1G by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputters, and also covered the top of the top layer 1C of SOI substrate 1 simultaneously.Preferably adopt the depositing operation of good shape retention to form thinner laying 2, its material such as silica, TEOS (silica based materials of preparing as raw material CVD taking TEOS), silicon nitride, silicon oxynitride, amorphous carbon, diamond like carbon amorphous carbon (DLC) etc. and combination thereof.In a preferred embodiment, laying 2 is silica prepared by HDPCVD.The thickness of laying 2 for example only
As shown in Figure 5, in remaining gate trench 1G, form packed layer 3.On laying 2, form packed layer 3 by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputters, filled remaining gate trench completely and covered the laying 2 at substrate 1 top layer 1C top.Packed layer 3 preferably and laying 2 there is the material of higher Etch selectivity, for example, in the time that laying 2 is selected silica based materials, packed layer 3 is selected the materials such as silicon nitride, amorphous carbon, DLC, polysilicon, monocrystalline silicon, amorphous silicon, polycrystal SiGe, polycrystalline Si C, and vice versa.The techniques such as preferred PECVD, HDPCVD are to improve trench fill rate.It should be noted that packed layer 3 will form little jut on the position of original gate trench 1G, this be during due to filling groove material layer first in bottom, middle part engages the top engaging after a while of having arched upward.Packed layer 3 thickness for example
As shown in Figure 6, on packed layer 3, form the second photoetching offset plate figure PR2.Similar with PR1, form photoresist layer exposure afterwards, development formation PR2, it has covered the active area of following device, only around active area, leaves opening portion to expose packed layer 3.In top view (not shown), PR2 by be possessed ring-type or frame shape opening covering the figure of active area core, needing it according to Butut wiring can be rectangle, circle, ellipse, polygon etc.
As shown in Figure 7, taking PR2 as mask, etching exposes packed layer 3, laying 2 and the top layer 1C in opening successively, until expose the oxygen buried layer 1B of SOI substrate 1.The preferred anisotropic technique of etching, such as plasma dry etching, RIE etc.For example carbon of etching gas fluorine-based (CxHyFz, x is that 1～4, y is that 0～4, z is 1～8, triadic relation meet make to form saturated or undersaturated fluorohydrocarbon) gas, thereby by adjusting carbon fluorine, this controls etching rate and obtains steep pattern.For example, etching gas can comprise CF 4, CH 3f, CHF 3, CH 2f 2, C 4f 8, C 4f 6deng and combination and further comprise O 2, the oxidizing gas such as CO to be to regulate etch rate.Etching terminal can be adjusted by controlling etch rate and etch period, or in detection etch chamber, reaction product material, content are determined.
As shown in Figure 8, on whole device, form dielectric isolation layer 4.Form dielectric isolation layer 4 by techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputters, covered the opening portion outside packed layer 3 and active area completely.Dielectric isolation layer 4 materials are preferably the oxide such as silica, TEOS.
As shown in Figure 9, adopt CMP, return the technique planarization dielectric isolation layer 4 such as quarters, packed layer 3 is until expose laying 2, removed packed layer 3 tops dielectric isolation layer 4 part and only around active area, leave dielectric isolation layer 4 to be used as shallow trench isolation from (STI).
As shown in figure 10, carry out source and leak doping, to form source-drain area 1S/1D in the top layer 1C of packed layer 3 both sides.For example carry out Implantation, make ion pass thinner laying 2 to enter in top layer 1C by controlling Implantation Energy and dosage.The dopant injecting for example comprises Li, B, C, N, F, P, As, Be, Si, Ge, In, Ga etc. and combination thereof, for example 1～20KeV of Implantation Energy, and implantation dosage is 1E13～5E16cm for example -2.Now, due to stopping of packed layer 3, inject ion and fail the channel region 1CH of deep below.
As shown in figure 11, selective removal packed layer 3, exposes gate trench 1G again.Carry out selective etching method for the material of packed layer 3, for example hot phosphoric acid wet etching is removed silicon nitride material, HF base corrosive liquid (dHF, dBOE etc.) wet method is removed silica based materials (in the time that the laying 2 of its below is not silica material), oxygen plasma dry etching is removed the materials such as amorphous carbon, DLC, TMAH wet etching polysilicon, amorphous silicon etc., strong oxidizer (ozone, hydrogen peroxide) mixes with strong acid (sulfuric acid, nitric acid) removes SiGe, SiC etc.Selective etch technique does not corrode laying 2 completely or substantially, has protected source-drain area and channel region.Now, gate trench 1G bottom still has laying 2.
Preferably, as shown in figure 12, etching laying 2 bottoms, to expose channel region 1CH, have also been removed the part laying 2 at top layer 1C top simultaneously.For example remove the laying 2 of gate trench 1G bottom by dry etching, and retained part laying 2 with the grid curb wall as device at sidewall.In addition, also can adopt wet etching, for example HF base corrosive liquid is removed silica, controls corrosive liquid and joins this and etching temperature, makes the etch rate (this is preferably greater than 5:1 both etch rates) apparently higher than sidewall for the etch rate of bottom.In addition, in the time that laying 2 is (1～5nm) as thin as a wafer silica material of thermal oxidation or chemical oxidation or the formation of HDPCVD technique, also can not remove laying 2 parts of gate trench 1G bottom, thereby and this laying 2 be reduced to cross section defect as the boundary layer between high k material gate insulator and channel region 1CH after a while.
As shown in figure 13, in gate trench 1G, form gate stack 5.Preferably, by chemical oxidation or thermal oxidation at gate trench 1G top and sidewall form ultra-thin boundary layer 5A, for example silica material (when laying 2 is also thinner, for example, when 1～5nm, can be omitted a layer 5A; Or when laying 2 is thicker while being for example greater than 5nm, can preferably adopt process portion shown in Figure 12 to remove or the layer 2 of attenuate channel bottom, form a layer 5A simultaneously).Subsequently, adopt the techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxidation, chemical oxidation, evaporation, sputter to fill gate insulator 5B, work function regulating course 5C, resistance adjustment layer 5D in gate trench 1G bottom and sidewall successively.Gate insulator 5B is high k material, includes but not limited to comprise be selected from Hf0 2, HfSiO x, HfSiON, HfAlO x, HfTaO x, HfLaO x, HfAlSiO x, HfLaSiO xhafnium sill (wherein, each material is joined this and chemical valence difference according to multi-element metal component, and oxygen atom content x can rationally adjust, for example can be 1～6 and be not limited to integer), or comprise and be selected from ZrO 2, La 2o 3, LaAlO 3, TiO 2, Y 2o 3rare earth based high K dielectric material, or comprise Al 2o 3, with the composite bed of its above-mentioned material.Work function regulating course 5C material is M xn y, M xsi yn z, M xal yn z, M aal xsi yn z, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.Resistance adjustment layer 5D material can be polysilicon, poly-SiGe or metal, wherein metal can comprise metal simple-substance or the alloy of these metals and the nitride of these metals such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La, in addition can be doped with elements such as C, F, N, O, B, P, As with further regulatory work function.
As shown in figure 14, carry out CMP, return the techniques such as quarter with stacking 4 (4A～4D) of planarized gate until expose the top layer 1C of SOI substrate.Subsequently, can further adopt various conventional process to complete device manufacture.For example on device, deposit interlayer dielectric layer (ILD), in ILD, etching forms contact hole with source of exposure drain region, forms metal silicide to reduce contact resistance in contact hole, fills metal material and form contact plug on metal silicide.
Last device as shown in figure 14, comprises the source-drain area of gate stack both sides in the channel region, substrate top layer of gate stack below in gate stack in SOI substrate, SOI substrate top layer, substrate top layer.Wherein, all parts material and corresponding technological parameter describe in detail in method flow, do not repeat them here.
According to method, semi-conductor device manufacturing method of the present invention, in SOI top layer etching form gate trench and define below channel region, fill be limited with after gate trench source region and shallow trench isolation from, form thus ultra-thin SOI semiconductor device, realize the miniaturization of device, improved device performance.
Although with reference to one or more exemplary embodiments explanation the present invention, those skilled in the art can know without departing from the scope of the invention method that forms device architecture is made to various suitable changes and equivalents.In addition, can make and manyly may be suitable for the amendment of particular condition or material and not depart from the scope of the invention by disclosed instruction.Therefore, object of the present invention does not lie in and is limited to as the disclosed specific embodiment for realizing preferred forms of the present invention, and disclosed device architecture and manufacture method thereof are by all embodiment that comprise falling in people's scope of the invention.

Claims (10)

1. a method, semi-conductor device manufacturing method, comprising:
SOI substrate is provided, comprises substrate, oxygen buried layer and top layer;
In top layer, etching forms gate trench;
In gate trench, form laying and packed layer;
Etching packed layer, laying and top layer, form the opening that exposes oxygen buried layer, and the top layer in opening forms active area, the top layer constituting channel district of gate trench bottom;
In opening fill insulant form shallow trench isolation from.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, oxygen buried layer thickness 80～200nm, top layer thickness 30～100nm.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, laying material comprises silica, TEOS, silicon nitride, silicon oxynitride, amorphous carbon, diamond like carbon amorphous carbon (DLC) and combination thereof, thickness is 5～30nm; Packed layer material comprises silicon nitride, amorphous carbon, DLC, polysilicon, monocrystalline silicon, amorphous silicon, polycrystal SiGe, polycrystalline Si C and combination thereof, and thickness is 20～50nm.
4. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the channel region thickness that the top layer of gate trench bottom forms is 1～20nm.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, form shallow trench isolation from after further comprise:
Planarization shallow trench, packed layer are until expose laying;
Top layer dopant implant taking packed layer as mask to both sides, forms source-drain area;
Remove packed layer, again expose gate trench;
In gate trench, form gate stack.
6. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, gate stack comprises the gate insulator of the boundary layer of oxide material, high k material, work function regulating course and the resistance adjustment layer of nitride material.
7. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, wet etching is removed packed layer.
8. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, removes the laying of gate trench bottom, retains laying to be used as grid curb wall in gate trench sidewalls.
9. method, semi-conductor device manufacturing method as claimed in claim 5, wherein, forms gate stack and further comprises afterwards:
On device, form interlayer dielectric layer;
Etching interlayer dielectric layer forms the contact hole in source of exposure drain region;
In contact hole, form metal silicide;
On metal silicide, form contact plug.
10. a semiconductor device, comprising:
Substrate, has substrate, oxygen buried layer and top layer;
Gate stack, is arranged in the active area of top layer;
Channel region, is arranged in top layer gate stack below;
Source-drain area, is arranged in top layer gate stack both sides;
Shallow trench isolation from, be arranged in outside the active area of top layer.
CN201310184801.3A 2013-05-17 2013-05-17 Method, semi-conductor device manufacturing method Active CN104167358B (en)

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CN117690954A (en) * 2024-02-01 2024-03-12 合肥晶合集成电路股份有限公司 Semiconductor device and manufacturing method thereof

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CN117690954B (en) * 2024-02-01 2024-05-07 合肥晶合集成电路股份有限公司 Semiconductor device and manufacturing method thereof

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