CN104167356B - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- CN104167356B CN104167356B CN201410356503.2A CN201410356503A CN104167356B CN 104167356 B CN104167356 B CN 104167356B CN 201410356503 A CN201410356503 A CN 201410356503A CN 104167356 B CN104167356 B CN 104167356B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 43
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000011946 reduction process Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 230000003139 buffering effect Effects 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- -1 boron ion Chemical class 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002085 persistent effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an insulated gate bipolar transistor (IGBT) and a preparation method thereof. The IGBT includes an N-type base region, a P-type base region, a back P+ collecting electrode region, back N+ collecting electrode regions, an N+ emitting electrode region, a gate oxide layer, an emitting electrode, a P- buffer layer, a gate electrode and a collecting electrode. The N-type base region includes an N+ diffusion residual layer, an N- base region and an N+ buffer layer, which are sequentially laminated. Doping concentrations of the N+ diffusion residual layer and the N+ buffer layer gradually increase outwards from the boundaries of the N- base region. The N+ residual layer is arranged on the N- base region of the IGBT so that an ion doping concentration at an N-type front face is effectively improved and a current processing capability of the device is effectively improved and thus a switch-on saturation voltage drop is reduced; and the N+ buffer layer, the P- buffer layer, the back P+ collecting electrode region and the back N+ collecting electrode region, which are arranged sequentially on a back face from top to bottom, form an embedded NPN transistor so that a role of rapid channel of a minority carrier is played and the minority carrier is helped to scan the N- base region as soon as possible and thus switch-off time and switch-off loss of the device are reduced.
Description
Technical field
The present invention relates to field of high voltage power semiconductor devices, more particularly to a kind of insulated gate bipolar transistor
（IGBT）.
Background technology
As the compound full-control type power semiconductor of latest generation, insulated gate bipolar transistor（Insulated
Gate Bipolar Transistor, abbreviation IGBT）The advantage of power MOSFET and bipolar transistor is rolled into one, is had
Voltage is controlled, input impedance is big, driving power is little, control circuit is simple, switching loss is little, break-make speed is fast and operating frequency is high
The advantages of, it is the most representational product of internationally recognized Power Electronic Technique third time revolution, motor control, new forms of energy, height
Requisite power " core is dirty " in the middle of the fields such as ferrum, intelligent grid, electric automobile.It is little to switch to PDP, high ferro construction is arrived greatly,
The appearance for having IGBT figures without exception.IGBT power is big, high pressure, good energy-conserving effect the features such as determine which not still
Now, the mainstream technology of high side power semiconductor and within the following quite a long time, market prospect are very wide.
Since succeeding in developing from IGBT device, through the development of more than 30 years, its Technology and indices constantly change
Enter and improve, IGBT device developed into for the 6th generation via the first generation, its various performance parameter also reaches its maturity.But to height
In terms of the development of frequency high-power, still need to trade off between reduction on-state voltage drop and raising switching speed.
The difference that IGBT is distributed according to the back side, can be divided into punch（PT-IGBT）With it is non-punch（NPT-IGBT）Two
Plant structure.PT-IGBT can form N+ cushions and N- bases by epitaxially grown mode on the P+ substrates of Uniform Doped, so
Facad structure needed for making on N- bases again afterwards.It is hundreds of microns in the thickness of Uniform Doped that NPT-IGBT is then
Facad structure is first made in N- single crystalline substrates, forward direction is thinned to by N- bases by grinding the processes such as etching to the back side then
Thickness needed for blocking voltage, then back of the body P+ colelctor electrodes are overleaf formed by the way of ion implanting.It is distinguishing with PT-IGBT
It is that NPT types IGBT do not need thick-layer extension, is adapted to the IGBT of the high forward blocking voltage of manufacture, but due to no N+ cushions, because
The N- bases that this is reached needed for identical forward blocking voltage are thicker than PT-IGBT, and this can cause its forward conduction voltage drop ratio
PT-IGBT is bigger.But due to the colelctor electrode doping content of PT-IGBT it is too high so that its open when conductivity modulation effect phase
For NPT types will become apparent from, that is, when turning off, the hole in drift region can be more, therefore in turn off process, substantial amounts of hole
Can not be combined in time so as to which the turn-off time is longer, shut-off power consumption also can be bigger.For that purpose it is necessary to pass through minority carrier life time control
Technology so just makes the device amplitude of current tail and persistent period in turn off process all reduce reducing minority carrier life time, and
The transparent collector of NPT-IGBT can make few son reach rapidly metal electrode when off, therefore need not be using technologies such as irradiation
Reduce carrier lifetime.
Chinese patent application CN201010290339.1 discloses a kind of new construction of IGBT, as shown in Figure 1.Including
The colelctor electrode 10 at the back side, back of the body P+ collector areas 11, back of the body N+ cushions 12, N- bases 13, gate oxide 14, gate electrode 15, N+ are sent out
Emitter region 16, emitter stage 17, P+ emitter regions 18, N+ residual layers 19.The described structure of this invention is by being expanded using N+ in front
Scattered residual layer can effectively weaken the impact of JFET resistance, so that the conduction voltage drop of device is reduced, collector current is obtained
Improve.But the structure does not have any improvement for the turn-off time performance of device, does not have between conduction voltage drop and turn-off time
To form one effectively to trade off.
The content of the invention
The present invention provides a kind of insulated gate bipolar transistor and preparation method thereof, and which passes through to expand in front high temperature knot deeply
Dissipate, the diffusion residual layer of thinning rear formation again can effectively improve front carrier concentration；Overleaf embedded NPN pipes then rise
To the effect of the express passway of a few son, help few son scan out N- bases as soon as possible.Device is able in conduction voltage drop
A better trade-off is formed with the turn-off time, high-speed switch application is more suitable for.
A kind of insulated gate bipolar transistor, including N-type base, p-type base, back of the body P+ collector areas, N+ emitter regions, grid
Oxide layer, emitter stage, gate electrode and colelctor electrode；N+ diffusion residual layers that described N-type base includes stacking gradually, N- bases and
Outwards doping content gradually increases from the border starting of N- bases for N+ cushions, described N+ diffusion residual layers and N+ cushions,
Described insulated gate bipolar transistor is further provided with P- cushions, back of the body N+ collector areas, and described P- cushions are located at N+
Between cushion and back of the body P+ collector areas, described back of the body N+ collector areas are located at the two ends of back of the body P+ collector areas.
Described N- bases be doping content constant region, the forward blocking voltage of its thickness and doping content by needed for device
Decision, forward blocking voltage and its thickness positive correlation, it is negatively correlated with doping content.
Described N+ diffusions residual layer, if thickness is too small, the impurity doping concentration on surface can relatively low, conductance modulation act on compared with
Weak, it is relatively low that conduction voltage drop declines degree；If thickness is excessive, the impurity doping concentration on surface can be higher, and conductance modulation effect is relatively strong,
Although it is more that conduction voltage drop declines, this can also cause the reduction of forward blocking voltage, while also resulting in the turn-off time
Increase.Therefore, the thickness of N+ diffusions residual layer is advisable with 5 ~ 15um.
Described P- cushions, if thickness is too small, p-type collector region will be compressed, therefore colelctor electrode when turning on
Injection will reduce, therefore conduction voltage drop will increased；If thickness is excessive, p-type collector region will extend,
Now conductivity modulation effect will be strengthened, and conduction voltage drop will decrease, but on the other hand, due to what is be overleaf embedded in
The extension of NPN pipes base can limit the extraction of few son, and the turn-off time also can rise accordingly, thus the thickness of P- cushions with 1 ~
5um is advisable.
Present invention also offers the preparation method of the insulated gate bipolar transistor, including：
（1）The first N+ diffusion regions and the 2nd N+ diffusion regions are formed respectively by High temperature diffusion in n type single crystal silicon both sides；
（2）Respectively a N+ diffusion regions and the 2nd N+ diffusion regions are processed to form N+ diffusion residual layers and N+
Cushion；
（3）P-type base, N+ emitter regions, emitter stage are formed on N+ diffusion residual layers；
（4）P- cushions, back of the body P+ collector areas, back of the body N+ collector areas are formed by injecting ion on N+ cushions, P is carried on the back
Colelctor electrode is formed after+collector area and the metallization of back of the body N+ collector areas.
Insulated gate bipolar transistor of the present invention, due to its special preparation method：N+ spreads residual layer and N+ cushions
It is in the deeply knot diffusion of same step double-sided elevated temperature, and respectively through thinning and diffusion residual layer that formed；N+ on N- bases
Diffusion residual layer, improves the positive foreign ion doping content in N-type base, defines stronger conductance modulation effect, so as to
The conduction voltage drop of IGBT is significantly reduced, the current capacity of IGBT is improved.Meanwhile, by overleaf N+ cushions by one it is
The embedded NPN transistor that row processing step is formed, then serve the effect of the express passway of a few son, when off, helps
Few son can scan out N- bases as soon as possible, so as to reduce the turn-off time of device.
The N+ diffusion residual layers of insulated gate bipolar transistor of the present invention are same with the formation of the N+ cushions at the back side
After the knot diffusion deeply of secondary high temperature, then formed through reduction process such as grinding, polishings, these belong to original normal process, are not required to
Additional process step is wanted to be formed, so as to reduce manufacturing cost.And the diffusion residual layer at the back side is being formed after thinning
N+ cushions, the thickness of the N- bases that IGBT can be made required when identical forward blocking voltage is reached is less, and the back side
Embedded NPN transistor can reduce turn-off time and the turn-off power loss of device again.
Description of the drawings
Fig. 1 is the cross-sectional view of existing IGBT.
Fig. 2 is the cross-sectional view of IGBT of the present invention.
Fig. 3 a-3g are that IGBT manufacture processes of the present invention illustrate each section of structure；Wherein, Fig. 3 a are original N-type silicon chip
Profile, Fig. 3 b diffuse to form the profile behind two diffusion regions for wafer high temperature shown in Fig. 3 a；Fig. 3 c be silicon chip shown in Fig. 3 b just
Profile after face diffusion region is processed；Fig. 3 d are the profile after silicon chip shown in Fig. 3 c forms IGBT Facad structures；Fig. 3 e are
Structural representation after the processing of silicon chip back side diffusion region shown in Fig. 3 d；Fig. 3 f are that the injection ion of silicon chip back side shown in Fig. 3 e forms the back of the body
The profile of P+ collector areas；Fig. 3 g are that the back of the body P+ of silicon chip shown in Fig. 3 f collector areas back face metalization forms section after colelctor electrode
Figure.
Fig. 4 is the conduction voltage drop simulation comparison figure of traditional PT-IGBT devices and IGBT device of the present invention.
Fig. 5 is the shut-off simulation waveform of traditional PT-IGBT devices and IGBT device of the present invention.
Specific embodiment
In order that the technical problem to be solved, technical scheme and improvement effect become more apparent, below tie
Accompanying drawing is closed, the present invention is described in further detail.
As shown in Fig. 2 insulated gate bipolar transistor, including N-type base, p-type base 30, back of the body P+ collector areas 22, back of the body N
+ collector area 21, N+ emitter regions 28, gate oxide 26, emitter stage 29, gate electrode 27 and colelctor electrode 20；Described N-type base
It is made up of the N+ diffusion residual layers 31, N- bases 25 and the N+ cushions 24 that stack gradually, the insulated gate bipolar transistor is manufactured
Process is as shown in Figure 3 a-3g, specific as follows：
From crystal orientation as shown in Figure 3 a it is<100>N-type single crystalline substrate 32, its doping content be 4.2 × 1013cm-3,
Substrate thickness is 400um, is pressure demand according to forward blocking voltage（Such as 1700V, similarly hereinafter）, adjustable doping content is extremely
1×1013cm-3~1×1014cm-3。
As shown in Figure 3 b, N-type single crystalline substrate forms the N+ for stacking gradually Jing after a double-sided elevated temperature ties diffusion deeply and expands
Scattered area 34, N- bases 25 and the 2nd N+ diffusion regions 33, wherein 25 thickness of N- bases are adjustable according to the requirement of forward blocking voltage
To 100 ~ 300um, a N+ diffusion regions 34 and the 2nd N+ diffusion regions 33 are non-uniform doping.
As shown in Figure 3 c, N+ diffusion regions 34 are ground and the processing step such as polishing after form N+ diffusion residual layers 31,
This layer of THICKNESS CONTROL is within a few micrometers（It is preferred between 5 ~ 15um）.Thinning back substrate thickness is not less than 280um, can so protect
In card post-production, silicon chip is not easily broken.
As shown in Figure 3 d, spread in N+ and first pass through on residual layer 31 oxidation, the photoetching of P+ bases, etching, boron ion injection, expansion
Dissipate and wait processing step to form p-type base 30, then gate oxide 26 is formed in its surface oxidation, then deposited on gate oxide
Polysilicon forms gate electrode 27, then forms N+ transmittings by steps such as N+ emitter region photoetching, etching, arsenic ion injection, diffusions
Area 28, finally forms emitter stage 29, the front of such IGBT by depositing metal on N+ collector areas after photoetching, etching again
Structure is formed substantially.
As shown in Fig. 3 e, 3f, the N+ at the back side is defined after 33 Jing grinding back surfaces of the 2nd N+ diffusion regions and polishing etc. are thinning
Cushion 24, its THICKNESS CONTROL is in some tens of pm or so（8 ~ 20um is advisable）, first pass through the processing steps such as boron ion injection, diffusion
P- cushions 23 are formed respectively, and P- buffer layer thicknesses THICKNESS CONTROL is within a few micrometers（1 ~ 5um is advisable）, then noted by boron ion
The processing step such as enter, activate and forming back of the body P+ collector areas 22, then again by photoetching, etching, phosphonium ion injection, the technique such as spread
Step forms back of the body N+ collector areas 21.
As shown in figure 3g, after metal being deposited on back of the body P+ collector areas 22 with back of the body N+ collector areas 21 form colelctor electrode 20,
So far, a complete IGBT would have been completed.
Present invention uses device simulation software Medici has carried out simulating, verifying to present embodiment.
Fig. 4 compares the current processing disposal ability of traditional PT-IGBT and the present embodiment device, can from figure
Go out, 100A/cm is all in Collector Current Density2When, the conduction voltage drop of traditional PT-IGBT is 1.65V, the present embodiment device
Conduction voltage drop be 1.52V.The conduction voltage drop of the present embodiment device reduces 9%, this is because positive N+ residual layers increase
The electron concentration on surface, so as to improving conductivity modulation effect.
Fig. 5 compares the turn-off time of traditional PT-IGBT and the present embodiment device, it can be seen that with electric current
Density drops to 10% for basis for estimation, and the turn-off time of NFS-IGBT and traditional PT-IGBT is respectively 0.33u and 0.7us.
That is, the turn-off speed of NFS is faster than traditional PT-IGBT more than 1 times, conduction voltage drop is also better achieved with shut-off
The trade-off relation of time, is particularly well-suited to high-speed switch application.
Presently preferred embodiments of the present invention is the foregoing is only, that what is made within every the spirit and principles in the present invention appoints
What modification, equivalent and improvement etc., should be included within the scope of the present invention.
Claims (1)
1. a kind of preparation method of insulated gate bipolar transistor, it is characterised in that：
Described insulated gate bipolar transistor, including N-type base, p-type base, back of the body P+ collector areas, N+ emitter regions, grid oxygen
Change layer, emitter stage, gate electrode and colelctor electrode；Described N-type base includes N+ diffusion residual layers, N- bases and the N+ for stacking gradually
Outwards doping content gradually increases from the border starting of N- bases for cushion, described N+ diffusion residual layers and N+ cushions, its
It is characterised by：Described insulated gate bipolar transistor is further provided with P- cushions, back of the body N+ collector areas, described P- bufferings
Layer is located between N+ cushions and back of the body P+ collector areas, and described back of the body N+ collector areas are located at the two ends of back of the body P+ collector areas；Institute
The N- base doping concentration stated is constant；
Described preparation method includes：
（1）The first N+ diffusion regions and the 2nd N+ diffusion regions are formed respectively by High temperature diffusion in n type single crystal silicon both sides；
（2）Respectively a N+ diffusion regions and the 2nd N+ diffusion regions are processed to form N+ diffusion residual layers and N+
Cushion；
（3）P-type base, N+ emitter regions, emitter stage are formed on N+ diffusion residual layers；
（4）P- cushions, back of the body P+ collector areas, back of the body N+ collector areas are formed by injecting ion on N+ cushions, P+ collection is carried on the back
Colelctor electrode is formed after electrode district and the metallization of back of the body N+ collector areas；
Described N+ cushions are that the 2nd N+ diffusion regions are used obtained in reduction process.
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| CN105514148A (en) * | 2015-10-22 | 2016-04-20 | 温州墨熵微电子有限公司 | Insulated gate bipolar transistor |
| CN108630749A (en) * | 2018-05-09 | 2018-10-09 | 西安理工大学 | A kind of super-pressure silicon carbide thyristor and preparation method thereof |
| CN113451399A (en) * | 2021-06-02 | 2021-09-28 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239466B1 (en) * | 1998-12-04 | 2001-05-29 | General Electric Company | Insulated gate bipolar transistor for zero-voltage switching |
| CN102439725A (en) * | 2010-09-25 | 2012-05-02 | 浙江大学 | Insulated gate bipolar transistor(igbt) and method for manufacturing same |
| CN103872113A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Tunneling reverse-conducting IGBT and manufacturing method thereof |
| CN103872053A (en) * | 2013-12-17 | 2014-06-18 | 上海联星电子有限公司 | TI-IGBT device |
-
2014
- 2014-07-25 CN CN201410356503.2A patent/CN104167356B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6239466B1 (en) * | 1998-12-04 | 2001-05-29 | General Electric Company | Insulated gate bipolar transistor for zero-voltage switching |
| CN102439725A (en) * | 2010-09-25 | 2012-05-02 | 浙江大学 | Insulated gate bipolar transistor(igbt) and method for manufacturing same |
| CN103872113A (en) * | 2012-12-13 | 2014-06-18 | 中国科学院微电子研究所 | Tunneling reverse-conducting IGBT and manufacturing method thereof |
| CN103872053A (en) * | 2013-12-17 | 2014-06-18 | 上海联星电子有限公司 | TI-IGBT device |
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