CN104158534A - Voltage reduction conversion circuit for I/O interface - Google Patents
Voltage reduction conversion circuit for I/O interface Download PDFInfo
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- CN104158534A CN104158534A CN201310178635.6A CN201310178635A CN104158534A CN 104158534 A CN104158534 A CN 104158534A CN 201310178635 A CN201310178635 A CN 201310178635A CN 104158534 A CN104158534 A CN 104158534A
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- low pressure
- pmos pipe
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Abstract
The invention provides a voltage reduction conversion circuit for an I/O interface. The voltage reduction conversion circuit comprises the following parts: a high voltage inverter which is connected in series with a high voltage PMOS tube and a high voltage NMOS tube, wherein the grid electrodes of the high voltage NMOS tube and the high voltage PMOS tube are connected and are controlled by an input signal, the source electrode of the high voltage PMOS tube is connected with a high voltage power source, and the source electrode of the high voltage NMOS tube is connected with power ground; a clamp circuit whose power supply end, input end and output end are respectively connected with a low voltage power source, a first output end and a second output end; and a low voltage inverter which is connected in series with a low voltage PMOS tube and a low voltage NMOS tube, wherein the grid electrode, the source electrode and the drain electrode of the low voltage PMOS tube are respectively connected with a second output end, a low voltage power source and a third output end, the grid electrode, the source electrode and the drain electrode of the low voltage NMOS tube are respectively connected with the second output end, the power ground and the third output end, the power ground is lower than the low voltage power source, the low voltage power source is lower than the high voltage power source, and the voltage of the input signal varies between the voltage of the power ground and the voltage of the high voltage power source so that high voltage power received by the I/O interface can be converted to low voltage power needed by an actual circuit.
Description
Technical field
The invention belongs to logic circuit area, relate in particular to a kind of decompression converting circuit for I/O interface.
Background technology
Conventionally the interface between inside chip and external chip is called to I/O interface, the signal that can realize between external chip and inside chip by I/O interface is changed, and completes corresponding control function.As I/O interface can receive a high voltage source V
dDIOas I/O power supply, and side circuit needs a low power supply V
dD, as described V
dDIO> > V
dDtime, described V
dDIOstress application on these high-tension decompression converting circuits will transmitted.The most frequently used complementary metal oxide semiconductors (CMOS) of this decompression converting circuit (CMOS) inverter.
Fig. 1 shows the decompression converting circuit 10 of traditional simple digital signal of reception, it comprises CMOS inverter INV1 and the CMOS inverter INV2 of series connection, CMOS inverter INV1 is comprised of high voltage PMOS transistor PM1 and high pressure NMOS transistor NM1, the grid of PM1 and NM1 is connected to input A, the drain electrode of PM1 and NM1 is connected to output B, the source electrode of PM1 and V
dDIObe connected, the source electrode of NM1 and power supply ground V
sSbe connected; CMOS inverter INV2 is comprised of high voltage PMOS transistor PM2 and high pressure NMOS transistor NM1, and the grid of PM2 and NM2 is connected to output B, and the drain electrode of PM2 and NM2 is connected to output C, and the source electrode of PM2 meets V
dD, the source electrode of NM2 and power supply ground V
sSbe connected, the cut-in voltage of PM1 is V
tP, the cut-in voltage of PM2 is V
tN, | V
tP| and V
tNall be less than V
dDIOand be greater than V
dD.As input A access V
sStime, PM1 will be unlocked that output B end is pulled to V
dDIO, and NM1 will be closed, as described output B access V
dDIOtime, PM2 will be closed, and NM1 will be unlocked that output C is pulled down to V
sS; As input A access V
dDIOtime, NM1 will be unlocked output B will be pulled down to V
sS, and PM1 will be closed, as described output B access V
sStime, NM1 will be closed, due to the V of PM2
gS=| V
sS-V
dD| < | V
tP|, PM2 also will be closed, and described output C is V always
sS.
Therefore, described decompression converting circuit continues to receive direct current signal with a frequency, when the voltage of described input A switches from " 0-> 1 ", the voltage of described output B switches from " 1-> 0 ", because PM2 is now closed, cause the voltage of described output C unanimously to remain on V
sS, described decompression converting circuit cannot correctly convert the step-down of described I/O power supply to low power supply for use.Therefore the high voltage source V, receiving when I/O interface
dDIObe far longer than the low power supply V that side circuit needs
dDtime, need to provide a kind of new decompression converting circuit to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of decompression converting circuit for I/O interface, with the high voltage source that I/O interface is received, reduce and convert the required low-tension supply of side circuit to.
In order to address the above problem, the invention provides a kind of decompression converting circuit for I/O interface, comprising:
High pressure inverter, described high pressure inverter comprises high voltage PMOS pipe and high pressure NMOS pipe, the source electrode of described high voltage PMOS pipe is connected with the first output with high voltage source respectively with drain electrode, the grid of described high voltage PMOS pipe is controlled by an input signal, the source electrode of described high pressure NMOS pipe with drain electrode respectively with power supply be connected with described the first output, the grid of described high pressure NMOS pipe is connected with the grid of described high voltage PMOS pipe;
Clamp circuit, the feeder ear of described clamp circuit is connected with low-tension supply, and the input of described clamp circuit is connected with described the first output, and the output of described clamp circuit is connected with the second output; With
Low pressure inverter, described low pressure inverter comprises low pressure PMOS pipe and low pressure NMOS pipe, the source electrode of described low pressure PMOS pipe is connected with the 3rd output with described low-tension supply respectively with drain electrode, the grid of described low pressure PMOS pipe is connected with described the second output, the source electrode of described low pressure NMOS pipe with drain electrode respectively with described power supply be connected with described the 3rd output, the grid of described low pressure NMOS pipe is connected with the grid of described low pressure PMOS pipe
Wherein, described power supply ground is lower than described low-tension supply, and described low-tension supply is lower than described high voltage source, described input signal described power supply and described high voltage source between voltage swing.
Further, described high voltage PMOS pipe and high pressure NMOS pipe have respectively first threshold voltage and Second Threshold voltage, and the absolute value of described first threshold voltage and described Second Threshold voltage are all lower than described high voltage source and higher than described low-tension supply.
Further, described low pressure PMOS pipe and low pressure NMOS pipe have respectively the 3rd threshold voltage and the 4th threshold voltage, and the absolute value of described the 3rd threshold voltage and described the 4th threshold voltage are all lower than described low-tension supply and higher than described power supply ground.
Further, the step-down process of described decompression converting circuit is:
When described input signal is described high voltage source, described input signal is controlled described high voltage PMOS pipe cut-off, the conducting of described high pressure NMOS pipe simultaneously, exports the power supply that described high pressure inverter connects the source electrode of described high pressure NMOS pipe through described the first output;
When the input of described clamp circuit receives described power supply ground, described clamp circuit by the voltage of described the second output output be pulled down to the described power supply receiving equate;
The conducting of described low pressure PMOS pipe is controlled on described power supply ground simultaneously, described low pressure NMOS manages cut-off, the low-tension supply output that described low pressure inverter connects the grid of described low pressure PMOS pipe through described the 3rd output.
Further, the step-down process of described decompression converting circuit is:
When described input signal is described power supply ground, described input signal is controlled the conducting of described high voltage PMOS pipe, the cut-off of described high pressure NMOS pipe simultaneously, the described high voltage source output that described high pressure inverter connects the source electrode of described high voltage PMOS pipe through described the first output;
When the input of described clamp circuit receives described high voltage source, described clamp circuit is pulled to the voltage of described the second output output with the voltage of the feeder ear of described clamp circuit and equates;
Described low-tension supply is controlled the cut-off of described low pressure PMOS pipe simultaneously, described low pressure NMOS manages conducting, exports the power supply that described low pressure inverter connects the drain electrode of described low pressure NMOS pipe through described the 3rd output.
Further, described clamp circuit is high voltage intrinsic NMOS tube, the feeder ear that the grid end of described high voltage intrinsic NMOS tube is described clamp circuit, one end of the source/drain terminal of described high voltage intrinsic NMOS tube is the input of described clamp circuit, the output that the other end of the source/drain terminal of described high voltage intrinsic NMOS tube is described clamp circuit.
Compared with prior art, a kind of decompression converting circuit for I/O interface disclosed by the invention, because the described decompression converting circuit for I/O interface comprises high pressure inverter, described high pressure inverter comprises high voltage PMOS pipe and high pressure NMOS pipe, the source electrode of described high voltage PMOS pipe is connected with the first output with high voltage source respectively with drain electrode, the grid of described high voltage PMOS pipe is controlled by an input signal, the source electrode of described high pressure NMOS pipe with drain electrode respectively with power supply be connected with described the first output, the grid of described high pressure NMOS pipe is connected with the grid of described high voltage PMOS pipe, clamp circuit, the feeder ear of described clamp circuit is connected with low-tension supply, and the input of described clamp circuit is connected with described the first output, and the output of described clamp circuit is connected with the second output, with low pressure inverter, described low pressure inverter comprises low pressure PMOS pipe and low pressure NMOS pipe, the source electrode of described low pressure PMOS pipe is connected with the 3rd output with described low-tension supply respectively with drain electrode, the grid of described low pressure PMOS pipe is connected with described the second output, the source electrode of described low pressure NMOS pipe with drain electrode respectively with described power supply be connected with described the 3rd output, the grid of described low pressure NMOS pipe is connected with the grid of described low pressure PMOS pipe, wherein, described power supply ground is lower than described low-tension supply, described low-tension supply is lower than described high voltage source, described input signal described power supply and described high voltage source between voltage swing, so, when I/O interface receives high voltage source, the high voltage source that described decompression converting circuit can receive described input signal converts low-tension supply to through correctly step-down and uses for chip.
In addition, described clamp circuit is high voltage intrinsic NMOS tube, because the threshold voltage of described high voltage intrinsic NMOS tube is close to 0, when described high voltage intrinsic NMOS tube is realized clamper function, can make the voltage of the output output of described clamp circuit farthest approach described low-tension supply, thereby can guarantee to be subject to the low pressure inverter of described low-tension supply control correctly to export.
Accompanying drawing explanation
Fig. 1 is the decompression converting circuit structural representation in an embodiment of prior art;
Fig. 2 is the decompression converting circuit structural representation in one embodiment of the invention;
Fig. 3 is the decompression converting circuit input and output schematic diagram in one embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from alternate manner described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, so the present invention is not subject to the restriction of following public concrete enforcement.
Referring to Fig. 2, the invention provides a kind of decompression converting circuit 100 for I/O interface, the described decompression converting circuit 100 for I/O interface comprises high pressure inverter 200, clamp circuit 300 and low pressure inverter 400.
Concrete, described high pressure inverter 200 comprises high voltage PMOS pipe PM1 and high pressure NMOS pipe NM1, the source electrode of described high voltage PMOS pipe PM1 and drain electrode respectively with high voltage source V
dDIObe connected with the first output B, the grid of described high voltage PMOS pipe PM1 is connected with first input end A, and described first input end is controlled by an input signal IN, the source electrode of described high pressure NMOS pipe NM1 and drain electrode respectively with power supply ground V
sSbe connected with described the first output B, the grid of described high pressure NMOS pipe is connected with the grid of described high voltage PMOS pipe.Wherein, described high voltage PMOS pipe has first threshold voltage V
tP1, described high pressure NMOS pipe has Second Threshold voltage V
tN2, and described in | V
tP1| and V
tN1all higher than a low-tension supply V
dDand lower than described high voltage source V
dDIO.
Concrete, the feeder ear of described clamp circuit 300 and described low-tension supply V
dDbe connected, the input of described clamp circuit 300 is connected with described the first output B, and the output of described clamp circuit 300 is connected with the second output C.Described clamp circuit 300 is realized being analyzed as follows of clamper function:
When the input of described clamp circuit 300, compare with its feeder ear, the voltage receiving is lower than described low-tension supply V
dDtime, described clamp circuit 300 conductings, if the voltage of the output of described clamp circuit 300 and described low-tension supply V
dDequate, the voltage of the output of described clamp circuit 300 output be forced to drop-down, close with the voltage of the input of described clamp circuit 300; When the input of described clamp circuit 300, compare with its feeder ear, the voltage receiving is higher than described low-tension supply V
dDtime, described clamp circuit 300 conductings, if the voltage of the output of described clamp circuit 300 and described power supply ground V
sSequate, the voltage of the output of described clamp circuit 300 output is forced to draw, close with the voltage of the feeder ear of described clamp circuit 300.
Further, described clamp circuit is high voltage intrinsic NMOS tube NM0, the feeder ear that the grid end of described high voltage intrinsic NMOS tube is described clamp circuit, one end of the source/drain terminal of described high voltage intrinsic NMOS tube is the input of described clamp circuit, the output that the other end of the source/drain terminal of described high voltage intrinsic NMOS tube is described clamp circuit.Because the threshold voltage of described high voltage intrinsic NMOS tube is close to 0, when described high voltage intrinsic NMOS tube is realized clamper function, can make the voltage of the output output of described clamp circuit farthest approach described low-tension supply V
dDthereby, can guarantee to be subject to the low pressure inverter of described low-tension supply control correctly to export.
Concrete, described low pressure inverter 400 comprises low pressure PMOS pipe PM2 and low pressure NMOS pipe NM2, the source electrode of described low pressure PMOS pipe PM2 and drain electrode respectively with described low-tension supply V
dDbe connected with the 3rd output D, the grid of described low pressure PMOS pipe PM2 is connected with described the second output C, the source electrode of described low pressure NMOS pipe NM2 and drain electrode respectively with described power supply V
sSbe connected with described the 3rd output D, the grid of described low pressure NMOS pipe NM2 is connected with the grid of described low pressure PMOS pipe PM2, and described low-tension supply V
dDlower than described high voltage source V
dDIO, described input signal IN is at described power supply ground V
sSwith described high voltage source V
dDIObetween voltage swing.Wherein, described low pressure PMOS pipe PM2 has the 3rd threshold voltage V
tP2, described low pressure NMOS pipe NM2 has the 4th threshold voltage V
tN2, and | described V
tP2| and V
tN2all higher than described power supply ground V
sSand lower than described low-tension supply V
dD.
In conjunction with Fig. 3, how described decompression converting circuit is carried out to the process of step-down and analyzes as follows:
When described input signal IN is described high voltage source V
dDIOtime, the pressure reduction between the grid source electrode of described high voltage PMOS pipe PM1 is lower than V
tP1, described input signal IN controls described high voltage PMOS pipe PM1 cut-off, and the pressure reduction between the grid source electrode of described high pressure NMOS pipe NM1 is higher than V
tN1, described input signal IN controls described high pressure NMOS pipe NM1 conducting, and described high pressure inverter 200 is through described the first output B, by the described power supply ground V of the source electrode connection of described high pressure NMOS pipe NM1
sSoutput; Described clamp circuit 300 is realized clamper function, the described low-tension supply V of described the second output C output
dDbe pulled down to the described power supply ground V with described the first output B output
sSequate; When the voltage of described the second output C is described power supply ground V
sStime, the pressure reduction between the grid source electrode of described low pressure PMOS pipe PM2 is higher than V
tP2, described power supply ground V
sScontrol described low pressure PMOS pipe PM2 conducting, the pressure reduction between the grid source electrode of described low pressure NMOS pipe NM2 is lower than V
tN2, described power supply ground V
sScontrol described low pressure NMOS pipe NM2 cut-off, the low-tension supply V that described low pressure inverter 400 connects the grid of described low pressure PMOS pipe NM2 through described the 3rd output C
dDoutput.
When described input signal IN is described power supply ground V
sStime, the pressure reduction between the grid source electrode of described high voltage PMOS pipe PM1 is higher than V
tP1, described input signal IN controls described high voltage PMOS pipe PM1 conducting, and the pressure reduction between the grid source electrode of described high pressure NMOS pipe NM1 is lower than V
tN1, described input signal IN controls described high pressure NMOS pipe NM1 cut-off, and described high pressure inverter 200 is through described the first output B, by the described high voltage source V of the source electrode connection of described high voltage PMOS pipe PM1
dDIOoutput; Described clamp circuit 300 is realized clamper function, the described power supply ground V of described the second output C output
sSbe pulled to the described low-tension supply V exporting with the feeder ear of described clamp circuit 300
dDequate; When the voltage of described the second output C is described low-tension supply V
dDtime, the pressure reduction between the grid source electrode of described low pressure PMOS pipe PM2 is lower than V
tP2, described low-tension supply V
dDcontrol described low pressure PMOS pipe PM2 cut-off, the pressure reduction between the grid source electrode of described low pressure NMOS pipe NM2 is higher than V
tN2, described low-tension supply V
dDcontrol described low pressure NMOS pipe NM2 conducting, the power supply ground V that described low pressure inverter 400 connects the drain electrode of described low pressure NMOS pipe NM2 through described the 3rd output C
sSoutput.
As can be seen here, the present invention is when high voltage source that I/O interface receives, and the high voltage source that described decompression converting circuit can receive described input signal converts low-tension supply to through correctly step-down and uses for chip.
Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that the claims in the present invention were defined.
Claims (6)
1. for a decompression converting circuit for I/O interface, comprising:
High pressure inverter, described high pressure inverter comprises high voltage PMOS pipe and high pressure NMOS pipe, the source electrode of described high voltage PMOS pipe is connected with the first output with high voltage source respectively with drain electrode, the grid of described high voltage PMOS pipe is controlled by an input signal, the source electrode of described high pressure NMOS pipe with drain electrode respectively with power supply be connected with described the first output, the grid of described high pressure NMOS pipe is connected with the grid of described high voltage PMOS pipe;
Clamp circuit, the feeder ear of described clamp circuit is connected with low-tension supply, and the input of described clamp circuit is connected with described the first output, and the output of described clamp circuit is connected with the second output; With
Low pressure inverter, described low pressure inverter comprises low pressure PMOS pipe and low pressure NMOS pipe, the source electrode of described low pressure PMOS pipe is connected with the 3rd output with described low-tension supply respectively with drain electrode, the grid of described low pressure PMOS pipe is connected with described the second output, the source electrode of described low pressure NMOS pipe with drain electrode respectively with described power supply be connected with described the 3rd output, the grid of described low pressure NMOS pipe is connected with the grid of described low pressure PMOS pipe
Wherein, described power supply ground is lower than described low-tension supply, and described low-tension supply is lower than described high voltage source, described input signal described power supply and described high voltage source between voltage swing.
2. the decompression converting circuit for I/O interface as claimed in claim 1, it is characterized in that, described high voltage PMOS pipe and high pressure NMOS pipe have respectively first threshold voltage and Second Threshold voltage, and the absolute value of described first threshold voltage and described Second Threshold voltage are all lower than described high voltage source and higher than described low-tension supply.
3. the decompression converting circuit for I/O interface as claimed in claim 1, it is characterized in that, described low pressure PMOS pipe and low pressure NMOS pipe have respectively the 3rd threshold voltage and the 4th threshold voltage, and the absolute value of described the 3rd threshold voltage and described the 4th threshold voltage are all lower than described low-tension supply and higher than described power supply ground.
4. the decompression converting circuit for I/O interface as claimed in claim 1, is characterized in that, the step-down process of described decompression converting circuit is:
When described input signal is described high voltage source, described input signal is controlled described high voltage PMOS pipe cut-off, the conducting of described high pressure NMOS pipe simultaneously, exports the power supply that described high pressure inverter connects the source electrode of described high pressure NMOS pipe through described the first output;
When the input of described clamp circuit receives described power supply ground, described clamp circuit by the voltage of described the second output output be pulled down to the described power supply receiving equate;
The conducting of described low pressure PMOS pipe is controlled on described power supply ground simultaneously, described low pressure NMOS manages cut-off, the low-tension supply output that described low pressure inverter connects the grid of described low pressure PMOS pipe through described the 3rd output.
5. the decompression converting circuit for I/O interface as claimed in claim 1, is characterized in that, the step-down process of described decompression converting circuit is:
When described input signal is described power supply ground, described input signal is controlled the conducting of described high voltage PMOS pipe, the cut-off of described high pressure NMOS pipe simultaneously, the described high voltage source output that described high pressure inverter connects the source electrode of described high voltage PMOS pipe through described the first output;
When the input of described clamp circuit receives described high voltage source, described clamp circuit is pulled to the voltage of described the second output output with the voltage of the feeder ear of described clamp circuit and equates;
Described low-tension supply is controlled the cut-off of described low pressure PMOS pipe simultaneously, described low pressure NMOS manages conducting, exports the power supply that described low pressure inverter connects the drain electrode of described low pressure NMOS pipe through described the 3rd output.
6. the decompression converting circuit for I/O interface as described in any one in claim 1 to 5, it is characterized in that, described clamp circuit is high voltage intrinsic NMOS tube, the feeder ear that the grid end of described high voltage intrinsic NMOS tube is described clamp circuit, one end of the source/drain terminal of described high voltage intrinsic NMOS tube is the input of described clamp circuit, the output that the other end of the source/drain terminal of described high voltage intrinsic NMOS tube is described clamp circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310178635.6A CN104158534B (en) | 2013-05-14 | 2013-05-14 | For the decompression converting circuit of I/O interfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310178635.6A CN104158534B (en) | 2013-05-14 | 2013-05-14 | For the decompression converting circuit of I/O interfaces |
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| Publication Number | Publication Date |
|---|---|
| CN104158534A true CN104158534A (en) | 2014-11-19 |
| CN104158534B CN104158534B (en) | 2017-06-23 |
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| CN201310178635.6A Active CN104158534B (en) | 2013-05-14 | 2013-05-14 | For the decompression converting circuit of I/O interfaces |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049028A (en) * | 2015-08-20 | 2015-11-11 | 上海华力微电子有限公司 | Power-on detecting circuit for preventing uncertainty state of I/O circuit |
| CN106874231A (en) * | 2015-12-14 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of total wire maintainer and electronic installation |
| CN107181482A (en) * | 2016-03-09 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | input and output receiving circuit |
| CN108169543A (en) * | 2016-12-07 | 2018-06-15 | 中芯国际集成电路制造(上海)有限公司 | High-voltage detecting circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007089A1 (en) * | 2003-07-08 | 2005-01-13 | Rohm Co., Ltd. | Step-up/step-down DC-DC converter and portable device employing it |
| CN1922786A (en) * | 2004-01-21 | 2007-02-28 | 株式会社瑞萨科技 | Voltage clamp circuit, switching power supply apparatus, semiconductor integrated circuit device, and voltage level converting circuit |
| CN101635165A (en) * | 2008-07-21 | 2010-01-27 | 上海华虹Nec电子有限公司 | Decoding circuit using low-voltage MOS transistors to realize high-voltage resistance, and realization method |
| CN102437730A (en) * | 2011-12-24 | 2012-05-02 | 西安启芯微电子有限公司 | Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter |
| CN102893320A (en) * | 2010-12-08 | 2013-01-23 | 上海贝岭股份有限公司 | Level shift circuit |
-
2013
- 2013-05-14 CN CN201310178635.6A patent/CN104158534B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050007089A1 (en) * | 2003-07-08 | 2005-01-13 | Rohm Co., Ltd. | Step-up/step-down DC-DC converter and portable device employing it |
| CN1922786A (en) * | 2004-01-21 | 2007-02-28 | 株式会社瑞萨科技 | Voltage clamp circuit, switching power supply apparatus, semiconductor integrated circuit device, and voltage level converting circuit |
| CN101635165A (en) * | 2008-07-21 | 2010-01-27 | 上海华虹Nec电子有限公司 | Decoding circuit using low-voltage MOS transistors to realize high-voltage resistance, and realization method |
| CN102893320A (en) * | 2010-12-08 | 2013-01-23 | 上海贝岭股份有限公司 | Level shift circuit |
| CN102437730A (en) * | 2011-12-24 | 2012-05-02 | 西安启芯微电子有限公司 | Anti-ringing circuit applied to high-voltage boosting type DC-DC (Direct Current to Direct Current) converter |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049028A (en) * | 2015-08-20 | 2015-11-11 | 上海华力微电子有限公司 | Power-on detecting circuit for preventing uncertainty state of I/O circuit |
| CN105049028B (en) * | 2015-08-20 | 2018-10-16 | 上海华力微电子有限公司 | A kind of power on detection circuit for preventing I/O circuits from not knowing state |
| CN106874231A (en) * | 2015-12-14 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | A kind of total wire maintainer and electronic installation |
| CN106874231B (en) * | 2015-12-14 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | Bus retainer and electronic device |
| CN107181482A (en) * | 2016-03-09 | 2017-09-19 | 中芯国际集成电路制造(上海)有限公司 | input and output receiving circuit |
| CN107181482B (en) * | 2016-03-09 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Input/output receiving circuit |
| CN108169543A (en) * | 2016-12-07 | 2018-06-15 | 中芯国际集成电路制造(上海)有限公司 | High-voltage detecting circuit |
| CN108169543B (en) * | 2016-12-07 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | High voltage detection circuit |
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|---|---|
| CN104158534B (en) | 2017-06-23 |
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