CN104135276A - Radio frequency transmitting device - Google Patents
Radio frequency transmitting device Download PDFInfo
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- CN104135276A CN104135276A CN201410293624.7A CN201410293624A CN104135276A CN 104135276 A CN104135276 A CN 104135276A CN 201410293624 A CN201410293624 A CN 201410293624A CN 104135276 A CN104135276 A CN 104135276A
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Abstract
The invention discloses a radio frequency transmitting device. The radio frequency transmitting device comprises a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator, wherein the twin voltage-controlled oscillator comprises a first voltage-controlled oscillator and a second voltage-controlled oscillator having the same structures, wherein when the twin voltage-controlled oscillator is in a receiving mode, the first voltage-controlled oscillator and the second voltage-controlled oscillator are coupled with each other to form an orthogonal voltage-controlled oscillator, and the orthogonal voltage-controlled oscillator constructs a phase-lock loop with the phase frequency detector, the charge pump and the loop filter to generate orthogonal carriers for receiving information; and when the twin voltage-controlled oscillator is in a transmitting mode, the first voltage-controlled oscillator constructs a phase-lock loop with the phase frequency detector, the charge pump and the loop filter, and the second voltage-controlled oscillator is used for performing frequency modulation on transmitted data. By adopting the radio frequency transmitting device, the stability of carrier frequencies can be kept at a high data transmission rate, and the frequency hopping locking time is very short.
Description
Technical field
The present invention relates to twireless radio-frequency communication circuit engineering field, particularly for needs transmitted at high speed, require the radio frequency communications circuitry field of energy-efficient.
Background technology
Along with the fast development of wireless communication technology, the demand of low-power consumption high-speed radio-frequency emitter is also increased day by day.Such as need to transmit the application scenario of high data rate at Wireless capsule endoscope and neural recording etc.
Due to the permanent envelope trait of shift keying modulation, make in transmitter, to adopt high efficiency nonlinear power amplifier, therefore this modulation system is widely used in the occasion that requires low-power consumption transmitting.
Can be used at present frequency shift keyed transmitter mainly contains based on mixer architecture with based on phase-locked loop structures.Transmitter flexibility based on mixer architecture is high, can be used for different types of modulation, but this structure needs digital to analog converter and the frequency mixer of high power consumption, is therefore not suitable for low-power consumption application.
For the transmitter based on phase-locked loop structures, roughly there are at present four kinds of implementations.One is that modulation signal is added on frequency divider, and this method is simple and accuracy is high, but for modulation signal, phase-locked loop presents low-frequency filter characteristics, and therefore the data rate of transmitting is limited to the loop bandwidth of phase-locked loop.The second way is the modulation of closed loop voltage controlled oscillator, and this method is directly added to modulating data on blocked voltage controlled oscillator, and in this case, phase-locked loop presents high-pass filtering characteristic for modulation signal, and therefore the low-frequency component of modulation signal can be destroyed.The third mode is that modulation signal is added on frequency divider and voltage controlled oscillator simultaneously, 2 modulation that are otherwise known as of this modulate emission mode, this modulation system combines the advantage of two kinds of modes above, ideally, if high path and low path mate completely, the data rate that transmits so will not be subject to the restriction of PLL loop bandwidth.But for the requirement of two signal path gains and bandwidth match, the design complexities of system and power consumption are increased.The 4th kind of mode is the modulation of open loop voltage controlled oscillator, first this modulation system is locked in voltage controlled oscillator in certain transmitting carrier frequency by phase-locked loop, then disconnect phase-locked loop, modulation signal is directly added on voltage controlled oscillator, and transmit data rate will be broken away from the restriction of PLL loop bandwidth like this.But due in emission process, phase-locked loop is in open loop situations, the easy frequency of occurrences drift phenomenon of the frequency of oscillation of voltage controlled oscillator, frequency drift is generally by Leakage Current, external disturbance and variation of ambient temperature cause.
Summary of the invention
(1) technical problem that will solve
Main purpose of the present invention is to provide a kind of Wireless RF transmitter of high-speed low-power-consumption, makes to launch high data rate signal, can keep again carrier wave stable, can be applicable in the application scenario of the high data rates such as medical electronics.
(2) summary of the invention
The invention provides a kind of Wireless RF transmitter, it comprises: phase frequency detector, charge pump, loop filter and two born of the same parents' voltage controlled oscillator;
Wherein, described pair of born of the same parents' voltage controlled oscillator comprises the first voltage controlled oscillator and the second voltage controlled oscillator that structure is identical, wherein, when described pair of born of the same parents' voltage controlled oscillator is during in receiving mode, described the first voltage controlled oscillator and the second voltage controlled oscillator intercouple, form orthogonal voltage-controlled vibrator, described orthogonal voltage-controlled vibrator and described phase frequency detector, charge pump, loop filter form phase-locked loop, produce the quadrature carrier that reception information is used; When described pair of born of the same parents' voltage controlled oscillator is during in emission mode, described the first voltage controlled oscillator and described phase frequency detector, charge pump, loop filter form phase-locked loop, and described the second voltage controlled oscillator is for carrying out frequency modulation(FM) to transmitting data.
Wherein, described pair of born of the same parents' voltage controlled oscillator also comprises: the first coupling branch road and the second coupling branch road, wherein, the output of described the first voltage controlled oscillator is connected with the input of described the first coupling branch road and the second coupling branch road respectively, and the output of described the second voltage controlled oscillator is connected with the input of described the first coupling branch road and the second coupling branch road respectively.
Wherein, when described first coupling branch road and second coupling branch road add after electric current, described the first voltage controlled oscillator and the second voltage controlled oscillator are coupled and are formed orthogonal voltage-controlled vibrator by described the first coupling branch road and the second coupling branch road, and described pair of born of the same parents' voltage controlled oscillator switches to receiving mode;
When disconnecting after the electric current of the first coupling branch road and the second coupling branch road, described the first voltage controlled oscillator and the coupling of the second voltage controlled oscillator solution, described pair of born of the same parents' voltage controlled oscillator switches to emission mode.
Wherein, the frequency of oscillation of described the first voltage controlled oscillator and the second voltage controlled oscillator is subject to the control of first frequency control signal.
Wherein, described phase frequency detector, charge pump and loop filter regulate described first frequency control signal according to the value of feedback of the output frequency of described pair of born of the same parents' voltage controlled oscillator.
It also comprises described device:
Frequency preset module, it carries out preset to described pair of born of the same parents' pressuring controlling oscillator frequency for described phase-locked loop when the frequency hopping.
Wherein, described frequency preset module changes described first frequency control signal according to the preset control word of first frequency.
Wherein, the frequency of oscillation of described the first voltage controlled oscillator and the second voltage controlled oscillator is also subject to the control of the preset control word of second frequency.
Wherein, the preset control word of described first frequency and the preset control word of second frequency are that the target frequency that will jump to according to described pair of born of the same parents' voltage controlled oscillator sets in advance.
Described device also comprises: digital processing unit, it samples to the output frequency of described pair of born of the same parents' voltage controlled oscillator in the time powering on, to obtain the output frequency of described pair of born of the same parents' voltage controlled oscillator and the corresponding relation of the preset control word of described first frequency and the preset control word of second frequency.
(3) beneficial effect
Can find out from technique scheme, the present invention has following beneficial effect:
1, radio-frequency (RF) transmitter provided by the invention, all circuit can be integrated with standard CMOS process single-chip, and system configuration is simple, meets the low cost requirement of practical application, transmitter is realized high data rate communication with low power consumption, has solved the low-power consumption problem in related application.
2, radio-frequency (RF) transmitter provided by the invention, owing to having adopted a kind of pair of born of the same parents' voltage controlled oscillator in phase-locked loop, phase-locked loop can be operated in two kinds of different patterns: receiving mode and emission mode.In the time of receiving mode, two born of the same parents' voltage controlled oscillators, in corss coupling syntype, can provide quadrature carrier for receiver; In the time of emission mode, two born of the same parents' voltage controlled oscillators are removed coupling, independent vibration.Can reduce like this transceiver entirety hardware spending, save area, reduce the cost.
3, radio-frequency (RF) transmitter provided by the invention, in the time of emission mode, two born of the same parents' voltage controlled oscillators are removed coupling, independent vibration, one of them voltage controlled oscillator (iVCO) is locked by phase-locked loop, and another one voltage controlled oscillator (qVCO) is not locked, and modulation signal is added on qVCO, transmit data rate has been broken away from the restriction of PLL loop bandwidth like this, can keep the stable of transmitting carrier frequency simultaneously.
4, radio-frequency (RF) transmitter provided by the invention, the preset technology of proportion not only can shorten the locking time of phase-locked loop greatly, and can reduce output load capacitance and do not mate the impact on voltage controlled oscillator frequency of oscillation, has improved the accuracy of frequency.
5, RF receiving/transmission device provided by the invention, its variable gain power amplifier is to be made up of power drive level and power-amplifier stage.Its power drive level adopts AB class circuit structure, and power-amplifier stage adopts category-B complementary push-pull formula structure, and this structure, in meeting the linear requirement of power amplifier, has reduced system power dissipation.The input of power drive level adopts inductance coupling, improves transmitter gain, and in the time inputting without radiofrequency signal, only has power drive level to consume power consumption, reduces transmitting power consumption, improves emission effciency.
6, radio-frequency (RF) transmitter provided by the invention is particularly suitable in the wireless communication field that needs high-speed low-power-consumption transmitting application.
Brief description of the drawings
Fig. 1 is a kind of high-speed radio radio-frequency (RF) transmitter provided by the invention;
Fig. 2 is the circuit diagram of frequency preset module 13 provided by the invention;
Fig. 3 is the circuit diagram of provided by the invention pair of born of the same parents' voltage controlled oscillator 14;
Fig. 4 is the circuit structure diagram of power amplifier 16 provided by the invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
Fig. 1 shows the system block diagram of the high-speed radio radio-frequency (RF) transmitter based on phase-locked loop provided by the invention, and this emitter is for launching the digital baseband signal that adopts shift keying modulation.As shown in Figure 1, this radio-frequency (RF) transmitter comprises: phase frequency detector 10, charge pump 11, loop filter 12, frequency preset module 13, the two born of the same parents' voltage controlled oscillators 14 of restructural, buffer 15, power amplifier 16, redundant module 17, programmable frequency divider 18, dual-mode frequency divider 19, digital processing unit 20 and nonvolatile memory 21.
Wherein, the first input end of described phase frequency detector 10 receives the reference signal f of outside input
ref, the second input receives the output signal f of programmable frequency divider 18
div, the first output UP is connected with the input of charge pump 11 with the second output DN.Described phase frequency detector 10 is for the reference signal f to input
refoutput signal f with programmable frequency divider 18
divfrequency and phase place compare, as reference signal f
reffrequency be greater than the output signal f of programmable frequency divider 18
divfrequency time, the first output UP of phase frequency detector 10 produces positive pulse, and the signal of the second output DN output is low level.As reference signal f
reffrequency be less than the output signal f of programmable frequency divider 18
divfrequency time, the second output DN of phase frequency detector 10 produces positive pulse, and the signal of the first output UP output is low level.As reference signal f
reffrequency equal the output signal f of programmable frequency divider 18
divfrequency and phase difference are 0 o'clock, the first output UP and and the signal of the second output DN output be all low level.
The input of charge pump 11 is connected with the first output UP and the second output DN of phase frequency detector 10, and output is connected with the input of loop filter 12; Described charge pump 11 is subject to the control of phase frequency detector 10 output signals, and in the time that the first output UP of phase frequency detector 10 produces positive pulse, charge pump 11 carries out charging operations, and its output produces charging current.In the time that the second output DN of phase frequency detector 10 produces positive pulse, charge pump 11 carries out discharge operation, and its output produces discharging current.In the time that the first output UP of phase frequency detector 10 and the second output DN are low level, charge pump 11 neither charges and does not also discharge, and its output current is 0.
The input of loop filter 12 is connected with the output of charge pump 11, and output is connected with the input of frequency preset module 13.Described loop filter 12 is for the charging and discharging currents of charge pump 11 being changed into the control voltage Va of control frequency preset module 13, and in the time that charge pump 11 produces charging current, the control voltage Va of loop filter 12 outputs increases.In the time that charge pump 11 produces discharging current, the control voltage Va of loop filter 12 outputs reduces.In the time that charge pump 11 outputs neither produce charging current and also do not produce discharging current, loop filter 12 output control voltage Va keep constant.Wherein, the variation of described control voltage Va directly affects the variation of the output frequency of described pair of born of the same parents' voltage controlled oscillator 14,, in phase-locked loop, when described Va increases, causes described control voltage Vc to reduce, and when Va reduces, described Vc increases.
The input of frequency preset module 13 and the output Va of loop filter 12 and the first output C[5:0 of digital processing unit 20] be connected, the preset control word C[5:0 of first frequency exporting for receiving analog control voltage Va that loop filter 12 exports and digital processing unit 20], its output is connected with the input of the two born of the same parents' voltage controlled oscillators 14 of restructural, and the control voltage Vc of its output controls the frequency change of the two born of the same parents' voltage controlled oscillators 14 of restructural.The output control voltage Vc of frequency preset module 13 is by simulating control end Va and digital control end C[5:0] jointly determine, namely the output frequency of the two born of the same parents' voltage controlled oscillators 14 of restructural is by simulating control end Va and the first preset digital control word C[5:0] jointly determine.Transmitter is in the time powering on, keep in the certain situation of Va voltage, to the preset control word C[5:0 of different first frequencies] the value sampling output frequency that obtains two born of the same parents' voltage controlled oscillator 14 correspondences of restructural draws C[5:0 thus] with the corresponding relation of two born of the same parents' voltage controlled oscillator 14 output frequencies of restructural, in the time that phase-locked loop frequency need to jump to target frequency, calculate by digital processing unit the C[5:0 that target frequency is corresponding] value, then be directly added in frequency preset module 13, thereby the output frequency of the two born of the same parents' voltage controlled oscillators 14 of restructural is set to target frequency, thereby shortening phase lock loop lock on time.
The two input Vc of born of the same parents' voltage controlled oscillator 14 of restructural and the second output P[2:0 of frequency preset module 13 outputs, digital processing unit 20], external voltage VB1 and emission port TX-DATA be connected, output is connected with the input of buffer 15.Input Vc is used for controlling the two born of the same parents' voltage controlled oscillator 14 varactor capacitance variation of restructural, changes thereby control its frequency of oscillation.The preset control word P[2:0 of second frequency of the second output output of described digital processing unit 20] change for controlling two born of the same parents' voltage controlled oscillator 14 capacitor arrays of restructural, thus the frequency of change oscillator work.External voltage VB1 is for controlling the mode of operation of the two born of the same parents' voltage controlled oscillators 14 of restructural, and in the time that VB1 is low level, the two born of the same parents' voltage controlled oscillators 14 of restructural are operated in emission mode, for launching digital modulation signals; In the time that VB1 is high level, the two born of the same parents' voltage controlled oscillators 14 of restructural are operated in receiving mode, are equivalent to a quadrature oscillator, output orthogonal carrier wave.Input TX-DATA for being added to digital modulation signals the two born of the same parents' voltage controlled oscillators 14 of restructural under emission mode.
Buffer 15 comprises two buffers 150 and 151, the input of the first buffer 150 is connected with the output of q oscillator in the two born of the same parents' voltage controlled oscillators 14 of restructural, its output is connected with power amplifier 16, the input of the second buffer 151 is connected with the output of i oscillator in the two born of the same parents' voltage controlled oscillators 14 of restructural, and its output is connected with dual-mode frequency divider 19.Buffer 15 is for isolating the two born of the same parents' voltage controlled oscillators 14 of restructural and power amplifier 16 and dual-mode frequency divider 19.
The input of power amplifier 16 is connected with the output of the first buffer 150, and output is connected with antenna; Power amplifier 16 is for amplifying the oscillator signal that comes from the two born of the same parents' voltage controlled oscillator 14 q oscillators of restructural of exporting from the first buffer 150 and passing through antenna transmission;
Redundant module 17 is connected to the centre of the second buffer 151 and dual-mode frequency divider 19, its input load electric capacity equates with the input load electric capacity of power amplifier 16, the load capacitance that makes like this buffer 150 see with buffer 151 is consistent, and then makes the load capacitance that in the two born of the same parents' voltage controlled oscillators 14 of restructural, i oscillator is seen with q oscillator consistent.
The input of dual-mode frequency divider 19 is connected with the second buffer 151 outputs, for the oscillator signal of two born of the same parents' voltage controlled oscillator 14 first oscillators of the restructural of receiving from the second buffer 151 is carried out to first frequency division, and exports programmable frequency divider 18 to;
The input of programmable frequency divider 18 is connected with dual-mode frequency divider 19 outputs, and for by further the output signal of dual-mode frequency divider 19 frequency division, the signal after frequency division exports phase frequency detector 10 and digital processing unit 20 to.The signal that outputs to phase frequency detector 10 for external reference signal f
refcarry out frequency and phase bit comparison, form feedback control loop.Output to the signal of digital processing unit 20 for the work clock of digital processing unit.
The input of digital processing unit 20 is connected with the output of nonvolatile memory 21, and receive the outside programmed configurations data of inputting, its output control frequency preset module 13, the two born of the same parents' voltage controlled oscillators 14 of restructural, programmable frequency divider 18, nonvolatile memory 21.Digital processing unit 20 in the time of chip power to the calculating of sampling of the output frequency of dual-mode frequency divider 19, draw frequency of oscillation and the first preset digital control word C[5:0 of the two born of the same parents' voltage controlled oscillators 14 of restructural] and the preset control word P[2:0 of second frequency] corresponding relation, then by preset first frequency corresponding different frequencies of oscillation control word C[5:0] and the preset control word P[2:0 of second frequency] be stored in nonvolatile memory 21, for frequency preset module 13 being carried out to frequency preset in the time of frequency hopping, also can input C[5:0 by outside] and P[2:0] be configured.Described frequency preset control word comprises that described digital processing unit 20 also produces the frequency dividing ratio of Digital Signals programmable frequency divider 18 for the preset control word of second frequency of the capacitor array in the preset control word of first frequency of the current source of control frequency preset module 13 and the two born of the same parents' voltage controlled oscillators 14 of control restructural; Described frequency preset control word exports nonvolatile memory 21 to and stores;
Input, the output of nonvolatile memory 21 are connected with input, the output of digital processing unit 16; The preset control signal C[5:0 of first frequency that it calculates for storing described digital processing unit 20] and the preset control signal P[2:0 of second frequency].
Based on a kind of high-speed radio radio-frequency (RF) transmitter system block diagram described in Fig. 1, Fig. 2 has provided the circuit diagram of frequency preset module 13 provided by the invention.As shown in Figure 2, frequency preset module 13 is carried out during for phase-locked loop frequency hopping preset to pressuring controlling oscillator frequency, comprise a resistance R 1 and multiple metal-oxide-semiconductor M0, M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14.The predetermined frequency control voltage Va that the grid of M0 is exported with loop filter 12 is connected, and M0 source electrode is connected with supply voltage VDD, and M0 drain electrode is connected with grid and resistance R 1 one end of M14, metal-oxide-semiconductor M1, M2, M3, M4, M5, the grid of M6 is connected with bias voltage Vb and supply voltage VDD respectively with source electrode, its drain electrode respectively with metal-oxide-semiconductor M7, M8, M9, M10, M11, the source electrode of M12 connects, metal-oxide-semiconductor M7, M8, M9, M10, M11, the grid of M12 respectively with digital controlled signal C<0>, C<1>, C<2>, C<3>, C<4>, C<5> connects, the drain electrode of its drain electrode and M0, the grid of M14 is connected with resistance R 1 one end, and the drain electrode of M14 is connected with ground, and source electrode is connected with the drain electrode of M13, and the grid of M13 is connected with bias voltage Vb and supply voltage VDD respectively with source electrode.Metal-oxide-semiconductor M1, M2, M3, M4, M5, M6 form set of number control current source, metal-oxide-semiconductor M7, M8, M9, M10, M11, M12 are the switch whether control current source flows to resistance R, the breadth length ratio of metal-oxide-semiconductor M1, M2, M3, M4, M5, M6 is pressed 2 exponential increase, and therefore the size of current of the digital control current source of this group is pressed 2 exponential increase.The output current of digital control current source all will change voltage into by resistance R 1, and transistor M13 and M14 form source follower, for by the voltage Buffer output in resistance R to Vc, Vc is used for controlling the frequency of oscillation of restructural pair born of the same parents' voltage controlled oscillators 14.In the time of chip power, digital processing unit 20 control switch LS<0> close, LS<1> opens, frequency preset module 13 is controlled voltage Va and is received on bias voltage VDD/2, by digital processing unit 20, two born of the same parents' oscillator 14 output frequencies are sampled, so just can draw in the time that control voltage Va is supply voltage half (VDD/2), different voltage controlled oscillator frequencies of oscillation and frequency preset module 13 control word C[5:0] and two born of the same parents' voltage controlled oscillator 14 control words of restructural between corresponding relation.For in the time of frequency hopping, directly by C[5:0] and P[2:0] carry out preset, thereby oscillator frequency is preset in the frequency approaching with target frequency.The C[5:0 of correspondence under the different frequency that sampling obtains] and P[2:0] be stored in nonvolatile memory 21, then opened by digital processing unit 20 control switch LS<0>, LS<0> closes, and phase-locked loop enters closed loop mode.In the time that phase-locked loop need to jump to target frequency from current frequency of oscillation, digital processor module 20 calculates the corresponding control word C[5:0 of target frequency by linear interpolation algorithm] and P[2:0] value, then by C[5:0] output to frequency preset module 13, by P[2:0] output to the two born of the same parents' voltage controlled oscillators 14 of restructural, thereby the value that two restructural born of the same parents' voltage controlled oscillator 14 frequency presets to is approached to target frequency, then completes meticulous locking by loop control voltage.Can greatly shorten like this locking time of phase-locked loop.
Based on a kind of high-speed radio radio-frequency (RF) transmitter system block diagram described in Fig. 1, Fig. 3 has provided the circuit diagram of provided by the invention pair of born of the same parents' voltage controlled oscillator 14.As shown in Figure 3, described pair of born of the same parents' voltage controlled oscillator 14 specifically comprises: two independences and identical voltage controlled oscillator i oscillator 410 and q oscillator 411, and two coupling branch road i coupling branch road 412 and q coupling branch road 413.Described pair of born of the same parents' voltage controlled oscillator 14 has two kinds of mode of operations: receiving mode and emission mode, in the time of receiving mode, i oscillator 410 and q oscillator 411 are in couple state, at this time the two born of the same parents' voltage controlled oscillators 14 of restructural are equivalent to a quadrature oscillator, can be for generation of the required quadrature carrier of receiver.In the time of emission mode, i oscillator 410 and q oscillator 411 are removed coupling, independent vibration, the locking of i oscillator phase locked loop, and q oscillator is not locked, the digital modulation signals that will send is added on q oscillator, for generation of frequency modulated signal, transmit data rate has been broken away from the restriction of PLL loop bandwidth like this, the frequency of oscillation of i oscillator is kept stable by phase-locked loop locking, and because i oscillator is identical with q oscillator control voltage Vc, the frequency of oscillation of q oscillator will be consistent with the frequency of oscillation of i oscillator, therefore in transmitting data, can keep the stable of transmitting carrier frequency.
Particularly, bias voltage VB3, control word P[2:0] be connected with the input of i oscillator and q oscillator with control voltage Vc, the output port I+ of i oscillator 410 is connected with q coupling branch road 413 with i coupling branch road 412 with I-, and the output port Q+ of q oscillator 411 is connected with q coupling branch road 413 and i coupling branch road 412 with Q-.I coupling branch road 412 is by resistance R 11, capacitor C 11, and metal-oxide-semiconductor M11, M12, M13, M14, M15, M16 form.M11 source electrode is connected with supply voltage VDD with M12 source electrode, M11 grid is connected with bias voltage VB1 with M12 grid, drain electrode is connected with M13 source electrode and M14 source electrode respectively with M12 in M11 drain electrode, resistance R 11 and capacitor C 11 parallel connections, one end is connected with M11 drain electrode, one end is connected with M12 drain electrode, M13 grid is connected with q oscillator 411 output Q-and output Q+ respectively with M14 grid, drain electrode is connected with M15 source electrode and M16 source electrode respectively with M14 in M13 drain electrode, M15 grid is connected with bias voltage VB2 with M16 grid, drain electrode is connected with output I+ and the output I-of i oscillator 410 respectively with M16 in M15 drain electrode.Q coupling branch road 413 is by resistance R 21, capacitor C 21, and metal-oxide-semiconductor M21, M22, M23, M24, M25, M26 form.M21 source electrode is connected with supply voltage VDD with M22 source electrode, M21 grid is connected with bias voltage VB1 with M22 grid, drain electrode is connected with M23 source electrode and M24 source electrode respectively with M22 in M21 drain electrode, resistance R 21 and capacitor C 21 parallel connections, one end is connected with M21 drain electrode, one end is connected with M22 drain electrode, M23 grid is connected with i oscillator 410 output I+ and output I-respectively with M24 grid, drain electrode is connected with M25 source electrode and M26 source electrode respectively with M24 in M23 drain electrode, M25 grid is connected with bias voltage VB2 with M26 grid, drain electrode is connected with output Q+ and the output Q-of q oscillator 411 respectively with M26 in M25 drain electrode.I oscillator is two cross-couplings negative resistance LC voltage controlled oscillators that structure is identical with q oscillator, and they are controlled by same control voltage Vc.LC voltage controlled oscillator adopts cross-couplings negative resistance technology, and has adopted the digital control capacitor array of 3 bits to expand the tuning range of voltage controlled oscillator.The two born of the same parents' voltage controlled oscillators 14 of restructural have two kinds of mode of operations: receiving mode and emission mode.The switching of these two kinds of mode of operations realizes by switching bias voltage VB1.
At the two born of the same parents' voltage controlled oscillators 14 of restructural during in receiving mode, bias voltage VB1 connects a fixed-bias transistor circuit, open in coupling branch current source (M11, M12, M21, M22), at this time i oscillator and q oscillator rely on coupling branch road to intercouple, can be equivalent to a quadrature oscillator, therefore the output of i oscillator is identical with the output signal frequency of q oscillator, but quadrature in phase.Parallel resistance electric capacity (R11-C11 and R22-C22) on coupling path is used for avoiding existing in orthogonal voltage-controlled vibrator bimodulus oscillation effect.
At the two born of the same parents' voltage controlled oscillators 14 of restructural during in emission mode, bias voltage VB1 connects supply voltage, coupling branch current source (M11, M12, M21, M22) close, at this moment i oscillator and q oscillator are no longer equivalent to a quadrature oscillator, be that i oscillator and q oscillator are removed coupling, i oscillator and q oscillator are in independent oscillatory regime, the output I+ of i oscillator and I-access in phase-locked loop through buffer 15, the output Q+ of q oscillator and Q-receive on power amplifier 16 after buffer 15, because being subject to same frequency of oscillation control voltage Vc, i oscillator and q oscillator control, the frequency of oscillation of q oscillator will be followed the frequency of oscillation of i oscillator, the base band data of transmitting is added on the VB3 port of q oscillator, the data rate of transmitting will be broken away from the restriction of PLL loop bandwidth like this, and the carrier frequency of transmitting will keep stable.The existing transmitter based on phase-locked loop mainly contains four kinds of implementations: closed loop frequency divider modulate emission, closed loop voltage controlled oscillator modulate emission, 2 modulate emission and open loop voltage controlled oscillator modulate emission.
The transmit data rate of closed loop frequency divider modulate emission structure is limited to the loop bandwidth of phase-locked loop, is therefore difficult to the transmit data rate that reaches higher.The shortcoming of closed loop voltage controlled oscillator modulate emission structure is that the low-frequency component of transmitting data can be by loss distortion.2 modulated structures combine the advantage of closed loop frequency divider modulate emission and closed loop voltage controlled oscillator modulate emission, have avoided shortcoming separately simultaneously, but not mating of gain and phase place can the quality that transmits of impact, and design is complicated and consumption power consumption is larger.The transmitting carrier wave of open loop voltage controlled oscillator modulate emission structure is easily subject to the impact of Leakage Current and outside noise interference, and this structure is not suitable for continuous modulation transmitting in addition, and therefore the data volume of transmission is restricted.
The phase-locked loop transmitter that the present invention proposes adopts based on two born of the same parents' voltage controlled oscillator structures, in the time of transmitting, launch carrier wave and can keep stable, avoid open loop voltage controlled oscillator modulate emission problem, the problem includes: frequency drift problem, can realize again higher data transmission rate, avoided closed loop frequency divider modulate emission problem, the problem includes: emission rate is limited to the problem of PLL loop bandwidth simultaneously.
Based on a kind of high-speed radio radio-frequency (RF) transmitter system block diagram described in Fig. 1, Fig. 4 has provided the circuit diagram of power amplifier 16 provided by the invention.As shown in Figure 4, described power amplifier 16 is made up of driving stage circuit 610 and output-stage circuit 611, the rf modulated signal that it produces for launching q oscillator.Wherein driving stage 610 is by capacitor C in, Cp, inductance L 1, resistance R 1, metal-oxide-semiconductor M1, M2, M3, M4 composition.Capacitor C in mono-termination radiofrequency signal RFin, one end is connected with the grid of metal-oxide-semiconductor M1, resistance R 1 one end is connected with bias voltage VB, one end is connected with M1 grid, capacitor C p one end is connected with M1 grid, one end is connected with metal-oxide-semiconductor M4 drain electrode, metal-oxide-semiconductor M1 source electrode is connected with ground, drain electrode is connected with metal-oxide-semiconductor M2 source electrode, metal-oxide-semiconductor M2 drain electrode is connected with inductance L 1 and metal-oxide-semiconductor M3 drain electrode, the grid of M2 is connected with power vd D, inductance L 1 one end is connected with power vd D, one end is connected with M2 drain electrode, M3 drain electrode is connected with M2 drain electrode, M3 grid is connected with switching signal SW1, M4 drain electrode is connected with capacitor C p one end, M4 source electrode is connected with M2 drain electrode, the grid of M4 is connected with switching signal SW0.Output stage 611 is by capacitor C 1, C2 and C3, resistance R 2 and R3, metal-oxide-semiconductor M5 and M6 composition, capacitor C 1 one end is connected with C2, one end is connected with M5 grid, capacitor C 2 other ends are connected with M6 grid, resistance R 2 one end are connected with bias voltage VBP, and one end is connected with M5 grid, and resistance R 3 one end are connected with bias voltage VBN, one end is connected with M6 grid, M6 source electrode is connected with ground, and M6 drain electrode is connected with M5 drain electrode, and M5 source electrode is connected with supply voltage VDD, capacitor C 3 one end are connected with M5 drain electrode and M6 drain electrode, and one end is connected with output RFout.
The driving stage circuit 610 of power amplifier 16, for radiofrequency signal is amplified for the first time, provides the high voltage signal amplitude of oscillation, and output-stage circuit 611 is for 50 Ω antenna loads outside driving chip.Switch SW 0 and SW1 are used for realizing third gear gain and control (high-gain, medium gain and low gain), and the gain control range of 20dB can be provided.In the time that SW0 and SW1 are high level, power amplifier 16 is in high gain mode; When being high level as SW0, when SW1 is low level, power amplifier 16 is in medium gain pattern; When being low level as SW0, when SW1 is high level, power amplifier 16 is in low gain mode.The metal-oxide-semiconductor M5 of output stage 611 and M6 are operated in subthreshold value point by bias voltage VBP and VBN are set, and to reduce quiescent current consumption, improve the efficiency of power amplifier.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a Wireless RF transmitter, it comprises: phase frequency detector, charge pump, loop filter and two born of the same parents' voltage controlled oscillator;
Wherein, described pair of born of the same parents' voltage controlled oscillator comprises the first voltage controlled oscillator and the second voltage controlled oscillator that structure is identical, wherein, when described pair of born of the same parents' voltage controlled oscillator is during in receiving mode, described the first voltage controlled oscillator and the second voltage controlled oscillator intercouple, form orthogonal voltage-controlled vibrator, described orthogonal voltage-controlled vibrator and described phase frequency detector, charge pump, loop filter form phase-locked loop, produce the quadrature carrier that reception information is used; When described pair of born of the same parents' voltage controlled oscillator is during in emission mode, described the first voltage controlled oscillator and described phase frequency detector, charge pump, loop filter form phase-locked loop, and described the second voltage controlled oscillator is for carrying out frequency modulation(FM) to transmitting data.
2. device as claimed in claim 1, wherein, described pair of born of the same parents' voltage controlled oscillator also comprises: the first coupling branch road and the second coupling branch road, wherein, the output of described the first voltage controlled oscillator is connected with the input of described the first coupling branch road and the second coupling branch road respectively, and the output of described the second voltage controlled oscillator is connected with the input of described the first coupling branch road and the second coupling branch road respectively.
3. device as claimed in claim 2, wherein, when described first coupling branch road and second coupling branch road add after electric current, described the first voltage controlled oscillator and the second voltage controlled oscillator are coupled and are formed orthogonal voltage-controlled vibrator by described the first coupling branch road and the second coupling branch road, and described pair of born of the same parents' voltage controlled oscillator switches to receiving mode;
When disconnecting after the electric current of the first coupling branch road and the second coupling branch road, described the first voltage controlled oscillator and the coupling of the second voltage controlled oscillator solution, described pair of born of the same parents' voltage controlled oscillator switches to emission mode.
4. device as claimed in claim 1, wherein, the frequency of oscillation of described the first voltage controlled oscillator and the second voltage controlled oscillator is subject to the control of first frequency control signal.
5. device as claimed in claim 4, wherein, described phase frequency detector, charge pump and loop filter regulate described first frequency control signal according to the value of feedback of the output frequency of described pair of born of the same parents' voltage controlled oscillator.
6. device as claimed in claim 4, it also comprises:
Frequency preset module, it carries out preset to described pair of born of the same parents' pressuring controlling oscillator frequency for described phase-locked loop when the frequency hopping.
7. device as claimed in claim 6, wherein, described frequency preset module changes described first frequency control signal according to the preset control word of first frequency.
8. device as claimed in claim 4, wherein, the frequency of oscillation of described the first voltage controlled oscillator and the second voltage controlled oscillator is also subject to the control of the preset control word of second frequency.
9. install as claimed in claim 7 or 8, wherein, the preset control word of described first frequency and the preset control word of second frequency are that the target frequency that will jump to according to described pair of born of the same parents' voltage controlled oscillator sets in advance.
10. device as claimed in claim 9, it also comprises: digital processing unit, it samples to the output frequency of described pair of born of the same parents' voltage controlled oscillator in the time powering on, to obtain the output frequency of described pair of born of the same parents' voltage controlled oscillator and the corresponding relation of the preset control word of described first frequency and the preset control word of second frequency.
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