CN104125049A

CN104125049A - Redundancy implementation method of PCIE (Peripheral Component Interface Express) device based on BRICKLAND platform

Info

Publication number: CN104125049A
Application number: CN201410387756.6A
Authority: CN
Inventors: 牟茜; 刘振东; 李萌
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2014-08-08
Filing date: 2014-08-08
Publication date: 2014-10-29

Abstract

The invention discloses a redundancy implementation method of a PCIE (Peripheral Component Interface Express) device based on a BRICKLAND platform, and belongs to the technical field of computers. The method comprises the following steps: respectively setting two adjacent CPU as CPU0 and CPU1; connecting PCIEDEVICE in the system to the CPU0 and CPU1 through PCIESwitch; monitoring the states of the CPU0 and CPU1 by the system through FPGA (Field Programmable Gate Array)/ CPLD (Complex Programmable Logic Device); controlling the connection state of PCIESwitchPort according to the monitored state results of the CPU0 and the CPU1, and thus determining the connection of the CPU0 and PU1 to the PCIEDEVICE. With the adoption of the method, the PCIE device is switched to other CPU in case some CPU of the server suffers from fault, and thus the PCIE device under the faulted CPU can work normally without closing the system, and as a result, the stability of the whole system is improved.

Description

A kind of PCIE equipment redundancy implementation method based on BRICKLAND platform

Technical field

The present invention relates to field of computer technology, specifically a kind of PCIE equipment redundancy implementation method based on BRICKLAND platform.

Background technology

The simplicity of the maintainability of the development of server technology now to server and server maintenance requires more and more higher, current Brickland Platform Server, PCIE controller is integrated in CPU inside, part server does not use all PCIE resources of corresponding CPU, and system can have been supported online and the offline function of CPU, but in the time there is CPU offline situation, the PCIE equipment under offline CPU is disabled, causes the not continuity of PCIE equipment work.

Current Brickland Platform Server mostly is multi processor platform, and in the time that offline or other mistakes appear in a CPU, losing efficacy at once in the PCIE groove position under corresponding CPU, causes PCIE equipment normally to work, and greatly reduces the stability of whole system.

Literary composition Chinese and English is explained as follows:

PCIE Slot: i.e. PCI Express slot, this slot is the actual embodiment of PCE bus on server master board; PCI Express, is called for short PCI-E, is the one of computer bus PCI, and it has continued to use existing PCI programming concept and communication standard, but builds based on serial communication system faster.Intel is the main supporter of this interface.PCIe is only applied to intraconnection.Because PCIe is based on existing pci system, only need amendment physical layer and need not revise software and just existing pci system can be converted to PCIe.PCIe has speed faster, to replace almost whole existing internal buss (comprising AGP and PCI).

The passive switch of PCIE Passive Switch:PCIE, needs Event triggered;

CPU Online/Offline: the modern advanced feature on system architecture makes processor possess the ability of error reporting and error correction.CPU architecture is supported subregion, and this makes the computational resource of single cpu also can meet the needs of virtual machine.Some OEM have supported the hot plug of NUMA hardware, the insertion of physical node with remove the support that needs hot plug of processor technology.The CPU. that this advanced feature needs kernel can remove where necessary to use such as, for the needs of RAS, a CPUoffline who carries out malicious code must be remained on this CPU outside system execution route, after changing this CPU, need to do online operation, it is continued to use within import system execution route again.

Brickland platform: the i.e. server platform of ' Brickland ', is made up of the server platform of platform code name ' Brickland ' the Ivy Bridge goods processor of Intel Xeon series and C602J server chipset.

Summary of the invention

Technical assignment of the present invention is to provide a kind of PCIE equipment redundancy implementation method based on BRICKLAND platform.

Technical assignment of the present invention is realized in the following manner, and the method step is as follows:

Two adjacent CPU are set to respectively to CPU0 and CPU1, PCIE DEVICE in system is connected respectively to CPU0 and CPU1 by PCIE Switch, system is carried out the state of monitoring CPU 0 and CPU1 by FPGA/CPLD, control PCIE Switch Port connection status by monitoring the state outcome of CPU0 and CPU1, thereby determine that PCIE DEVICE connects CPU0 or CPU1.

In the time that described CPU0 is working properly, FPGA/CPLD connects PCIE Switch to be arranged on Port0, and PCIE DEVICE is connected to CPU0 by the Port0 of PCIE Switch, and now, PCIE Switch Port1 is closed condition.

In the time that offline appears in described CPU0 or occur that other are wrong, FPGA/CPLD monitoring CPU 0 breaks down, and automatically PCIE Switch is switched to Port1, and PCIE DEVICE is connected to CPU1 by Port1, ensures that PCIE DEVICE normally works.

A kind of PCIE equipment redundancy implementation method based on BRICKLAND platform of the present invention compared to the prior art, can realize server system in the time that certain CPU breaks down, PCIE equipment is switched on other CPU, can be without shutdown system in the situation that, the PCIE equipment under fault CPU that ensures is normally worked, to improve whole system stability.

Brief description of the drawings

Accompanying drawing 1 is a kind of PCIE Redundancy Design schematic diagram of the PCIE equipment redundancy implementation method based on BRICKLAND platform.

The connection diagram when CPU0 that accompanying drawing 2 is a kind of PCIE equipment redundancy implementation method based on BRICKLAND platform normally works.

Connection diagram when accompanying drawing 3 is a kind of CPU0 offline of the PCIE equipment redundancy implementation method based on BRICKLAND platform.

Figure Chinese and English is explained as follows:

PCIE DEVICE:PCIe equipment comprises EP (as the equipment such as network interface card, video card), Switch and PCIe bridge.PCIe bus adopts connected mode end to end, and each PCIe port can only connect an EP, and certain PCIe port also can connect Switch and carry out link expansion.The PCIe link expanding by Switch can continue to articulate EP or other Switch

PCIE Switch: in PCIe architecture, Switch is in core status.PCIe bus is used Switch to carry out link expansion, in Switch, and the corresponding Virtual PC I bridge of each port.

embodiment

Embodiment 1:

Two adjacent CPU are set to respectively to CPU0 and CPU1, PCIE equipment in system is connected respectively to CPU0 and CPU1 by PCIE Switch, system is carried out the state of monitoring CPU 0 and CPU1 by FPGA/CPLD, control PCIE Switch Port connection status by monitoring the state outcome of CPU0 and CPU1; In the time that described CPU0 is working properly, FPGA/CPLD connects PCIE Switch to be arranged on Port0, and PCIE DEVICE is connected to CPU0 by the Port0 of PCIE Switch, and now, PCIE Switch Port1 is closed condition.

Embodiment 2:

Two adjacent CPU are set to respectively to CPU0 and CPU1, PCIE equipment in system is connected respectively to CPU0 and CPU1 by PCIE Switch, system is carried out the state of monitoring CPU 0 and CPU1 by FPGA/CPLD, control PCIE Switch Port connection status by monitoring the state outcome of CPU0 and CPU1; In the time that offline appears in described CPU0 or occur that other are wrong, FPGA/CPLD monitoring CPU 0 breaks down, and automatically PCIE Switch is switched to Port1, and PCIE DEVICE is connected to CPU1 by Port1, ensures that PCIE DEVICE normally works.

Embodiment 3:

Two adjacent CPU are set to respectively to CPU0 and CPU1, PCIE Slot in system is connected respectively to CPU0 and CPU1 by PCIE Switch, system is carried out the state of monitoring CPU 0 and CPU1 by FPGA/CPLD, control PCIE Switch Port connection status by monitoring the state outcome of CPU0 and CPU1; In the time that described CPU0 is working properly, FPGA/CPLD connects PCIE Switch to be arranged on Port0, and PCIE DEVICE is connected to CPU0 by the Port0 of PCIE Switch, and now, PCIE Switch Port1 is closed condition; In the time that offline appears in described CPU0 or occur that other are wrong, FPGA/CPLD monitoring CPU 0 breaks down, and automatically PCIE Switch is switched to Port1, and PCIE DEVICE is connected to CPU1 by Port1, ensures that PCIE DEVICE normally works.

By embodiment above, described those skilled in the art can be easy to realize the present invention.But should be appreciated that the present invention is not limited to above-mentioned several embodiments.On the basis of disclosed execution mode, described those skilled in the art can the different technical characterictic of combination in any, thereby realizes different technical schemes.

Claims

1. the PCIE equipment redundancy implementation method based on BRICKLAND platform, is characterized in that, the method step is as follows:

2. a kind of PCIE equipment redundancy implementation method based on BRICKLAND platform according to claim 1, it is characterized in that, in the time that described CPU0 is working properly, FPGA/CPLD connects PCIE Switch to be arranged on Port0, PCIE DEVICE is connected to CPU0 by the Port0 of PCIE Switch, now, PCIE Switch Port1 is closed condition.

3. a kind of PCIE equipment redundancy implementation method based on BRICKLAND platform according to claim 1, it is characterized in that, in the time that there is offline in described CPU0 or occurs that other are wrong, FPGA/CPLD monitoring CPU 0 breaks down, automatically PCIE Switch is switched to Port1, PCIE DEVICE is connected to CPU1 by Port1, ensures that PCIE DEVICE normally works.