CN104124142A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104124142A CN104124142A CN201310143239.XA CN201310143239A CN104124142A CN 104124142 A CN104124142 A CN 104124142A CN 201310143239 A CN201310143239 A CN 201310143239A CN 104124142 A CN104124142 A CN 104124142A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 115
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 150000004767 nitrides Chemical group 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 abstract 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device and a manufacturing method thereof. The method includes the following steps: providing a semiconductor substrate and forming sequentially a first sacrifice material layer and a second sacrifice layer provided with a first opening on the semiconductor substrate; forming offset side walls on side walls of the first opening; etching the first sacrifice layer beneath the first opening so as to form a second opening; etching the semiconductor substrate beneath the second opening so as to form a groove; forming a gate oxide layer in the groove and forming a gate material layer on the gate oxide layer and in the first opening and second opening; and sequentially removing the second sacrifice layer and the first sacrifice layer so as to form a grid electrode which is provided with a recess at a peripheral bottom part. According to the semiconductor device and the manufacturing method thereof, an overlap capacitance between the gate electrode and a source/drain region in the substrate can be reduced and effective widths of the offset side walls at the two sides of the grid electrode are reduced and a stress applied to a channel region beneath the grid electrode by a high-stress contact etch stop layer which covers the grid electrode is reinforced and a channel current carrier mobility ratio is improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method that forms the jagged grid of outer rim bottom tool.
Background technology
When the manufacturing process node of cmos device reaches 90nm and when following, the overlap capacitance between low channel mobility, short-channel effect and grid and the source/drain region of substrate becomes the principal element of the hydraulic performance decline that makes such device.For this reason, those skilled in the art adopts various stress techniques to carry out the channel mobility of boost device.For NMOS, the most one of stress technique of extensive use be on substrate, form there is high tensile stress contact etch stop layer (CESL) to cover the grid being formed on described substrate.This stress technique is compatible mutually with traditional semiconductor fabrication process, does not need to increase extra operation, for example extra epitaxial growth or photo-mask process.
In order further to strengthen the stress that described contact etch stop layer acts on the channel region of cmos device, those skilled in the art adopts stress closely to face technology conventionally, reduces to be formed on the thickness of the sidewall of grid both sides.This stress technique need to adopt etch process to realize the reduction of the thickness of the sidewall that is formed on grid both sides, and this is etched in to a certain extent can cause damage to grid; Due to the reduction of sidewall thickness, the etching that follow-up formation contact hole adopts causes the probability of damage to become large to substrate; Meanwhile, the problem of short-channel effect and overlap capacitance is not resolved.
Therefore, a kind of method need to be proposed, to address the above problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, forms successively the first sacrificial material layer and second sacrificial material layer with the first opening; On the sidewall of described the first opening, form offset side wall; Described in etching, described first sacrificial material layer of the first opening below, to form the second opening, removes described offset side wall; The described Semiconductor substrate of the second opening below described in etching, to form groove; In described groove, form gate oxide layers, and form gate material layer on described gate oxide layers and in described the first opening and described the second opening; Remove successively described the second sacrificial material layer and described the first sacrificial material layer, to form the jagged grid of outer rim bottom tool.
Further, after forming described grid, also comprise and form the step of surrounding described grid and covering the shielding layer of described Semiconductor substrate.
Further, after forming described shielding layer, the both sides that are also included in described grid form the step of clearance wall.
Further, before forming described clearance wall, also comprise the step of carrying out light dope Implantation annealing, to form lightly-doped source/drain region in the Semiconductor substrate in described grid both sides.
Further, after forming described clearance wall, also comprise and carry out the step that heavy doping ion is injected and annealed, to form heavy-doped source/drain region in the Semiconductor substrate in described grid both sides.
Further, described the first sacrificial material layer is oxide skin(coating); Described the second sacrificial material layer is nitride layer.
Further, the step that has the second sacrificial material layer of the first opening described in formation comprises: in described the first sacrificial material layer, form the second sacrificial material layer; In described the second sacrificial material layer, form the photoresist layer of the figure with described the first opening; Take described photoresist layer as mask, and the second sacrificial material layer described in etching, until expose described the first sacrificial material layer; Adopt cineration technics to remove described photoresist layer.
Further, the step that forms described offset side wall comprises: deposition offset side wall material layer is to cover the surface of described the second sacrificial material layer and sidewall and the bottom of described the first opening; Described in etching, offset side wall material layer is to form described offset side wall.
Further, the material of described offset side wall material layer is identical with the material of described the first sacrificial material layer, in etching, forms in the step of described the second opening, and described offset side wall is removed simultaneously.
Further, adopt thermal oxidation technology to form described gate oxide layers and described shielding layer.
Further, adopt wet etching process to remove described the second sacrificial material layer.
Further, the step of removing described the first sacrificial material layer comprises: first adopt anisotropic dry method etch technology to implement the etching to described the first sacrificial material layer, until expose described Semiconductor substrate; Adopt again wet etching process to remove the first sacrificial material layer of described gate material layer below.
The present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be formed on the groove in described Semiconductor substrate; Be arranged in the gate oxide layers of described groove; Be formed on the gate material layer on described gate oxide layers, between the outer rim bottom of described gate material layer and described Semiconductor substrate, there is recess.
Further, described semiconductor device also comprises: the clearance wall that surrounds described gate material layer and cover the shielding layer of described Semiconductor substrate and be positioned at described gate material layer both sides.
Further, arrive the lower end of described recess along the upper end of described recess, the width of described gate material layer progressively reduces.
Further, the bottom width of described gate material layer is identical with the width of described gate oxide layers.
According to the present invention, can in Semiconductor substrate, form the jagged grid of outer rim bottom tool, thereby reduce the overlap capacitance between the source/drain region in grid and substrate, reduce the effective width of the offset side wall of grid both sides, the heavily stressed contact etch stop layer that strengthens cover gate acts on the stress of the channel region of grid below, promotes channel carrier mobility.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
The schematic cross sectional view of the device that Figure 1A-Fig. 1 M obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 2 is the flow chart that the method for exemplary embodiment of the present forms the jagged grid of outer rim bottom tool.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that the method for the jagged grid of formation outer rim bottom tool that explaination the present invention proposes.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, but do not get rid of, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, with reference to Figure 1A-Fig. 1 M and Fig. 2, the detailed step of the jagged grid of method formation outer rim bottom tool is according to an exemplary embodiment of the present invention described.
With reference to Figure 1A-Fig. 1 M, wherein show the schematic cross sectional view of the device that method is implemented successively according to an exemplary embodiment of the present invention step obtains respectively.
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, the constituent material of Semiconductor substrate 100 is selected monocrystalline silicon.In Semiconductor substrate 100, to be formed with isolation structure, various trap (well) structure etc., in order simplifying, in diagram, to be omitted.
Next, in Semiconductor substrate 100, form successively the first sacrificial material layer 101 and the second sacrificial material layer 102.The various suitable technique that the formation of the first sacrificial material layer 101 and the second sacrificial material layer 102 can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method.The first sacrificial material layer 101 is oxide skin(coating), preferential oxidation silicon layer; The second sacrificial material layer 102 is nitride layer, preferably silicon nitride layer.
Then, as shown in Figure 1B, in the second sacrificial material layer 102, form the first opening 103, to expose the first sacrificial material layer 101.The processing step that forms the first opening 103 comprises: the photoresist layer that forms the figure with the first opening 103 in the second sacrificial material layer 102; Take described photoresist layer as mask, and etching the second sacrificial material layer 102, until expose the first sacrificial material layer 101; Adopt cineration technics to remove described photoresist layer.The etched etching gas of the second sacrificial material layer 102 is comprised to CF
4, CHF
3, CH
2f
2, CH
3f etc.
Then, as shown in Figure 1 C, on the sidewall of the first opening 103, form offset side wall 104.The processing step that forms offset side wall 104 comprises: deposition offset side wall material layer is to cover the surface of the second sacrificial material layer 102 and sidewall and the bottom of the first opening 103; Described in etching, offset side wall material layer is to form offset side wall 104.The material of described offset side wall material layer is preferably identical with the material of the first sacrificial material layer 101, and in the present embodiment, the material of described offset side wall material layer is silica.The etched etching gas of described offset side wall material layer is comprised to CF
4, CHF
3, C
2f
6, C
4f
8, C
5f
8deng.
Then,, as shown in Fig. 1 D, the first sacrificial material layer 101 of etching the first opening 103 belows, to form the second opening 105 in the first sacrificial material layer 101.Described etching is until stop while exposing Semiconductor substrate 100, and offset side wall 104 is removed simultaneously, and the top width of the second opening 105 of formation is identical with the width of the first opening 103, and the bottom width of the second opening 105 of formation is less than the width of the first opening 103.The etched etching gas of the first sacrificial material layer 101 to the first opening 103 belows comprises CF
4, CHF
3, C
2f
6, C
4f
8, C
5f
8deng.
Then,, as shown in Fig. 1 E, the Semiconductor substrate 100 of etching the second opening 105 belows, to form groove 107 ' in Semiconductor substrate 100.The etched etching gas of Semiconductor substrate 100 to the second opening 105 belows comprises CF
4, HBr, Cl
2, CHF
3, O
2deng.
Then,, as shown in Fig. 1 F, in groove 107 ', form gate oxide layers 107.The various suitable technique that the formation of gate oxide layers 107 can adopt those skilled in the art to have the knack of, for example thermal oxidation technology.
Next, on gate oxide layers 107 and in the first opening 103 and the second opening 105, form gate material layer 106.The various suitable technique that the formation of gate material layer 106 can adopt those skilled in the art to have the knack of, for example chemical vapor deposition method and the subsequently chemical mechanical milling tech of enforcement.The preferred polysilicon layer of gate material layer 106.
Then, as shown in Figure 1 G, remove the second sacrificial material layer 102.The various suitable technique that the removal of the second sacrificial material layer 102 can adopt those skilled in the art to have the knack of, for example wet etching process.
Then,, as shown in Fig. 1 H, etching the first sacrificial material layer 101, until expose Semiconductor substrate 100.Adopt anisotropic dry method etch technology to implement the etching to the first sacrificial material layer 101, after described etching finishes, the first sacrificial material layer 101 that is positioned at gate material layer 106 belows is not removed.
Then, as shown in Figure 1 I, remove the first sacrificial material layer 101 of gate material layer 106 belows, with the bottom formation recess 108 ' near outer rim in gate material layer 106.Adopt wet etching process to implement the removal to the first sacrificial material layer 101 of gate material layer 106 belows.So far, in Semiconductor substrate 100, form the jagged grid 106 ' of outer rim bottom tool.
It should be noted that, the above-mentioned wet etching process that also can complete by a step the removal of the first sacrificial material layer 101 is implemented.
Then,, as shown in Fig. 1 J, form the shielding layer 108 that surrounds grid 106 ' and cover Semiconductor substrate 100.Adopt thermal oxidation technology to form shielding layer 108.
Then,, as shown in Fig. 1 K, carry out light dope Implantation annealing, to form lightly-doped source/drain region 109 in the Semiconductor substrate 100 in grid 106 ' both sides.For nmos pass transistor, the doping ion of described light dope Implantation can be phosphonium ion or arsenic ion etc.; For PMOS transistor, the doping ion of described light dope Implantation can be boron ion or indium ion etc.
Then,, as shown in Fig. 1 L, in the both sides of grid 106 ', form clearance wall 110.The material preferred nitrogen SiClx of clearance wall 110.
Then,, as shown in Fig. 1 M, carry out heavy doping ion and inject and anneal, to form heavy-doped source/drain region 111 in the Semiconductor substrate 100 in grid 106 ' both sides.
So far, complete whole processing steps that method is implemented according to an exemplary embodiment of the present invention, next, can complete by subsequent technique the making of whole semiconductor device.According to the present invention, can in Semiconductor substrate, form the jagged grid of outer rim bottom tool, thereby reduce the overlap capacitance between the source/drain region in grid and substrate, reduce the effective width of the offset side wall of grid both sides, the heavily stressed contact etch stop layer that strengthens cover gate acts on the stress of the channel region of grid below, promotes channel carrier mobility.
With reference to Fig. 2, wherein show the flow chart of the jagged grid of method formation outer rim bottom tool according to an exemplary embodiment of the present invention, for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in Semiconductor substrate, form successively the first sacrificial material layer and second sacrificial material layer with the first opening;
In step 202, on the sidewall of the first opening, form offset side wall;
In step 203, the first sacrificial material layer of etching the first opening below, to form the second opening, removes offset side wall;
In step 204, the Semiconductor substrate of etching the second opening below, to form groove;
In step 205, in groove, form gate oxide layers, and form gate material layer on gate oxide layers and in the first opening and the second opening;
In step 206, remove successively the second sacrificial material layer and the first sacrificial material layer, to form the jagged grid of outer rim bottom tool.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms successively the first sacrificial material layer and second sacrificial material layer with the first opening;
On the sidewall of described the first opening, form offset side wall;
Described in etching, described first sacrificial material layer of the first opening below, to form the second opening, removes described offset side wall;
The described Semiconductor substrate of the second opening below described in etching, to form groove;
In described groove, form gate oxide layers, and form gate material layer on described gate oxide layers and in described the first opening and described the second opening;
Remove successively described the second sacrificial material layer and described the first sacrificial material layer, to form the jagged grid of outer rim bottom tool.
2. method according to claim 1, is characterized in that, after forming described grid, also comprises and forms the step of surrounding described grid and covering the shielding layer of described Semiconductor substrate.
3. method according to claim 2, is characterized in that, after forming described shielding layer, the both sides that are also included in described grid form the step of clearance wall.
4. method according to claim 3, is characterized in that, before forming described clearance wall, also comprises the step of carrying out light dope Implantation annealing, to form lightly-doped source/drain region in the Semiconductor substrate in described grid both sides.
5. method according to claim 4, is characterized in that, after forming described clearance wall, also comprises and carries out the step that heavy doping ion is injected and annealed, to form heavy-doped source/drain region in the Semiconductor substrate in described grid both sides.
6. method according to claim 1, is characterized in that, described the first sacrificial material layer is oxide skin(coating); Described the second sacrificial material layer is nitride layer.
7. method according to claim 1, is characterized in that, the step described in formation with the second sacrificial material layer of the first opening comprises: in described the first sacrificial material layer, form the second sacrificial material layer; In described the second sacrificial material layer, form the photoresist layer of the figure with described the first opening; Take described photoresist layer as mask, and the second sacrificial material layer described in etching, until expose described the first sacrificial material layer; Adopt cineration technics to remove described photoresist layer.
8. method according to claim 1, is characterized in that, the step that forms described offset side wall comprises: deposition offset side wall material layer is to cover the surface of described the second sacrificial material layer and sidewall and the bottom of described the first opening; Described in etching, offset side wall material layer is to form described offset side wall.
9. method according to claim 8, is characterized in that, the material of described offset side wall material layer is identical with the material of described the first sacrificial material layer, in etching, forms in the step of described the second opening, and described offset side wall is removed simultaneously.
10. method according to claim 1, is characterized in that, adopts thermal oxidation technology to form described gate oxide layers and described shielding layer.
11. methods according to claim 1, is characterized in that, adopt wet etching process to remove described the second sacrificial material layer.
12. methods according to claim 1, is characterized in that, the step of removing described the first sacrificial material layer comprises: first adopt anisotropic dry method etch technology to implement the etching to described the first sacrificial material layer, until expose described Semiconductor substrate; Adopt again wet etching process to remove the first sacrificial material layer of described gate material layer below.
13. 1 kinds of semiconductor device, comprising:
Semiconductor substrate;
Be formed on the groove in described Semiconductor substrate;
Be arranged in the gate oxide layers of described groove;
Be formed on the gate material layer on described gate oxide layers, between the outer rim bottom of described gate material layer and described Semiconductor substrate, there is recess.
14. semiconductor device according to claim 13, is characterized in that, also comprise: the clearance wall that surrounds described gate material layer and cover the shielding layer of described Semiconductor substrate and be positioned at described gate material layer both sides.
15. semiconductor device according to claim 13, is characterized in that, arrive the lower end of described recess along the upper end of described recess, and the width of described gate material layer progressively reduces.
16. semiconductor device according to claim 15, is characterized in that, the bottom width of described gate material layer is identical with the width of described gate oxide layers.
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| CN109560114A (en) * | 2018-12-06 | 2019-04-02 | 京东方科技集团股份有限公司 | Manufacturing method, display panel and the display device of display panel |
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