CN104113740A - Mixed format signal optical fiber transmission device - Google Patents
Mixed format signal optical fiber transmission device Download PDFInfo
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- CN104113740A CN104113740A CN201410364473.XA CN201410364473A CN104113740A CN 104113740 A CN104113740 A CN 104113740A CN 201410364473 A CN201410364473 A CN 201410364473A CN 104113740 A CN104113740 A CN 104113740A
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Abstract
The invention discloses a mixed format signal optical fiber transmission device. The mixed format signal optical fiber transmission device comprises a sending end, a fiber channel and a receiving end, wherein the sending end converts input camera link format video image signals and multi-channel universal serial signals into optical signals, the optical signals are sent to the receiving end through the fiber channel, and the receiving end receives the optical signals and restores the optical signals to original video image signals and multi-channel universal serial data signals. The mixed format signal optical fiber transmission device is suitable for optical fiber transmission of the camera link video image signals and the multi-channel universal serial signals in all configuration modes, the transmission of mixed format signals in a single-fiber channel at different rates can be achieved through multiplexing of a transmission bus, and consumption of extra fiber channels and devices is reduced. According to the mixed format signal optical fiber transmission device, electrical signal conversion processing and transmission control are achieved through a field programmable gate array (FPGA) device, the requirement for actual functions is met, meanwhile, the usage of application-specific integrated circuits is reduced, the advantage of high integration and universalization degrees can be achieved, and supports can be provided for further function extension and performance upgrading.
Description
Technical field
The present invention relates to signal and process and transmission technique field, relate in particular to a kind of mixed format signal optical fibre transmitting device.
Background technology
Along with frame frequency and resolution improve constantly, at present the bandwidth of video image acquisition equipment can reach gigabit per second (Gbps) rank, and cable is difficult to meet the transmitting of the High-speed video images signal of more than ten rice distance.Optical Fiber Transmission has the advantages that high, the anti-electromagnetic interference performance of bandwidth is strong, transmission range is long, and progressively replacement cables is being applied at a high speed and in long distance transmit now.
Current fibre optic transmission equipment both domestic and external is all for single format signal transmission, can not meet the real-time Transmission of high speed image signal and extended formatting signal simultaneously, therefore in Practical Project, need to use many transmission equipments and many group optical-fibre channels, make transmission system have the shortcoming that volume is large, cost is high and difficult in maintenance.Meanwhile, this type of high speed fibre transmission equipment generally adopts ASIC Design and realization, at the aspects such as adaptability of Function Extension, performance upgrade and operational environment, is limited to.
Summary of the invention
For addressing the above problem, the invention provides a kind of mixed format signal optical fibre transmitting device and transmission method based on FPGA.
The invention provides following technical scheme: a kind of mixed format signal optical fibre transmitting device, comprises transmitting terminal (1), optical-fibre channel (2) and receiving terminal (3); Described transmitting terminal (1) comprises FPGA transmission processing unit (4), the first connector group (5), photoelectric conversion unit (6) and tranmitting data register generation unit (7); Described optical-fibre channel (2) comprises three groups of monomode fibers, and described optical-fibre channel (2) connects described transmitting terminal (1) and described receiving terminal (3); Described receiving terminal (2) comprises the second connector group (8), FPGA reception & disposal unit (9), electrooptic switching element (10) and receive clock generation unit (11);
Described FPGA transmission processing unit (4) is connected with described photoelectric conversion unit (6) with described the first connector group (5) respectively; Three groups of SFP optical transceivers of described photoelectric conversion unit (6), for receiving from described the first connector group (5) 12 road LVDS level Camera Link format video picture signal He10 road general serial signal and the signal of reception being converted to the high-speed serial signals of three road CML level, are sent in described FPGA transmission processing unit (4); Described photoelectric conversion unit (6) sends to described receiving terminal (3) for converting electrical signals to light signal by described optical-fibre channel (2); Described tranmitting data register generation unit (7) is connected with described FPGA transmission processing unit (4) with described the first connector group (5) respectively, described tranmitting data register generation unit (7), for receiving the 1 road LVDS pixel clock signal from described the first connector group (5), offers described FPGA transmission processing unit (4) through eliminating dithering process by clock;
Described FPGA reception & disposal unit (9) is connected with described electrooptic switching element (10) with described optical-fibre channel (2) respectively; Three groups of SFP optical transceivers in described electrooptic switching element (10) input to described FPGA reception & disposal unit (9) after for the high-speed serial signals that described optical-fibre channel (2) is transmitted to San road light signal and be converted to three road CML forms; Described FPGA reception & disposal unit (9) for Jiang San road high-speed serial signals process and revert to 12 road LVDS level Camera Link vision signals, 3 LVDS channel associated clock signal He10 road, road rs 232 serial interface signals are sent to subordinate by described the second connector group (8); Described receive clock generation unit (11) is connected with described FPGA reception & disposal unit (9), and described receive clock generation unit (11) is for generating reference clock and offer described FPGA reception & disposal unit (9).
Alternatively, in device as above, described FPGA transmission processing unit (4) comprises Camera Link agreement string modular converter (12), a UART module (13), gap marker and cache module (14), bus-sharing module (15), speed module (16) and a GTP module (17); Described FPGA reception & disposal unit (9) comprises Camera Link agreement parallel serial conversion module (18), the 2nd UART module (19), bus demultiplexing module (20), reduction of speed module (21) and the 2nd GTP module (22).
Alternatively, in device as above, described Camera Link agreement string modular converter (12) are converted to 84 road LVTTL level parallel signals specifically for the Camera Link agreement LVDS level diagram image signal on Jiang12 road with the ratio of 1:7; Described Camera Link agreement parallel serial conversion module (18) is converted to 12 road Camera Link agreement LVDS level bus signals specifically for Jiang84 road LVTTL level parallel signal with the ratio of 7:1.
Alternatively, in device as above, described Camera Link agreement string modular converter (12) comprise that input difference turns single-ended clock buffer IBUFGDS (23), input difference turns single ended buffer IBUFDS (24), delayer IODLY (25), input deserializer ISERDES (26), phase-locked loop pll (27) and sampled point delay controller (28); Described input difference turns single ended buffer IBUFDS (23) and through described delay line IODLY (25), inputs to described deserializer ISERDES (26) for differential data signals being converted to single-ended signal; Described input difference turns single-ended clock buffer IBUFDS (23) and sends into described phase-locked loop pll (27) for differential pixel clock signal being converted to single-ended pixel clock signal; Described phase-locked loop pll (27) is for generating 7 frequency multiplication high-speed sampling clocks, and after it is alignd with pixel clock phase, sends into described input deserializer ISERDES (26); Described input deserializer ISERDES (26) exports parallel data after unstringing for the 1:7 of settling signal; Sampled point delay controller (28) is carried out sampled point search and control method, and the delay that completes data channel regulates.
Alternatively, in device as above, described sampled point delay controller (28) is for dividing between the state area of monocycle signal, by regulating the result after the delay of data channel and detection are unstringed, the sampling location that automatic searching is suitable, the sampling of high-speed sampling clock, along aliging with the ideal interval of data, is met to foundation and the retention time of register while guaranteeing sampling; The search of described sampled point delay controller (28) specific implementation sampled point and the processing procedure regulating comprise: the stability region of calculative determination cycle data and unstable region, and stability region is divided into three intervals according to the minimum step of delayer resource in sheet, and definite ideal is interval; After resetting, detect the data of the output of unstringing, judge sampling clock along present position and select to enter coarse adjustment pattern or accurate adjustment joint pattern; Coarse adjustment pattern, by regulating data path to postpone, makes sampling clock edge to the stability region in data; After completing, coarse adjustment enters accurate adjustment joint pattern; Accurate adjustment joint pattern postpones judgement sample point in which kind of interval of stability region by increasing and reducing, and makes respectively corresponding delay adjusting, makes sampling clock interval along the ideal at middle part, alignment stability region; Accurate adjustment has saved rear continuation monitoring and has separated the result of string data and repeat said process, regulates in real time sampling point position.
Alternatively, in device as above, described Camera Link agreement parallel serial conversion module (18) comprises output single-ended transfer difference buffer OBUFDS (29), output serializer OSERDES (30) and phase-locked loop pll (31); Described bus demultiplexing module (20) and described reduction of speed module (21) are sent into described output serializer OSERDES (30) by Camera Link parallel image data and low speed after reduction with road clock respectively; Described phase-locked loop pll (31) is sent into described output serializer OSERDES (30) for generating 7 frequency multiplication high-frequency clocks; Described output serializer OSERDES (30) is for sending into described output single-ended transfer difference buffer OBUFDS (29) by parallel signal in the serialization of 7:1 ratio; Described output single-ended transfer difference buffer OBUFDS (29) is for being that LVDS differential level is exported by the Camera Link picture signal after pixel clock signal and stringization by single-ended level conversion.
Alternatively, in device as above, the bus-sharing controller in described bus-sharing module (15) is for controlling the time division multiplexing that MUX completes data/address bus; Described bus-sharing controller detects video image frame synchronizing signal effective status, prioritised transmission vedio data when picture frame synchronizing signal is effective; When frame synchronizing signal is invalid, utilize the universal serial port data of the slot transmission multi-path low speed of interframe invalid data, the standby condition of the every road of described bus-sharing controller cycle detection serial data, the serial ports channel data that control bus transmission buffer is ready to complete in real time;
Bus demultiplexing controller in described bus demultiplexing module (20), for detection of the traffic identifier position in input parallel signal bus, judges the multiplexing window of picture signal and general serial signal, completes the shunt operation of picture signal stream and serial signal stream; When general serial signal demultiplexing, sense channel flag, sends data exchange into each serial signal passage by shunt selector.
Alternatively, in device as above, described speed module (16) adopts the built-in digital dock administrative unit stone in FPGA transmission processing unit (4) that 28 channel parallel datas are obtained to data/address bus Sui road synchronised clock after speed with road clock 2 frequencys multiplication phase retardation; Then by 28 circuit-switched data buses are merged into 14 circuit-switched data buses by the mode that frequency doubling clock alternately reads two paths of data within the single slow clock cycle.
Alternatively, in device as above, described FPGA transmission processing unit (4) and the device model of FPGA reception & disposal unit (9) are XC5VLX50T.
Alternatively, in device as above, described tranmitting data register generation unit (7) and described receive clock generation unit (11) adopt SI5323 and peripheral circuit thereof.
The present invention's beneficial effect is compared with prior art:
(1) mixed signal fiber transmission device of the present invention can be realized the real-time Optical Fiber Transmission of the general serial signal of Camera Link form High-speed video images signal He10 road 460.2k baud rate.The present invention can support high pixel clock frequency 90Mbps under syntype, the Camera Link High-speed video images signal transmission of total bandwidth 7.56Gbps; Adopt monomode fiber to make the transmission range of this device can reach km rank.
(2) the present invention proposes that a kind of Camera Link agreement based on FPGA is unstringed and the scheme of string, and when unstringing the method for automatic search data acquisition sampling point, realized Embedded being correctly decoded of Camera Link agreement.This scheme has substituted the DS90CR28X series application-specific integrated circuit (ASIC) that is not suitable for technical grade low-temperature working that traditional Camera Link equipment is used, and transmitting device temperature accommodation is expanded; Reduce the use of application-specific integrated circuit (ASIC) simultaneously, improved circuit reliability, reduced cost and power consumption.
(3) the present invention proposes a kind of High-speed video images signal and the multiplexing and Deplexing method of low speed general serial signal to same bus, realized different rates and different-format signal in the fusion transmission of same bus and recovered, improve the utilization ratio of bandwidth chahnel, reduced the quantity of optical-fibre channel.
(4) shake of outside pll clock generator filtering Camera Link clock for the present invention, makes reference clock meet the jitter toleration of kilomegabit serial transceiver internal clock data recovery unit; Guarantee the user clock of high speed serialization transceiver and the relation of pixel clock homology simultaneously, simplified data simultaneous operation.
(5) the present invention adopts the built-in high-speed transceiver GTP of FPGA carry out the high speed string of digital signal and unstring.This high-speed transceiver integrated level is high, low in energy consumption and electromagnetic interference performance good, and its programmable control mode facilitates user to be configured and Function Extension according to the needs that customize.
(6) the speed module in the present invention and reduction of speed module have been adjusted transmission rate (with road clock frequency) and bit wide in the situation that guaranteeing that parallel signal bus bandwidth is constant, circuit structure is simple and reliable, has effectively utilized interconnected high speed characteristics in FPGA sheet when having saved parallel port figure place.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of the mixed format signal optical fibre transmitting device that Fig. 1 provides for the embodiment of the present invention.
The structural representation of FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 2 A provides for the embodiment of the present invention.
The structural representation of FPGA reception & disposal unit in the mixed format signal optical fibre transmitting device that Fig. 2 B provides for the embodiment of the present invention.
The structural representation of Camera Link agreement string modular converter 12 in FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 3 provides for the embodiment of the present invention.
The structural representation of Camera Link agreement parallel serial conversion module 18 in FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 4 provides for the embodiment of the present invention.
Fig. 5 is input data stabilization window and the sampling clock schematic diagram along position that unstrings in the embodiment of the present invention.
Fig. 6 is the sampled point search of embodiment of the present invention employing and the implementing procedure figure of control method.
Fig. 7 is that in the embodiment of the present invention, speed module is merged into two-way low speed data the sequential chart of single channel speed data.
Fig. 8 is the structural representation of bus-sharing module 15 in the embodiment of the present invention.
Fig. 9 is the structural representation of bus demultiplexing module 20 in the embodiment of the present invention.
Embodiment
For making object, technical scheme and the advantage of the embodiment of the present invention clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The structural representation of the mixed format signal optical fibre transmitting device that Fig. 1 provides for the embodiment of the present invention.As shown in Figure 1, the mixed format signal optical fibre transmitting device of the present embodiment comprises transmitting terminal 1, optical-fibre channel 2 and receiving terminal 3; As shown in Figure 1, transmitting terminal 1 is arranged on mixed signal optical fiber transmitter card, and receiving terminal 3 is arranged on fiber-optic signal circuit board for receiving.Transmitting terminal 1 comprises FPGA transmission processing unit 4, the first connector group 5, photoelectric conversion unit 6 and tranmitting data register generation unit 7; For example the first connector group 5 is wherein comprised of two MDR26 connectors and 10 rs 232 serial interface signal connectors.For example photoelectric conversion unit 6 is comprised of three groups of SFP optical transceivers, and the maximum transmission rate of each optical transceiver is 3.75Gbps; For example tranmitting data register generation unit 7 is comprised of a slice SI5323 and peripheral circuit thereof.
Optical-fibre channel 2 comprises three groups of monomode fibers, i.e. optical-fibre channel 2 Wei San road monomode fibers.Optical-fibre channel 2 connects transmitting terminal 1 and receiving terminal 3; Receiving terminal 2 comprises the second connector group 8, FPGA reception & disposal unit 9, electrooptic switching element 10 and receive clock generation unit 11.
FPGA transmission processing unit 4 is connected with photoelectric conversion unit 6 with the first connector group 5 respectively; Three groups of SFP optical transceivers of photoelectric conversion unit 6, for receiving from the first connector group 5 12 road LVDS level Camera Link format video picture signal He10 road general serial signals and the signal of reception being converted to the high-speed serial signals of three road CML level, are sent in FPGA transmission processing unit 4; Photoelectric conversion unit 6 sends to receiving terminal 3 for converting electrical signals to light signal by optical-fibre channel 2; Tranmitting data register generation unit 7 is connected with FPGA transmission processing unit 4 with the first connector group 5 respectively, tranmitting data register generation unit 7, for receiving the 1 road LVDS pixel clock signal from the first connector group 5, offers FPGA transmission processing unit 4 through eliminating dithering process by clock;
FPGA reception & disposal unit 9 is connected with electrooptic switching element 10 with optical-fibre channel 2 respectively; Three groups of SFP optical transceivers in electrooptic switching element 10 input to FPGA reception & disposal unit 9 after optical-fibre channel 2 is transmitted to the high-speed serial signals that San road light signal is converted to three road CML forms; FPGA reception & disposal unit 9 for Jiang San road high-speed serial signals process and revert to 12 road LVDS level Camera Link vision signals, 3 LVDS channel associated clock signal He10 road, road rs 232 serial interface signals are sent to subordinate by the second connector group 8; Receive clock generation unit 11 is connected with FPGA reception & disposal unit 9, and receive clock generation unit 11 is for generating reference clock and offer FPGA reception & disposal unit 9.
Signal conversion and the processing procedure of described transmitting terminal 1 are as follows: 12 pairs of LVDS vision signals and 10 pairs of general serial signals input to FPGA transmission processing unit 4 from receiving the first connector group 5, for reducing the deflection between differential pair, each PCB layout to vision signal such as takes at the long process.10 road general serial signals input to FPGA transmission processing unit 4 by 10 rs 232 serial interface signal connectors of the first connector group 5.FPGA transmission processing unit 4 is converted to the signal of input three road high-speed serial signals and is sent to photoelectric conversion unit 6.Photoelectric conversion unit 6 is converted to light signal by high-speed serial signals, and by optical fiber, sending to circuit board for receiving is receiving terminal 3.Tranmitting data register generation unit 7 provides the clock of low jitter for FPGA transmission processing unit 4.
Described FPGA transmission processing unit 4 is cores of transmitting terminal, is responsible for conversion process and the transmission of signal and controls.
Described Camera Link agreement string modular converter 12Jiang 12 road LVDS level Camera Link format signals are converted to 84 road LVTTL level parallel data signals, go here and there and change than being 7:1, and it is 7 road parallel signals that Ji Mei road LVDS differential signal unstrings.Camera Link agreement string modular converter comprise three identical submodules, and first submodule is converted to 28 road parallel signals by 4 road LVDS signals of corresponding BASE type; Second 4 additional road LVDS signal of the corresponding MEDIUM type of sub-module converts, the 3rd 4 additional road LVDS signals of the corresponding FULL type of sub-module converts.
The structural representation of FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 2 A provides for the embodiment of the present invention.The structural representation of FPGA reception & disposal unit in the mixed format signal optical fibre transmitting device that Fig. 2 B provides for the embodiment of the present invention.As shown in Figure 2 A, FPGA transmission processing unit 4 comprises that Camera Link agreement string modular converter 12, a UART module 13, gap marker and cache module 14, bus-sharing module 15, speed module 16 and a GTP module 17 realize its function.As shown in Figure 2 B, FPGA reception & disposal unit 9 comprises that Camera Link agreement parallel serial conversion module 18, the 2nd UART module 19, bus demultiplexing module 20, reduction of speed module 21 and the 2nd GTP module 22 realize its function.
For example, Camera Link agreement string modular converter 12 are converted to 84 road LVTTL level parallel signals specifically for the Camera Link agreement LVDS level diagram image signal on Jiang12 road with the ratio of 1:7; Camera Link agreement parallel serial conversion module 18 is converted to 12 road Camera Link agreement LVDS level bus signals specifically for Jiang84 road LVTTL level parallel signal with the ratio of 7:1.
The structural representation of Camera Link agreement string modular converter 12 in FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 3 provides for the embodiment of the present invention.As shown in Figure 3, Camera Link agreement string modular converter 12 comprise that input difference turns single-ended clock buffer IBUFGDS23, input difference turns single ended buffer IBUFDS24, delayer IODLY25, input deserializer ISERDES26, phase-locked loop pll 27 and sampled point delay controller 28; Input difference turns single ended buffer IBUFDS23 and through delay line IODLY25, inputs to deserializer ISERDES26 for differential data signals being converted to single-ended signal; Input difference turns single-ended clock buffer IBUFDS23 and sends into phase-locked loop pll 27 for differential pixel clock signal is converted to single-ended pixel clock signal; Phase-locked loop pll 27 is for generating 7 frequency multiplication high-speed sampling clocks, and after it is alignd with pixel clock phase, sends into input deserializer ISERDES26; Input deserializer ISERDES26 exports parallel data after unstringing for the 1:7 of settling signal; Sampled point delay controller 28 is for carrying out sampled point search and control method, and the delay that completes data channel regulates.
In the present embodiment, Camera Link agreement string modular converter 12 design high conversion rates are 630Mbps, and corresponding parallel data speed is 630Mbps/7=90Mbps.As shown in Figure 3, the IBUFDS24 in Camera Link agreement string modular converter 18 is converted to single-ended LVTTL level signal by differential data signals.12 circuit-switched data signals after conversion input to delayer 25; IBUFGDS23 is converted to single-ended clock signal by LVDS differential clock signal and inputs to phase-locked loop pll.Delayer IODLY is for the time delay in fine adjustment path.INC and CE signal by sampled point delay controller 28 control lag devices 25 complete the increase and decrease to the time delay of transfer of data, and unit time delay step-length is 78ps.Signal after time delay adjustment exports solution string location to.Phase-locked loop pll 27 receives single-ended with road pixel clock and carry out 7 frequencys multiplication and phase alignment: the clock HCLK after frequency multiplication and pixel clock PCLK are offered to the ISERDES that separates in string location in the lump for unstringing, respectively corresponding CLK and CLKDIV mouth.4 road serial bus signals carry out 1:7 by 4 solution string locations and unstring.Each solution string location consists of two ISERDES cascades, and wherein main ISERDES is used Q1 to do front 6 outputs to Q6, and inferior ISERDES is used Q3 mouth to do the 7th output, and the SFO1 of main ISERDES is connected with SFI2 with the SFI1 of inferior ISERDES respectively with SFO2.4 separate string location output totally 28 LVTTL level diagrams as bus data.
Sampled point delay controller 28 connects IODLY and conciliates string location, detect and judge that whether the data of the output of unstringing are correct and stable, and by control signal CE and INC, increase and decrease the delay of each circuit-switched data in IODLY according to described sampled point method for searching, make the rising edge of sampling clock can be aligned in the center of data stabilization state.BITSLIP position slip signals, for adjusting the border of unstringing, is unstringed and is slided and can search the correct border of unstringing for 7 times at most for 1:7.
Alternatively, in device as above, sampled point delay controller 28 is for dividing between the state area of monocycle signal, by regulating the result after the delay of data channel and detection are unstringed, the sampling location that automatic searching is suitable, the sampling of high-speed sampling clock, along aliging with the ideal interval of data, is met to foundation and the retention time of register while guaranteeing sampling.
The 28 specific implementation sampled point search of sampled point delay controller and the processing procedure regulating comprise:
(1) stability region of calculative determination cycle data and unstable region, and stability region is divided into three intervals according to the minimum step of delayer resource in sheet, and definite ideal is interval;
(2) after reset, detect the data of the output of unstringing, judgement sampling clock also selects to enter coarse adjustment pattern or accurate adjustment joint pattern along present position;
(3) coarse adjustment pattern, by regulating data path to postpone, makes sampling clock edge to the stability region in data; After completing, coarse adjustment enters accurate adjustment joint pattern;
(4) accurate adjustment joint pattern postpones judgement sample point in which kind of interval of stability region by increasing and reducing, and makes respectively corresponding delay adjusting, makes sampling clock interval along the ideal at middle part, alignment stability region;
(5) accurate adjustment has saved the result of rear continuation monitoring solution string data and has repeated said process, regulates in real time sampling point position.
The structural representation of Camera Link agreement parallel serial conversion module 18 in FPGA transmission processing unit in the mixed format signal optical fibre transmitting device that Fig. 4 provides for the embodiment of the present invention.As shown in Figure 4, Camera Link agreement parallel serial conversion module 18 comprises output single-ended transfer difference buffer OBUFDS29, output serializer OSERDES30 and phase-locked loop pll 31; Bus demultiplexing module 20 and reduction of speed module 21 are sent into output serializer OSERDES30 by the Camera Link parallel image data after reduction and low speed with road clock respectively; Phase-locked loop pll 31 is sent into output serializer OSERDES30 for generating 7 frequency multiplication high-frequency clocks; Output serializer OSERDES30 is for sending into output single-ended transfer difference buffer OBUFDS29 by parallel signal in the serialization of 7:1 ratio; It is that LVDS differential level is exported by single-ended level conversion that output single-ended transfer difference buffer OBUFDS29 is used for the Camera Link picture signal after pixel clock signal and stringization.
For example the Camera Link agreement parallel serial conversion module 18 in receiving terminal 3 can comprise three Camera Link agreement parallel-serial conversion submodules, and Qi Jiang 84 road parallel signals are converted to 12 road LVDS level Camera Link signals.
Each Camera Link protocol conversion module can adopt Jiang28 road, 4 OSERDES unit parallel signal string to turn to 4 road high speed signals; PLL31 carries out pixel clock PCLK to offer OSERDES after 7 frequencys multiplication alignment phase; OBUFDS29 is to send after LVDS level by the LVTTL level conversion of high speed signal and pixel clock signal.
Alternatively, the FPGA transmission processing unit (4) in the present embodiment and FPGA reception & disposal unit (9) device model can adopt the FPGA device type of XC5VLX50T model.
Alternatively, the tranmitting data register generation unit 7 in the present embodiment and receive clock generation unit 11 adopt SI5323 and peripheral circuit thereof.
Fig. 5 unstrings input data stabilization window and sampling clock along the schematic diagram of position in the embodiment of the present invention, described the sequential of the sampled data of input deserializer ISERDES26.As shown in Figure 5, T represents the one-period of data, and input deserializer ISERDES26 is in the rising edge sampled data of clock.The pixel clock of take describes as design peak 90MHz as example: Camera Link serial data rate is 630Mbps, and T is 1.59ns; T
rsmkin the time interval that represents data labile state, comprise three parts: T wherein
pjfor the shake that phase-locked loop brings, maximum 0.179ns; T
shbe foundation and the retention time of ISERDES, representative value is 0.34ns; T
skewrepresent the fixedly deflection between different differential pairs, maximum is 0.182ns; T
rsmk=T
pj+ T
sh+ T
skew=0.701ns.Show that sampling clock is T-T along being aligned in width in figure
rsmkthe T of=1.59-0.701=0.889ns
eguarantee sampled data correctly in region.T
eregion is divided into L (left hand edge), C (centre), three regions of R (right hand edge), and desirable sample is in T
emiddle C region, left and right edges peak width is about 0.3ns, is slightly less than the unit delay step-length (78ps * 4=0.312ns) of an integer ISERDES.When in other operating frequencies, T
ethe dividing mode in region is similar to the above process, guarantees that left and right edges peak width is lower than an optional integer ISERDES unit delay step-length.
Described sampled point delay controller 28, its principle is that the data of unstringing according to detection are adjusted in real time signal delay and then obtained suitable sampled point.As shown in Figure 6, be the sampled point search of embodiment of the present invention employing and the implementing procedure figure of control method, specific as follows:
(1) after reset, first detect and judge that whether the data of the output of unstringing are correct and stable.Camera Link signal bus Zhong You tri-road signals are the synchronous control signals with associated sequential, are respectively frame synchronizing signal FVAL, line synchronizing signal LVAL and data useful signal DVAL, have following logical relation: DVAL=FVAL and LVAL.When signal being detected, meet this logical relation, and FVAL has, and when fixedly rising edge occurs, can to show to separate string data correct.Compare with general transmission midamble code pattern, this detection mode has advantages of real-time, can when normal transmission data, continue to monitor the result of unstringing.
(2) correct when detect separating string data, illustrate that sampling clock edge is at T
eregion, state machine redirect directly enters smart adjustment state; If it is wrong that step 1 detects data, illustrate that sampling clock edge is at T
rsmkregion, enters coarse adjustment state: data are reduced and postpone 10 step-lengths, make sampling clock along being aligned in T
eregion.
(3) object of accurate adjustment joint pattern is along being aligned in T by sampling clock
emiddle part C interval.First data are reduced and postpone 4 step-lengths, then rebound detected state detects output data.Because 4 step-lengths have surpassed width between Zone R, if testing result mistake illustrates that original clock saves forward position between Zone R in this step, therefore add that 8 step-lengths just can be by clock edge to interval at C.If detected correctly, illustrate that original clock is along interval in L or interval in C.
(4) data are increased and postpone 4 step-lengths, then detect: if detected, pass through, illustrate that sampling clock, along be in C interval before this step joint, reduces by 4 step-lengths and returns to C interval; If detection misdirection, illustrates that sampling clock is along be in L interval before this step joint, then can be by clock edge to interval at C by 8 step-lengths of data minimizing delay.
(5) complete after above step and guaranteed that generally clock is along being aligned in C interval, due to data unstable region T
rsmkbe maximum estimated, have sampling clock along being aligned in T
rsmkduring window inside edge, unstring correct, the wrong situation but unstringing may appear in the situations such as variation of ambient temperature, voltage fluctuation, therefore need to knock-on and continue to detect to detecting pattern.
After above-mentioned steps is processed, Camera Link agreement string modular converter Jiang12 road LVDS bus signals are converted to 84 road parallel signals, and 28 signals corresponding to BASE pattern are sent into bus-sharing module 15; The 56 parallel-by-bit signals corresponding to Medium and Full pattern are directly sent into speed module.
The serial port signal of described UART module 13Jiang 10 road 460.8k baud rates is gone here and there and changes, and single channel general serial signal is converted to 8bit valid data position and 1bit check digit totally 9 parallel-by-bit data.
The rs 232 serial interface signal difference number-mark of described gap marker and 14 pairs 10 parallelizations of passage of cache module is so that receiving terminal demultiplexing.Identify rear 10 signal bus bit wides and increase to 13, wherein high 4 is gap marker position.Gap marker and cache module 14 are used asynchronous FIFO to realize the caching from low frequency serial ports clock to the cross clock domain of high-frequency pixel clock.Standard universal rs 232 serial interface signal for 460.8k baud rate, comprises start bit and position of rest, the parallel data of maximum transmission 460.8k/10=46.08k bytes per second.Consider under extreme case effectively also to continue to receive 10 road general serial data when (FVAL is height) when view data, owing to needing the vision signal that prioritised transmission requirement of real-time is higher, so the asynchronous FIFO degree of depth of the buffer unit of every road serial signal need to be greater than the serial data amount of a two field picture time (1.5ms), so the degree of depth of the asynchronous FIFO in gap marker and cache module 14 is [1.5/ (1/46.08)]=70 bytes.The reading out data rate of FIFO (pixel clock frequency is 80MHz) is [80M/46.08k]=1736 > 70 * 10=700 with the ratio that writes serial data rate, the totally 700 groups of data that show 10 road FIFO buffer memorys can be sent in the clock cycle at a serial ports with the frequency of 80MHz, so need not consider to read successively the additional FIFO buffer memory degree of depth that different passage serial datas bring, the FIFO degree of depth selects to be greater than 70 integer value.
The video image acquisition equipment of the actual use of engineering bandwidth of picture signal under the highest frame frequency and ultimate resolution operating state time is 6.4Gbps, lower than the bandwidth 7.56Gbps of fiber transmission device; And the data of parallel image signal bus are just only that effectively FVAL pulsewidth is 1.5ms when frame synchronizing signal FVAL is high level, and the invalid data window width of two interframe is about 0.8ms, all shows that parallel bus has surplus to carry out the transmission of all the other low speed signals.
Fig. 7 is that in the embodiment of the present invention, speed module is merged into two-way low speed data the sequential chart of single channel speed data.Speed module obtains speed clock CLK2X by low speed with road clock CLK bis-frequencys multiplication positive jayrator 90 degree, at single low-speed clock, in the cycle, with speed clock, gather successively each of first via low speed data and the second road low speed data and obtain speed data, after cycling, the data of two-way low speed just synthesize road data at a high speed accordingly, realized output bus bit wide and reduced by half, transmission frequency doubles.90 degree phase shifts of speed clock have left enough register holding time surpluses for gathering low speed data, have guaranteed that two-way low speed data is stable when sampling.Signal after speed is sent into a GTP module 17 through the user clock of GTP transceiver synchronously.
A described GTP module 17 is the programmable high-speed transceiver stones in FPGA, has the advantages such as flexible configuration and Electro Magnetic Compatibility are good.The one GTP module 17 completes coding, stringization, the frequency multiplication to parallel data signal, and the high-speed serial signals that three groups of mixed format parallel data signals is converted to three road CML level sends to electrooptic switching element 6.In actual use, video image acquisition device pixel clock is 80MHz, and mode of operation is FULL, and the speed factor is 2, through 8B10B coding rear port, expands to 20, and single channel serial signal speed reaches 80MHz * 2 * 20=3.2Gbps.The serial electric signal of 6 three groups of SFPJiang of electrooptic switching element, tri-road CML level is converted to three road light signals, by monomode fiber, sends to mixed signal Optical Fiber Transmission circuit board for receiving.SI5323, by offering a GTP module 17 after pixel clock filtering shake, guarantees that its inner clock and data recovery unit possesses the reference clock lower than jitter toleration.The user clock and the pixel clock that due to a GTP module 17, generate are homology clocks, there is not the small frequency difference problem of non-homogeneous clock, when being inputed to high-speed transceiver, bus signals only need to, by simple synchronous, avoid complicated asynchronous buffer operation and additional signal delay.
As shown in Figure 1, mixed signal fiber transmission device receiving terminal 3 comprises the second connector group 8, electrooptic switching element 10 and receive clock generation unit 11: wherein the second connector group 8 is comprised of two MDR26 connectors and 10 serial ports connectors; Electrooptic switching element 10 is comprised of three groups of SFP optical transceivers; Receive clock generation unit 11 is comprised of a slice SI5323 and peripheral circuit thereof.
Described receiving terminal 3 is reverse process of transmitting terminal 1, is about to light signal and recovers to be reduced to LVDS form Camera Link vision signal He10 road serial port power signal.Electrooptic switching element 10 is converted to the light signal of inputting by optical fiber the high-speed serial signals of three road CML forms and inputs to FPGA reception & disposal unit 9.FPGA reception & disposal unit 9 Jiang San road high-speed serial signals are reduced to LVDS level Camera Link vision signal He10 road, 15 tunnels (12 circuit-switched data and 3 road clocks) rs 232 serial interface signal after processing, and by the second connector group 8, are sent to subordinate.Receive clock generation unit 11 generates low-jitter clock by a slice SI5323 by crystal clock source independently and offers high-speed transceiver clock for referencial use.
As shown in Figure 2, described FPGA reception & disposal unit 9 comprises Camera Link agreement parallel serial conversion module 18, the 2nd UAR T module 19, bus demultiplexing module 20, reduction of speed module 21, the 2nd GTP module 22.The 2nd GTP module 22 is converted to three groups of 16 GTP parallel data streams by the high-speed serial signals of CML form, by reduction of speed module 21, the parallel data stream transmission rate (with road clock frequency) of three groups 14 (in 16 of GTP output containing 2 redundant digits) is reduced by half subsequently and port number doubles, revert to three groups of 28 parallel datas that pixel clock is synchronous.
Fig. 8 is the structural representation of bus-sharing module 15 in the embodiment of the present invention.As shown in Figure 8, bus-sharing module 15 comprises bus-sharing controller 32 and MUX 33.Functional unit, signal that Fig. 8 has described bus-sharing module 15 flow to and multiplexing sequential.Bus-sharing controller 32 is controlled MUX 33, completes the time division multiplexing of view data and the defeated bus of multichannel serial data mutual transmission.Multiplexing detailed process is as follows: multiplex controller detect the state of frame synchronizing signal FVAL: FVAL when high level by MUX by bus switch to sending view data; When low level, switch to and send serial data stream.When sending serial data, bus-sharing controller cycle detection, from gap marker and cache module 14 input 10 road buffer memory ready signals, finds that buffer memory ready signal is just switched to output bus this passage and sends serial data when effective.Because view data there will not be the i.e. { FVAL of the effective situation of the invalid while LVAL of FVAL, LVAL}=" 01 ", FVAL and the LVAL position of therefore serial data being flowed to correspondence image data flow increase by two bit stream flags and assignment " 01 ", and receiving terminal just can differentiate between images data and serial data by detecting traffic identifier position like this.After identification process, serial data stream bit wide amounts to 15, with 28 bit image data low 13 and FVAL (the 25th), LVAL (the 26th) multiplexing, during transmitting serial port data, redundant digit is set to 0.28 bus signals after multiplexing input to speed module 16.
Bus-sharing controller 32 in bus-sharing module 15 in the present embodiment completes the time division multiplexing of data/address bus for controlling MUX 33; Bus-sharing controller 32 detects video image frame synchronizing signal effective status, prioritised transmission vedio data when picture frame synchronizing signal is effective; When frame synchronizing signal is invalid, utilize the universal serial port data of the slot transmission multi-path low speed of interframe invalid data, the standby condition of the bus-sharing controller 32 every road of cycle detection serial datas, the serial ports channel data that control bus transmission buffer is ready to complete in real time.
Alternatively, the speed module in the present embodiment 16 adopts digital dock administrative unit in FPGA transmission processing unit (4) that 28 channel parallel datas are obtained to data/address bus Sui road synchronised clock after speed with road clock 2 frequencys multiplication phase retardation; Then by 28 circuit-switched data buses are merged into 14 circuit-switched data buses by the mode that frequency doubling clock alternately reads two paths of data within the single slow clock cycle.
Particularly, the speed module 16 in the present embodiment doubles parallel data bus line speed (Ji Sui road clock frequency doubles); Bus bit wide is dwindled half.The video bus on Dan Zu 28 tunnels bit wide after speed module 16 is processed shortens to 14 tunnels, can mate the limited port bit wide of GTP module (16 of the maximum bit wides of single GTP) and effectively utilize the high frequency treatment characteristic of FPGA.San Zu 28 road parallel bus signals are converted to San Zu 14 road parallel bus signals after speed module; Pixel clock frequency with road doubles.
Fig. 9 is the structural representation of bus demultiplexing module 20 in the embodiment of the present invention.As shown in Figure 9, bus demultiplexing module 20 comprises demultiplexing controller 34 and shunt selector 35: demultiplexing controller detects first group of 28 traffic identifier position in parallel-by-bit bus signals, the multiplexing window of the general serial signal of real-time differentiate between images signal and parallelization, and complete de-multiplex operation, the general serial signal of picture signal and parallelization is inputed to respectively to Camera Link and go here and there protocol conversion module 18 and the 2nd UART19 module; When serial data Propagation solution is multiplexing, detect serial ports gap marker position, by shunt selector, data are sent into each general serial transceiver in the 2nd UART19 module.The 460.8k baud rate general serial signal that the 2nd UART module 19 is converted to standard by data exports the second connector group 8 to by IO mouth.Bus demultiplexing controller 34 in bus demultiplexing module 20 in the present embodiment is for detection of the traffic identifier position in input parallel signal bus, judge the multiplexing window of picture signal and general serial signal, complete the shunt operation of picture signal stream and serial signal stream; When general serial signal demultiplexing, sense channel flag, sends data exchange into each serial signal passage by shunt selector 35.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a mixed format signal optical fibre transmitting device, is characterized in that: comprise transmitting terminal (1), optical-fibre channel (2) and receiving terminal (3); Described transmitting terminal (1) comprises FPGA transmission processing unit (4), the first connector group (5), photoelectric conversion unit (6) and tranmitting data register generation unit (7); Described optical-fibre channel (2) comprises three groups of monomode fibers, and described optical-fibre channel (2) connects described transmitting terminal (1) and described receiving terminal (3); Described receiving terminal (2) comprises the second connector group (8), FPGA reception & disposal unit (9), electrooptic switching element (10) and receive clock generation unit (11);
Described FPGA transmission processing unit (4) is connected with described photoelectric conversion unit (6) with described the first connector group (5) respectively; Three groups of SFP optical transceivers of described photoelectric conversion unit (6), for receiving from described the first connector group (5) 12 road LVDS level Camera Link format video picture signal He10 road general serial signal and the signal of reception being converted to the high-speed serial signals of three road CML level, are sent in described FPGA transmission processing unit (4); Described photoelectric conversion unit (6) sends to described receiving terminal (3) for converting electrical signals to light signal by described optical-fibre channel (2); Described tranmitting data register generation unit (7) is connected with described FPGA transmission processing unit (4) with described the first connector group (5) respectively, described tranmitting data register generation unit (7), for receiving the 1 road LVDS pixel clock signal from described the first connector group (5), offers described FPGA transmission processing unit (4) through eliminating dithering process by clock;
Described FPGA reception & disposal unit (9) is connected with described electrooptic switching element (10) with described optical-fibre channel (2) respectively; Three groups of SFP optical transceivers in described electrooptic switching element (10) input to described FPGA reception & disposal unit (9) after for the high-speed serial signals that described optical-fibre channel (2) is transmitted to San road light signal and be converted to three road CML forms; Described FPGA reception & disposal unit (9) for Jiang San road high-speed serial signals process and revert to 12 road LVDS level Camera Link vision signals, 3 LVDS channel associated clock signal He10 road, road rs 232 serial interface signals are sent to subordinate by described the second connector group (8); Described receive clock generation unit (11) is connected with described FPGA reception & disposal unit (9), and described receive clock generation unit (11) is for generating reference clock and offer described FPGA reception & disposal unit (9).
2. device according to claim 1, it is characterized in that, described FPGA transmission processing unit (4) comprises Camera Link agreement string modular converter (12), a UART module (13), gap marker and cache module (14), bus-sharing module (15), speed module (16) and a GTP module (17); Described FPGA reception & disposal unit (9) comprises Camera Link agreement parallel serial conversion module (18), the 2nd UART module (19), bus demultiplexing module (20), reduction of speed module (21) and the 2nd GTP module (22).
3. device according to claim 2, it is characterized in that, described Camera Link agreement string modular converter (12) are converted to 84 road LVTTL level parallel signals specifically for the Camera Link agreement LVDS level diagram image signal on Jiang12 road with the ratio of 1:7; Described Camera Link agreement parallel serial conversion module (18) is converted to 12 road Camera Link agreement LVDS level bus signals specifically for Jiang84 road LVTTL level parallel signal with the ratio of 7:1.
4. device according to claim 2, it is characterized in that, described Camera Link agreement string modular converter (12) comprise that input difference turns single-ended clock buffer IBUFGDS (23), input difference turns single ended buffer IBUFDS (24), delayer IODLY (25), input deserializer ISERDES (26), phase-locked loop pll (27) and sampled point delay controller (28); Described input difference turns single ended buffer IBUFDS (23) and through described delay line IODLY (25), inputs to described deserializer ISERDES (26) for differential data signals being converted to single-ended signal; Described input difference turns single-ended clock buffer IBUFDS (23) and sends into described phase-locked loop pll (27) for differential pixel clock signal being converted to single-ended pixel clock signal; Described phase-locked loop pll (27) is for generating 7 frequency multiplication high-speed sampling clocks, and after it is alignd with pixel clock phase, sends into described input deserializer ISERDES (26); Described input deserializer ISERDES (26) exports parallel data after unstringing for the 1:7 of settling signal; Sampled point delay controller (28) is carried out sampled point search and control method, and the delay that completes data channel regulates.
5. device according to claim 4, it is characterized in that, described sampled point delay controller (28) is for dividing between the state area of monocycle signal, by regulating the result after the delay of data channel and detection are unstringed, the sampling location that automatic searching is suitable, the sampling of high-speed sampling clock, along aliging with the ideal interval of data, is met to foundation and the retention time of register while guaranteeing sampling; The search of described sampled point delay controller (28) specific implementation sampled point and the processing procedure regulating comprise: the stability region of calculative determination cycle data and unstable region, and stability region is divided into three intervals according to the minimum step of delayer resource in sheet, and definite ideal is interval; After resetting, detect the data of the output of unstringing, judge sampling clock along present position and select to enter coarse adjustment pattern or accurate adjustment joint pattern; Coarse adjustment pattern, by regulating data path to postpone, makes sampling clock edge to the stability region in data; After completing, coarse adjustment enters accurate adjustment joint pattern; Accurate adjustment joint pattern postpones judgement sample point in which kind of interval of stability region by increasing and reducing, and makes respectively corresponding delay adjusting, makes sampling clock interval along the ideal at middle part, alignment stability region; Accurate adjustment has saved rear continuation monitoring and has separated the result of string data and repeat said process, regulates in real time sampling point position.
6. device according to claim 2, it is characterized in that, described Camera Link agreement parallel serial conversion module (18) comprises output single-ended transfer difference buffer OBUFDS (29), output serializer OSERDES (30) and phase-locked loop pll (31); Described bus demultiplexing module (20) and described reduction of speed module (21) are sent into described output serializer OSERDES (30) by Camera Link parallel image data and low speed after reduction with road clock respectively; Described phase-locked loop pll (31) is sent into described output serializer OSERDES (30) for generating 7 frequency multiplication high-frequency clocks; Described output serializer OSERDES (30) is for sending into described output single-ended transfer difference buffer OBUFDS (29) by parallel signal in the serialization of 7:1 ratio; Described output single-ended transfer difference buffer OBUFDS (29) is for being that LVDS differential level is exported by the Camera Link picture signal after pixel clock signal and stringization by single-ended level conversion.
7. device according to claim 2, is characterized in that, the bus-sharing controller in described bus-sharing module (15) is for controlling the time division multiplexing that MUX completes data/address bus; Described bus-sharing controller detects video image frame synchronizing signal effective status, prioritised transmission vedio data when picture frame synchronizing signal is effective; When frame synchronizing signal is invalid, utilize the universal serial port data of the slot transmission multi-path low speed of interframe invalid data, the standby condition of the every road of described bus-sharing controller cycle detection serial data, the serial ports channel data that control bus transmission buffer is ready to complete in real time;
Bus demultiplexing controller in described bus demultiplexing module (20), for detection of the traffic identifier position in input parallel signal bus, judges the multiplexing window of picture signal and general serial signal, completes the shunt operation of picture signal stream and serial signal stream; When general serial signal demultiplexing, sense channel flag, sends data exchange into each serial signal passage by shunt selector.
8. device according to claim 2, it is characterized in that, described speed module (16) adopts the built-in digital dock administrative unit stone in FPGA transmission processing unit (4) that 28 channel parallel datas are obtained to data/address bus Sui road synchronised clock after speed with road clock 2 frequencys multiplication phase retardation; Then by 28 circuit-switched data buses are merged into 14 circuit-switched data buses by the mode that frequency doubling clock alternately reads two paths of data within the single slow clock cycle.
9. according to the arbitrary described device of claim 1-8, it is characterized in that, described FPGA transmission processing unit (4) and the device model of FPGA reception & disposal unit (9) are XC5VLX50T.
10. according to the arbitrary described device of claim 1-8, it is characterized in that, described tranmitting data register generation unit (7) and described receive clock generation unit (11) adopt SI5323 and peripheral circuit thereof.
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