CN104113334B - Multimode timing reference input realization device - Google Patents
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Abstract
The invention discloses a kind of multimode timing reference input realization device, the device is made up of five parts such as controlled frequency generator, high quality factor multiband frequency-selective network, multi-modulus frequency divider, automatic frequency alignment unit, data signals to analog signal converter.The timing reference input function of multimode output frequency can be achieved by the setting to its control bit for the present apparatus.While control bit selects multi-modulus frequency divider divide ratio, automatic frequency alignment unit produces digital control position, and through controlling the working condition of controlled frequency generator after data signal to analog signal converter.The output of controlled frequency generator is divided after high quality factor multiband frequency-selective network as the input of multi-modulus frequency divider, automatic alignment unit is delivered in then frequency dividing output again, clock output after calibrated is the final output of whole device, the timing reference input as other electronic installations.The present invention has simple in construction, and clock accuracy is high, it is easy to accomplish, the advantages that cost is cheap；It may replace conventional clock and refer to source device, when needed extensive use in the electronic equipment of clock.
Description
Technical field
The present invention is a kind of multimode timing reference input realization device, predominantly communication, tester, electronic equipment for consumption
Device etc. various electronic applications provides exact references clock.
Background technology
With the rapid development of modern communicationses, control and integrated circuit technique, high stable and high precision timing reference input
Turn into one of critical component for determining that various electronic system performances are good and bad.Particularly in electronic equipment for consumption, constantly
Reducing cost also turns into a technology development and the direct driving force broken through.In the electronic device that integrated level improves constantly, pass
System timing reference input has become bottleneck, and modern electricity is all unable to reach in manufacture, packaging technology, cost and technical performance
The demand of sub- equipment and device.The present invention technically realizes there is epoch-making meaning to the replacement of conventional clock reference source.
Particularly solve that conventional output frequency is single, frequency with time drift motion and the shortcomings of can not realizing high frequency reference clock is anxious
The technical barrier that need to be broken through.Device proposed by the present invention overcomes the shortcomings of above conventional clock reference source, can need
Widely used in the electronic equipment and IC products of clock control.
The content of the invention
Technical problem：The many conventional clock reference sources mainly used in electronic equipment and device at present can not be in the chips
The system integration is carried out, and when there is more height output frequency in clock reference source when desired, it is necessary to using frequency phase lock ring electricity
Double frequency function is realized on road, so as to substantially increase equipment cost.At the same time, the conventional clock reference source under the requirement of high frequency output
Production yield can also substantially reduce therewith.Particularly traditional timing reference input can only often provide single reference clock frequency
Rate.
Technical scheme：
The invention discloses a kind of multimode timing reference input realization device, the device is by controlled frequency generator, high-quality
Factor multiband frequency-selective network, multi-modulus frequency divider, automatic frequency alignment unit, data signal to the part of analog signal converter five
Form.
The timing reference input function of multimode output frequency can be achieved by the setting to its control bit for the present apparatus.In control bit
While selecting multi-modulus frequency divider divide ratio, automatic frequency alignment unit produces digital control position, and through data signal to mould
Intend the working condition that signal adapter controls controlled frequency generator afterwards.The output of controlled frequency generator by high-quality because
Input after plain multiband frequency-selective network as multi-modulus frequency divider is divided, and automatic frequency is delivered in then frequency dividing output again
Alignment unit, it is calibrated after clock output for whole device final output, the timing reference input as other electronic installations.
The present invention has simple in construction, and clock accuracy is high, it is easy to accomplish, the advantages that cost is cheap；It may replace conventional clock reference source dress
Put, can extensive use in the electronic equipment of clock when needed.
Beneficial effect：
The present invention has apparatus structure simple, and output frequency precision is high, is easy to realize in integrated circuits, and cost is cheap
The advantages that；Conventional clock can be substituted to refer to source device extensively, generally used in the electronic equipment of clock when needed.
1st, the present invention is to realize the reference source device of multimode clock frequency output, can be flexible compared with conventional reference source
Setting output frequency, the shortcomings that overcoming the single output frequency in conventional reference source.Connection is simple, it is easy to accomplish, save simultaneously
Power consumption and area.
2nd, the controlled frequency generator in the present invention can produce very high output frequency, without the shadow by the working time
Ring.
3rd, the installation cost in the present invention is low, and yield is high, overcomes conventional clock with reference to source device intermediate frequency rate with extraneous ring
The problems such as drift occur for border；
The present invention can integrate obtains the high reference clock of frequency accuracy in the chips, it is no longer necessary to has the device of outside
To produce reference clock, cost is reduced, is especially suitable for being widely used in each adhesive integrated circuit.
Brief description of the drawings：
Fig. 1 is the block diagram of the present invention.
Fig. 2 is that multi-modulus frequency divider realizes block diagram with what automatic frequency alignment unit cascaded.
Fig. 3 is controlled frequency generator, data signal to analog signal converter and the cascade of automatic frequency alignment unit
Realize block diagram.
Fig. 4 is that high quality factor multiband frequency-selective network realizes block diagram with what automatic frequency alignment unit cascaded.
Fig. 5 is that automatic frequency alignment unit realizes block diagram.
Fig. 6 is the circuit diagram of more mould frequency dividers in first and second embodiment.
Fig. 7 is that the multi-modulus frequency divider of first embodiment realizes block diagram.
Fig. 8 is the partial circuit diagram of automatic frequency alignment unit in first embodiment.
Fig. 9 is that the multi-modulus frequency divider of second embodiment realizes block diagram.
Figure 10 is the partial circuit diagram of automatic frequency alignment unit in second embodiment.
Embodiment
Control bit<C1, C2...Cn>As the input signal of automatic frequency alignment unit, these input signals are by anti-phase
Inversion signal corresponding to device generation, the logical operation that input signal passes through gate circuit with its inversion signal export n control bit<
A1, A2...An>；Then<A1, A2...An>Three groups of control bits are produced respectively<A11, A12...A1n>,<A21, A22...A2n
>,<A31, A32...A3n>；Control bit<C1, C2...Cn>Directly determine the divide ratio of multi-modulus frequency divider；<A1, A2...An>
Output frequency by digital circuit to analog circuit converter indirect control controlled frequency generator；<A1, A2...An>Pass through
Control<A11, A12...A1n>,<A21, A22...A2n>With<A31, A32...A3n>Together decide on high quality factor multiband
Frequency-selective network.Therefore, whole device is by flexibly setting control bit<C1, C2...Cn>Coordinate the design of specific unit module i.e.
Multimode timing reference input can be provided.
Embodiment 1：
Fig. 7 is that the multi-modulus frequency divider of embodiment 1 realizes block diagram.Multi-modulus frequency divider is divided by mould more than three in the present apparatus
Device is formed, and it is respectively s3, s2, s1, c3, c2, c1, d2, d1 to share 8 control bits.Wherein more mould frequency dividers 1, more moulds point
N1, N2 and N3 frequency dividing can be achieved in the combination of the Different Logic of frequency device 2 and more mould frequency dividers 3 respectively.Incoming frequency is fn, pass through
Frequency dividing, the frequency finally exported is fn/ N (wherein N=N1*N2*N3).Fig. 6 is the circuit of more mould frequency dividers of embodiment 1
Figure, the frequency divider by 4 d type flip flops (D1, D2, D3, D4), 3 phase inverters (1,2,3), 4 nor gates (21,22,23,24),
3 NAND gates (31,32,33), an XOR gate (41) are formed.Achievable divide ratio after the connection of mould frequency divider stage more than three
For 40,48,60,64,96,120,128,256 etc..
Fig. 8 is the partial circuit diagram of automatic frequency alignment unit in embodiment 1.Control bit s3, s2, s1, c3, c2, c1,
D2, d1 while the digital input signals as automatic frequency alignment unit, two data signal A2 are exported by logic circuit,
A1, wherein output terminals A 1 input for being achieved in that phase inverter 11, phase inverter 12 input, the output of phase inverter 13, phase inverter
Input of 15 input, the output of phase inverter 16, the output of phase inverter 17, the output of phase inverter 18 as NAND gate 21；It is anti-phase
The input of device 11, the input of phase inverter 12, the output of phase inverter 13, the input of phase inverter 14, the input of phase inverter 15, phase inverter
The input of 16 output, the input of phase inverter 17, the output of phase inverter 18 as NAND gate 22；Phase inverter 18 exports, is anti-phase
The output of device 17, the input of phase inverter 11, the input of phase inverter 12, the output of phase inverter 13, the output of phase inverter 15, phase inverter
Input signal of 16 input as NAND gate 23；The output of NAND gate 21, the output of NAND gate 22, the output of NAND gate 23 are made
For the input signal of NAND gate 27, now the output end of NAND gate 27 is A1 value.The implementation of output terminals A 2 and A1 phases
Seemingly, the output of phase inverter 14, the output of phase inverter 15, the input of phase inverter 11, the input of phase inverter 12, phase inverter 13 it is defeated
Enter, the input signal of the output of phase inverter 17, the output of phase inverter 18 as NAND gate 24；The output of phase inverter 17, phase inverter
16 input, the input of phase inverter 14, the output of phase inverter 15, the output of phase inverter 18, the input of phase inverter 11, phase inverter 13
Input, input signal of the input as NAND gate 25 of phase inverter 12；The input of phase inverter 11, phase inverter 12 input, instead
The output of phase device 13, the output of phase inverter 15, the output of phase inverter 17, the output of phase inverter 18, the input conduct of phase inverter 16
The input signal of NAND gate 26；The output of NAND gate 24, the output of NAND gate 25, the output of NAND gate 26 are as NAND gate 28
Input signal, now the output end of NAND gate 28 is A2 value.Final A1A2 output is ' 00 ', ' 01 ', ' 10 ', ' 11 '.
The output frequency that A1A2 four kinds of combination outputs pass through digital circuit to analog circuit converter indirect control controlled frequency generator
Rate.When A2A1=' 00 ', in a dormant state, system does not have rate-adaptive pacemaker to whole loop；When A2A1=' 01 ', controlled frequency
The output of rate generator is f1；When A2A1=' 10 ', the output of controlled frequency generator is f2；When A2A1=' 11 ', by
The output for controlling frequency generator is f3 (wherein f1, f2, f3 are different design frequencies).Then f1, f2, f3 frequency are as high
The input signal of quality factor multiband frequency-selective network, now under A11, A12 and A21, A22 control, high quality factor is more
Frequency range frequency-selective network selects accurate output frequency f1, f2, f3 in corresponding frequency range.
The input of output frequency f1, f2, f3 first as multi-modulus frequency divider 1, the output signal conduct of multi-modulus frequency divider 1 are more
The input signal of mould frequency divider 2, the input signal of the output signal of multi-modulus frequency divider 2 as multi-modulus frequency divider 3.Work as automatic frequency
The digital input signals of alignment unit are s3s2s1=' 110 ', during c3c2c1=' 010 ', d2d1=' 00 ', multi-modulus frequency divider
Divide ratio is 64, and now the data signal output of automatic frequency alignment unit is A1A2=' 01 ', controlled frequency generator
Output frequency is f1, and the frequency is more after frequency dividing as the input of multi-modulus frequency divider by high quality factor multiband frequency-selective network
The output input as automatic frequency alignment unit again of mould frequency divider, the now output of whole device is f1/64；When automatic
The digital input signals of frequency calibration unit are s3s2s1=' 110 ', during c3c2c1=' 110 ', d2d1=' 00 ', multimode frequency dividing
The divide ratio of device is 128, and now the data signal output of automatic frequency alignment unit is A1A2=' 01 ', and controlled frequency occurs
The output frequency of device is f1, and the frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, frequency dividing
The output input as automatic frequency alignment unit again of multi-modulus frequency divider afterwards, the now output of whole device is f1/128；
It is more during c3c2c1=' 110 ', d2d1=' 00 ' when the digital input signals of automatic frequency alignment unit are s3s2s1=' 110 '
The divide ratio of mould frequency divider is 256, and now the data signal output of automatic frequency alignment unit is A1A2=' 01 ', controlled frequency
The output frequency of rate generator is f1, and the frequency is by high quality factor multiband frequency-selective network, as the defeated of multi-modulus frequency divider
Enter, the output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency dividing, the now output of whole device is
f1/256.When the digital input signals of automatic frequency alignment unit are s3s2s1=' 111 ', the d2d1=' of c3c2c1=' 000 '
When 00 ', the divide ratio of multi-modulus frequency divider is 40, and now the data signal output of automatic frequency alignment unit is A1A2='
10 ', the output frequency of controlled frequency generator is f2, and the frequency is by high quality factor multiband frequency-selective network, as multimode
The input of frequency divider, the output input as automatic frequency alignment unit again of multi-modulus frequency divider, is now entirely filled after frequency dividing
The output put is f2/40；When the digital input signals of automatic frequency alignment unit are s3s2s1=' 111 ', c3c2c1='
During 001 ', d2d1=' 00 ', the frequency dividing ratio coefficient 60 of multi-modulus frequency divider, now the data signal of automatic frequency alignment unit is defeated
It is f2 in the output frequency switched under controlling to go out for A1A2=' 10 ', controlled frequency generation, and the frequency passes through high quality factor
Multiband frequency-selective network, as the input of multi-modulus frequency divider, after frequency dividing the output of multi-modulus frequency divider be used as automatic frequency school again
The input of quasi- unit, the now output of whole device are f2/60；When the digital input signals of automatic frequency alignment unit are
During s3s2s1=' 111 ', c3c2c1=' 101 ', d2d1=' 00 ', the divide ratio of multi-modulus frequency divider is 120, now automatic frequency
The data signal output of rate alignment unit is A1A2=' 01 ', and the output frequency of controlled frequency generator is f2, and the frequency passes through
High quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, the output conduct again of multi-modulus frequency divider after frequency dividing
The input of automatic frequency alignment unit, the now output of whole device are f2/120.It is digital defeated when automatic frequency alignment unit
It is s3s2s1=' 110 ' to enter signal, and during c3c2c1=' 001 ', d2d1=' 00 ', the divide ratio of multi-modulus frequency divider is 48, this
When automatic frequency alignment unit data signal output be A1A2=' 11 ', the output frequency of controlled frequency generator is f3, this
Frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, the output of multi-modulus frequency divider after frequency dividing
Input as automatic frequency alignment unit again, the now output of whole device are f3/48；When automatic frequency alignment unit
Digital input signals are s3s2s1=' 110 ', and during c3c2c1=' 101 ', d2d1=' 00 ', the divide ratio of multi-modulus frequency divider is
96, now the data signal output of automatic frequency alignment unit is A1A2=' 12 ', and the output frequency of controlled frequency generator is
F3, the frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, multi-modulus frequency divider after frequency dividing
The input as automatic frequency alignment unit again is exported, the now output of whole device is f3/96.
Embodiment 2：
Fig. 9 is that the multi-modulus frequency divider of embodiment 2 realizes block diagram.Multi-modulus frequency divider is divided by mould more than two in the present apparatus
Device and a single mode frequency divider are formed, and have 6 control bits, respectively s3, s2, s1, c3, c2, c1.Single mode frequency divider is by two D
Trigger is formed, and can realize 4 frequency dividings, the structure of mould frequency divider more than two and the structure phase of more mould frequency dividers in embodiment 1
Together.
Figure 10 is the partial circuit diagram of automatic frequency alignment unit in embodiment 2.Control bit s3, s2, s1, c3, c2, c1 is same
The digital input signals of Shi Zuowei automatic frequency alignment units, two data signal A2, A1, output end are exported by logic circuit
The A1 input signal for being achieved in that phase inverter 15 and input of the output signal of phase inverter 16 as NAND gate 28, phase inverter
15 output and the input exported as NAND gate 27 of phase inverter 14, the output of NAND gate 27,28 is as the defeated of NAND gate 29
Enter, the output signal of NAND gate 29 gives NAND gate 26, while the input of phase inverter 11, the input of phase inverter 12, phase inverter 13
Input signal of the output as NAND gate 26, the output of NAND gate 26 and exporting as the defeated of NAND gate 31 for NAND gate 25
Enter, now the output end of NAND gate 31 is A1 value.The implementation of output terminals A 2 is similar to A1, the output of phase inverter 11,
The output of phase inverter 13, the output of phase inverter 14, the output of phase inverter 15, the input of phase inverter 12, the input of phase inverter 16 are made
For the input of NAND gate 21；The output of phase inverter 11, the input of phase inverter 12, the input of phase inverter 13, the output of phase inverter 14,
Input of the output of phase inverter 15 as NAND gate 22；The input of phase inverter 12, the input of phase inverter 11, phase inverter 13 it is defeated
Go out, the output of phase inverter 14, the output of phase inverter 15, the input inputted as NAND gate 23 of phase inverter 16；Phase inverter 13
Input, the output of phase inverter 12, the output of phase inverter 11, the input of phase inverter 14, the output of phase inverter 15, phase inverter 16 it is defeated
Enter the input as NAND gate 24；The output of NAND gate 21, the output of NAND gate 22, the output of NAND gate 23 and NAND gate 24
The input as NAND gate 30 is exported, now the output end of NAND gate 30 is A2 value.Finally, A1A2 output be ' 00 ', '
01′、′10′、′11′.A1A2 four kinds of combination outputs pass through digital circuit to analog circuit converter indirect control controlled frequency
The output frequency of generator.When A2A1=' 00 ', in a dormant state, system does not have rate-adaptive pacemaker to whole loop；Work as A2A1
During=' 01 ', the output of controlled frequency generator is f1；When A2A1=' 10 ', the output of controlled frequency generator is f2；When
During A2A1=' 11 ', the output of controlled frequency generator is f3 (wherein f1, f2, f3 are different design frequencies).Then f1,
Input signal of f2, the f3 frequency as high quality factor multiband frequency-selective network, now in A11, A12 and A21, A22 control
Under system, high quality factor multiband frequency-selective network selects accurate output frequency f1, f2, f3 in corresponding frequency range.
The input of output frequency f1, f2, f3 first as single mode frequency divider, four divided output signals after single mode divides are made
For the input signal of multi-modulus frequency divider.When the digital input signals of automatic frequency alignment unit are s3s2s1=' 110 ', c3c2c1
During=' 000 ', the divide ratio of multimode selection frequency divider is 16, and the now data signal output of automatic frequency alignment unit is
A1A2=' 01 ', the output frequency of controlled frequency generator is f1, and the frequency is made by high quality factor multiband frequency-selective network
For the input of multi-modulus frequency divider, the output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency dividing, now
The output of whole device is f1/64；When the digital input signals of automatic frequency alignment unit are s3s2s1=' 110 ', c3c2c1
During=' 010 ', the divide ratio of multi-modulus frequency divider is 32, and now the data signal output of automatic frequency alignment unit is A1A2
=' 01 ', the output frequency of controlled frequency generator is f1, and the frequency is by high quality factor multiband frequency-selective network, as more
The input of mould frequency divider, the output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency dividing, now entirely
The output of device is f1/128；When the digital input signals of automatic frequency alignment unit are s3s2s1=' 110 ', c3c2c1='
When 110 ', the divide ratio of multi-modulus frequency divider is 64, and now the numeral output of automatic frequency alignment unit is A1A2=' 01 ', by
The output frequency for controlling frequency generator is f1, and the frequency is by high quality factor multiband frequency-selective network, as multi-modulus frequency divider
Input, the output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency dividing, now whole device is defeated
Go out for f1/256.It is more during c3c2c1=' 000 ' when the digital input signals of automatic frequency alignment unit are s3s2s1=' 011 '
The divide ratio of mould frequency divider is 10, and now the data signal output of automatic frequency alignment unit is A1A2=' 10 ', controlled frequency
The output frequency of rate generator is f2, and the frequency is by high quality factor multiband frequency-selective network, as the defeated of multi-modulus frequency divider
Enter, the output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency dividing, the now output of whole device is
f2/40；When the digital input signals of automatic frequency alignment unit are s3s2s1=' 011 ', during c3c2c1=' 001 ', multimode point
The divide ratio of frequency device is 15, and now the data signal output of automatic frequency alignment unit is A1A2=' 10 ', and controlled frequency is sent out
The output frequency of raw device is f2, and the frequency, as the input of multi-modulus frequency divider, is divided by high quality factor multiband frequency-selective network
The output input as automatic frequency alignment unit again of multi-modulus frequency divider after frequency, the now output of whole device is f2/60；
When the digital input signals of automatic frequency alignment unit are s3s2s1=' 111 ', during c3c2c1=' 101 ', multi-modulus frequency divider
Divide ratio is 30, and now the data signal output of automatic frequency alignment unit is A1A2=' 01 ', controlled frequency generator
Output frequency is f2, and the frequency is more after frequency dividing as the input of multi-modulus frequency divider by high quality factor multiband frequency-selective network
The output input as automatic frequency alignment unit again of mould frequency divider, the now output of whole device is f2/120.When certainly
The digital input signals of dynamic frequency alignment unit are s3s2s1=' 010 ', during c3c2c1=' 001 ', the frequency dividing of multi-modulus frequency divider
Coefficient is 12, and now the data signal output of automatic frequency alignment unit is A1A2=' 11 ', the output of controlled frequency generator
Frequency is f3, and the frequency is by high quality factor multiband frequency-selective network, and as the input of multi-modulus frequency divider, multimode is divided after frequency dividing
The output input as automatic frequency alignment unit again of frequency device, the now output of whole device is f3/48；Work as automatic frequency
The digital input signals of alignment unit are s3s2s1=' 110 ', during c3c2c1=' 001 ', the frequency dividing ratio coefficient of multi-modulus frequency divider
For 24, the now data signal output of automatic frequency alignment unit is A1A2=' 12 ', the output frequency of controlled frequency generator
For f3, the frequency is by high quality factor multiband frequency-selective network, as the input of multi-modulus frequency divider, multi-modulus frequency divider after frequency dividing
Output the input as automatic frequency alignment unit again, the now output of whole device is f3/96.
Claims (4)
1. a kind of multimode timing reference input realization device, it is characterised in that the device is by controlled frequency generator, high quality factor
This five parts structure of multiband frequency-selective network, multi-modulus frequency divider, automatic frequency alignment unit, data signal to analog signal converter
Into；The timing reference input function of multimode output frequency is realized by the setting to control bit；Multi-modulus frequency divider is selected in control bit
While divide ratio, automatic frequency alignment unit produces digital control position, and through data signal to analog signal converter it
The working condition of controlled frequency generator is controlled afterwards；High quality factor multiband frequency-selecting net is passed through in the output of controlled frequency generator
Input after network as multi-modulus frequency divider is divided, and automatic frequency alignment unit is delivered in then frequency dividing output again, through school
Clock output after standard is the final output of whole device, the timing reference input as other electronic installations.
2. multimode timing reference input realization device according to claim 1, it is characterised in that in control bit<C1,
C2...Cn>While determining multi-modulus frequency divider divide ratio, automatic frequency alignment unit also exists<C1, C2...Cn>Control
Under, set of number control bit is produced by logic control circuit<A1, A2...An>；Multi-modulus frequency divider is by single mode frequency divider and more
The cascade of mould frequency divider is realized or joined by more mould frequency divider stages and realized；Control bit<C1, C2...Cn>As multi-modulus frequency divider
Input signal, different divide ratios is realized by different combinations, the structure of sub- frequency divider, number, cascade system are by needing
Divide ratio determine；Control bit<C1, C2...Cn>Automatic frequency alignment unit input signal, these signals warp are used as simultaneously
Inversion signal corresponding to phase inverter generation is crossed, input signal passes through gate circuit logical operation with its inversion signal and exports multiple controls
Position<A1, A2 ... An>；So, in same group of control bit<C1, C2 ... Cn>Under control, while the frequency dividing of multi-modulus frequency divider is determined
Than the data signal output with automatic frequency alignment unit.
3. multimode timing reference input realization device according to claim 1, it is characterised in that controlled frequency generator it is defeated
It is by setting control bit by automatic frequency alignment unit to go out frequency<C1, C2 ... Cn>Caused control bit<A1, A2 ... An>Certainly
Fixed；Control bit<C1, C2 ... Cn>As the input signal of automatic frequency alignment unit, these signals are by phase inverter generation pair
The inversion signal answered, input signal export multiple control bits with its inversion signal by gate circuit logical operation<A1, A2 ... An>；
Control bit<A1, A2 ... An>Different Logic combine input signal as data signal to analog signal converter, determine by
Control the output frequency of frequency generator；So, in same group of control bit<C1, C2 ... Cn>Under control, while controlled frequency is determined
The data signal output of the output frequency and automatic frequency alignment unit of rate generator.
4. multimode timing reference input realization device according to claim 1, it is characterised in that high quality factor multiband selects
The Frequency Band Selection of frequency network is by setting control bit by automatic frequency alignment unit<C1, C2 ... Cn>Caused control bit<
A1, A2 ... An>Determine；Inductance, electric capacity and variable capacitance are by switched inductors in high quality factor multiband frequency-selective network
Array, switched capacitor array and switched varactor array realize that different switch combinations sets to obtain different frequency-selecting frequency ranges；
Control bit<C1, C2 ... Cn>As the input signal in automatic frequency alignment unit, can be produced not under different logic controls
Same data signal<A1, A2 ... An>；Then<A1, A2 ... An>As the input signal of three Different Logic circuits, produce respectively
Raw three groups of data signals<A11, A12 ... A1n>,<A21, A22 ... A2n>With<A31, A32 ... A3n>；Wherein<A11, A12 ... A1n
>The switch of controlling switch capacitor array,<A21, A22 ... A2n>The switch of controlling switch electric inductance array,<A31, A32 ... A3n>Control
The switch of variable capacitor array processed；So, in same group of control bit<C1, C2 ... Cn>Under control, at the same determine high-quality because
The Frequency Band Selection of plain multiband frequency-selective network and the data signal output of automatic frequency alignment unit；Now, controlled frequency occurs
The output signal of the wide-band of device output is obtaining accurately rate-adaptive pacemaker after high quality factor multiband frequency-selective network,
Input signal of the output frequency as multi-modulus frequency divider, in the presence of corresponding divide ratio, accurate division is realized, divided
Output frequency afterwards delivers to automatic frequency alignment unit again, it is calibrated after clock output for whole device final output.
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| CN112994682B (en) * | 2021-05-10 | 2021-08-03 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| CN102006095A (en) * | 2010-10-21 | 2011-04-06 | 华东师范大学 | Automatic frequency calibration channel selection filter for multi-frequency multi-mode wireless transceiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100810501B1 (en) * | 2005-12-08 | 2008-03-07 | 한국전자통신연구원 | Wide-Band Multi-Mode Frequency Composer and Variable Frequency Divider |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1196608A (en) * | 1997-04-11 | 1998-10-21 | 三星电子株式会社 | Digital processing phase lock loop for synchronous digital micro-wave apparatus |
| CN102006095A (en) * | 2010-10-21 | 2011-04-06 | 华东师范大学 | Automatic frequency calibration channel selection filter for multi-frequency multi-mode wireless transceiver |
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