CN104113332A - Clock generator based on analog delay phase-locked loop - Google Patents

Clock generator based on analog delay phase-locked loop Download PDF

Info

Publication number
CN104113332A
CN104113332A CN201410310797.5A CN201410310797A CN104113332A CN 104113332 A CN104113332 A CN 104113332A CN 201410310797 A CN201410310797 A CN 201410310797A CN 104113332 A CN104113332 A CN 104113332A
Authority
CN
China
Prior art keywords
semiconductor
oxide
metal
output
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410310797.5A
Other languages
Chinese (zh)
Other versions
CN104113332B (en
Inventor
李登全
张靓
朱樟明
杨银堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN201410310797.5A priority Critical patent/CN104113332B/en
Publication of CN104113332A publication Critical patent/CN104113332A/en
Application granted granted Critical
Publication of CN104113332B publication Critical patent/CN104113332B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Pulse Circuits (AREA)

Abstract

The invention provides a clock generator based on an analog delay phase-locked loop. The clock generator includes: a closed loop feedback system used for generating a plurality of sets of relay clock signals according to a reference clock signal; and an edge combinational circuit connected with the closed loop feedback system and used for adjusting a duty ratio of the plurality of sets of relay clock signals and outputting input clock signals of a time-interleaved successive approximation type analog-to-digital converter. The closed loop feedback system in the invention generates six sets of relay clock signals whose duty ratio is 50%, combination processing is performed on the six sets of relay clock signals whose duty ratio is 50% through the edge combination circuit, and six sets of input clock signals whose duty ratio is 20% are generated as the input clock signals of the six-channel time-interleaved successive approximation type analog-to-digital converter, thereby solving the problem that conventional input clock signal are not accurate enough.

Description

Based on the clock generator of analogue delay phase-locked loop
Technical field
The present invention relates to delay phase-locked loop field, particularly a kind of clock generator based on analogue delay phase-locked loop.
Background technology
High-speed communication system, as connected in series, ultra broadband and OFDM receiver, requires analog to digital converter to have switching rate more than GHz.At a high speed, the analog to digital converter of low middle precision is widely used in these fields.Wherein, time-interleaved gradual approaching A/D converter utilizes the mode of multichannel gradually-appoximant analog-digital converter concurrent working to improve switching rate, because adopting, subchannel analog to digital converter successively approaches structure, make power consumption and the area of whole system very little, and sample rate is very high, reaches GHz.But the input clock of existing time-interleaved structure is frequency divider clock, this frequency divider clock is accurate not, and the performance of time-interleaved structural entity is had to great impact.Therefore, the performance of existing time-interleaved gradual approaching A/D converter also has very large room for promotion.
Summary of the invention
The object of the present invention is to provide a kind of clock generator based on analogue delay phase-locked loop, solved the accurate not problem of traditional frequency divider clock.
In order to address the above problem, the embodiment of the present invention provides a kind of clock generator based on analogue delay phase-locked loop, comprising:
For according to reference clock signal, produce the closed loop feedback system of many group delay clock signals;
Be connected with described closed loop feedback system, for the duty ratio of described many group delay clock signals is adjusted, and export the edge combinational circuit of the input clock signal of described time-interleaved gradual approaching A/D converter.
Further, described closed loop feedback system produces the delay clock signals that six groups of duty ratios are 50%, and wherein, the phase place equal proportion of described six groups of delay clock signals increases.
Further, described six groups of delay clock signals are carried out combination of two processing by described edge combinational circuit, exports six groups of input clock signals that duty ratio is 20%, and wherein, the phase difference that carries out two groups of delay clock signals of combined treatment is preset value.
Wherein, described closed loop feedback system comprises: phase discriminator, the charge pump being connected with described phase discriminator, the loop filter being connected with described charge pump, the respectively voltage controlled delay line that is connected with described loop filter and described charge pump and the output latch circuit being connected with described voltage controlled delay line;
Wherein, the first delay clock signals ck1 that described phase discriminator feeds back for detection of described output latch circuit and the phase difference of the 7th delay clock signals ck7, and export a testing result;
Described charge pump is for being converted to electric current by described testing result;
Described loop filter is for by described current conversion being control voltage Vc;
Described voltage controlled delay line is for producing according to described control voltage Vc and described reference clock signal the delay clock signals that seven groups of duty ratios are 50%, wherein, described seven groups of delay clock signals comprise the first delay clock signals ck1, the second delay clock signals ck2, the 3rd delay clock signals ck3, the 4th delay clock signals ck4, the 5th delay clock signals ck5, the 6th delay clock signals ck6 and the 7th delay clock signals ck7 that phase place equal proportion increases;
Described output latch circuit is for seven groups of delay clock signals described in latch, and the first delay clock signals ck1, the second delay clock signals ck2, the 3rd delay clock signals ck3, the 4th delay clock signals ck4, the 5th delay clock signals ck5 and the 6th delay clock signals ck6 are exported to described edge combinational circuit, described the first delay clock signals ck1 and the 7th delay clock signals ck7 are fed back to described phase discriminator simultaneously.
Wherein, described phase discriminator comprises:
The first inverter I1, the first rising edge flip-over type d type flip flop FF1, the second rising edge flip-over type d type flip flop FF2, the 3rd rising edge flip-over type d type flip flop FF3, the first NAND gate N1, the second NAND gate N2;
Wherein, input termination the first input signal start of described the first inverter I1, the output of described the first inverter I1 is connected with the reset terminal Rst of described the first rising edge flip-over type d type flip flop FF1; The data input pin D of described the first rising edge flip-over type d type flip flop FF1 meets power vd D, the output Q of described the first rising edge flip-over type d type flip flop FF1 exports the first output signal rdy, and be connected with the data input pin D of the 3rd rising edge flip-over type d type flip flop FF3, the input end of clock clk of described the first rising edge flip-over type d type flip flop FF1 is connected with the first delay clock signals ck1; The input end of clock clk of described the second rising edge flip-over type d type flip flop FF2 is connected with the 7th delay clock signals ck7, the data input pin D of described the second rising edge flip-over type d type flip flop FF2 is connected with power vd D, output Q output the 3rd output signal DN of described the second rising edge flip-over type d type flip flop FF2; The input end of clock clk of described the 3rd rising edge flip-over type d type flip flop FF3 meets the first delay clock signals ck1, and the output Q of described the 3rd rising edge flip-over type d type flip flop FF3 exports the second output signals UP; Two inputs of described the first NAND gate N1 meet respectively described the second output signals UP and described the 3rd output signal DN, and the output of described the first NAND gate N1 is connected with the first input end of described the second NAND gate N2; The first input signal start described in the second input termination of described the second NAND gate N2, the output of described the second NAND gate N2 is connected with the reset terminal Rst of the 3rd rising edge flip-over type d type flip flop FF3 and the reset terminal Rst of the second rising edge flip-over type d type flip flop FF2 respectively.
Wherein, described charge pump comprises: input signal Circuit tuning, and described input signal Circuit tuning comprises: the anti-phase Circuit tuning of the second output signals UP and the 3rd output signal DN delay regulating circuit;
Wherein, the anti-phase Circuit tuning of described the second output signals UP comprises:
The second inverter I2, the 3rd inverter I3, the 4th inverter I4, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2;
Wherein, the second output signals UP described in the input termination of described the second inverter I2, the output of described the second inverter I2 is connected with the drain electrode of described the first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2 respectively; The grid of described the first metal-oxide-semiconductor M1 meets power vd D, and the source electrode of described the first metal-oxide-semiconductor M1 is connected with the drain electrode of described the second metal-oxide-semiconductor M2, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with the source electrode of the second metal-oxide-semiconductor M2; The grounded-grid of the second metal-oxide-semiconductor M2; The input of described the 3rd inverter I3 is connected with the drain electrode of described the second metal-oxide-semiconductor M2 with the source electrode of described the first metal-oxide-semiconductor M1 respectively, and the output of described the 3rd inverter I3 is connected with the input of described the 4th inverter I4; The output signal of described the 4th inverter I4 is the delay inversion signal UPb of described the second output signals UP.
Described the 3rd output signal DN delay regulating circuit comprises:
The 5th inverter I5, hex inverter I6, the 7th inverter I7, the 8th inverter I8;
Wherein, the 3rd output signal DN described in the input termination of described the 5th inverter I5, the output of described the 5th inverter I5 is connected with the input of described hex inverter I6; The output of described hex inverter I6 is connected with the input of described the 7th inverter I7; The output of described the 7th inverter I7 is connected with the input of described the 8th inverter I8; The output of described the 8th inverter I8 is exported the inhibit signal DN_delay of described the 3rd output signal DN;
Wherein, described charge pump also comprises: charge pump main body circuit, and described charge pump main body circuit comprises: electric current source generating circuit and current mirror charge-discharge circuit;
Wherein, described electric current source generating circuit comprises:
The 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the first resistance R 1;
Wherein, the source electrode of described the 3rd metal-oxide-semiconductor M3 is connected with power vd D, the grid of described the 3rd metal-oxide-semiconductor M3 is connected with grid and the drain electrode of described the 5th metal-oxide-semiconductor M5 respectively, the grid of described the 3rd metal-oxide-semiconductor M3 is also connected with grid and the drain electrode of described the 4th metal-oxide-semiconductor M4 respectively, and the drain electrode of described the 3rd metal-oxide-semiconductor M3 is connected with drain electrode and the grid of described the 6th metal-oxide-semiconductor M6 respectively; The source ground GND of described the 6th metal-oxide-semiconductor M6, the drain and gate of described the 6th metal-oxide-semiconductor M6 is connected with the source electrode of described the 5th metal-oxide-semiconductor M5 after connecting, and the drain and gate of described the 6th metal-oxide-semiconductor M6 is also connected with the grid of described the 7th metal-oxide-semiconductor M7 after connecting; The grid of described the 4th metal-oxide-semiconductor M4 is connected with the drain electrode of described the 7th metal-oxide-semiconductor M7 after being connected with drain electrode, and the grid of described the 4th metal-oxide-semiconductor M4 is also connected with the grid of described the 8th metal-oxide-semiconductor M8 after being connected with drain electrode, and the source electrode of described the 4th metal-oxide-semiconductor M4 meets power vd D; The source electrode of described the 8th metal-oxide-semiconductor M8 meets power vd D, and the drain electrode of described the 8th metal-oxide-semiconductor M8 is connected with described current mirror charge-discharge circuit; One end of described the first resistance R 1 is connected with the source electrode of described the 7th metal-oxide-semiconductor M7, other end ground connection GND;
Described current mirror charge-discharge circuit comprises:
The 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11, the 12 metal-oxide-semiconductor M12, the 13 metal-oxide-semiconductor M13, the 14 metal-oxide-semiconductor M14, the 15 metal-oxide-semiconductor M15, the 16 metal-oxide-semiconductor M16, the 17 metal-oxide-semiconductor M17, the first switching tube M18, the 19 metal-oxide-semiconductor M19, the 20 metal-oxide-semiconductor M20, second switch pipe M21, the 22 metal-oxide-semiconductor M22, the 23 metal-oxide-semiconductor M23, the 24 metal-oxide-semiconductor M24;
Wherein, the source ground GND of described the 9th metal-oxide-semiconductor M9, the grid of described the 9th metal-oxide-semiconductor M9 is connected with the drain electrode of described the 8th metal-oxide-semiconductor M8, described the tenth grid of metal-oxide-semiconductor M10 and the grid of described the 13 metal-oxide-semiconductor M13 respectively after being connected with drain electrode; The source ground GND of described the tenth metal-oxide-semiconductor M10, the drain electrode of described the tenth metal-oxide-semiconductor M10 is connected with the drain and gate of described the 11 metal-oxide-semiconductor M11 respectively; The source electrode of described the 11 metal-oxide-semiconductor M11 meets power vd D, and the drain and gate of described the 11 metal-oxide-semiconductor M11 is connected with the grid of described the 12 metal-oxide-semiconductor M12 after connecting; The source electrode of described the 12 metal-oxide-semiconductor M12 meets power vd D, and described the 12 metal-oxide-semiconductor M12 drain electrode is connected with drain electrode and the grid of described the 16 metal-oxide-semiconductor M16 respectively; The drain electrode of described the 16 metal-oxide-semiconductor M16 is connected with described the 23 drain electrode of metal-oxide-semiconductor M23 and the grid of described the 20 metal-oxide-semiconductor M20 respectively after being connected with grid, and the source electrode of described the 16 metal-oxide-semiconductor M16 is connected with the drain electrode of described the 17 metal-oxide-semiconductor M17; The grid of described the 17 metal-oxide-semiconductor M17 meets power vd D, the source ground GND of described the 17 metal-oxide-semiconductor M17; The source electrode of described the 23 metal-oxide-semiconductor M23 meets power vd D, the grid of described the 23 metal-oxide-semiconductor M23 is connected with the drain electrode of described the 20 metal-oxide-semiconductor M20, and the grid of described the 23 metal-oxide-semiconductor M23 is also connected with grid, the 24 drain electrode of metal-oxide-semiconductor M24 and the drain electrode of the 19 metal-oxide-semiconductor M19 of described the 22 metal-oxide-semiconductor M22 respectively; The drain electrode of described the 24 metal-oxide-semiconductor M24 connects controls voltage Vc, and the grid of described the 24 metal-oxide-semiconductor M24 meets the first output signal rdy, and the source electrode of described the 24 metal-oxide-semiconductor M24 meets power vd D; The source electrode of described the 19 metal-oxide-semiconductor M19 is connected with the drain electrode of described the first switching tube M18, the grid of described the 19 metal-oxide-semiconductor M19 is connected with the drain electrode of described the 22 metal-oxide-semiconductor M22, and the grid of described the 19 metal-oxide-semiconductor M19 is also connected with grid and the drain electrode of described the 15 metal-oxide-semiconductor M15 respectively; After the grid of described the 15 metal-oxide-semiconductor M15 and drain electrode connect, be connected with the drain electrode of described the 13 metal-oxide-semiconductor M13, the source electrode of described the 15 metal-oxide-semiconductor M15 is connected with the drain electrode of described the 14 metal-oxide-semiconductor M14; The source ground GND of described the 13 metal-oxide-semiconductor M13; The source electrode of described the 14 metal-oxide-semiconductor M14 meets power vd D, the grounded-grid GND of described the 14 metal-oxide-semiconductor M14; The source electrode of described the first switching tube M18 meets power vd D, and the grid of described the first switching tube M18 meets the delay inversion signal UPb of described the second output signals UP; The source electrode of described the 20 metal-oxide-semiconductor M20 is connected with the drain electrode of described second switch pipe M21; The source ground GND of described second switch pipe M21, the grid of described second switch pipe M21 meets the inhibit signal DN_delay of described the 3rd output signal DN; The source ground GND of described the 22 metal-oxide-semiconductor M22.
Wherein, described loop filter is specially capacitor C l, described capacitor C lone end be connected with described charge pump and described voltage controlled delay line respectively, and voltage Vc, described capacitor C are controlled in output lother end ground connection GND.
Wherein, described voltage controlled delay line comprises the differential voltage-controlled delay cell of the first order, the differential voltage-controlled delay cell in the second level, the differential voltage-controlled delay cell of the third level, the differential voltage-controlled delay cell of the fourth stage and the differential voltage-controlled delay cell of level V with same structure, wherein
The first input end of the differential voltage-controlled delay cell of the described first order is connected with the first reference clock signal CLK_P, the second input of the differential voltage-controlled delay cell of the described first order is connected with the second reference clock signal CLK_N, the first output of the differential voltage-controlled delay cell of the described first order is connected with the first input end of the differential voltage-controlled delay cell in the described second level, and the second output of the differential voltage-controlled delay cell of the described first order is connected with the second input of the differential voltage-controlled delay cell in the described second level;
The first output of the differential voltage-controlled delay cell in the described second level is connected with the first input end of the differential voltage-controlled delay cell of the described third level, and the second output of the differential voltage-controlled delay cell in the described second level is connected with the second input of the differential voltage-controlled delay cell of the described third level;
The first output of the differential voltage-controlled delay cell of the described third level is connected with the first input end of the differential voltage-controlled delay cell of the described fourth stage, and the second output of the differential voltage-controlled delay cell of the described third level is connected with the second input of the differential voltage-controlled delay cell of the described fourth stage;
The first output of the differential voltage-controlled delay cell of the described fourth stage is connected with the first input end of the differential voltage-controlled delay cell of described level V, and the second output of the differential voltage-controlled delay cell of the described fourth stage is connected with the second input of the differential voltage-controlled delay cell of described level V;
Wherein, every grade of described differential voltage-controlled delay cell comprises:
Voltage control tail current source M25, the first input metal-oxide-semiconductor M26, the second input metal-oxide-semiconductor M27, the first load metal-oxide-semiconductor M28, the second load metal-oxide-semiconductor M29, the 3rd load metal-oxide-semiconductor M30, the 4th load metal-oxide-semiconductor M31, the 9th inverter I9, the tenth inverter I10;
Wherein, the source ground GND of described voltage control tail current source M25, the grid of described voltage control tail current source M25 connects controls voltage Vc, and the drain electrode of described voltage control tail current source M25 is connected with the source electrode of described the first input metal-oxide-semiconductor M26 and the source electrode of described the second input metal-oxide-semiconductor M27 respectively; Described the first input metal-oxide-semiconductor M26 the grid first output OUT1 that is described differential voltage-controlled delay cell, the drain electrode of described the first input metal-oxide-semiconductor M26 is connected with the input of described the 9th inverter I9; The output of described the 9th inverter I9 is the first input end Vin1 of described differential voltage-controlled delay cell, describedly be connected with the drain electrode of described the first load metal-oxide-semiconductor M28 and the grid of described the 3rd load metal-oxide-semiconductor M30, drain electrode respectively, the output of described the 9th inverter I9 is also connected with the grid of described the second load metal-oxide-semiconductor M29; The source electrode of described the 3rd load metal-oxide-semiconductor M30 meets power vd D; The source electrode of described the first load metal-oxide-semiconductor M28 meets power vd D, the grid of described the first load metal-oxide-semiconductor M28 is connected with the drain electrode of the second load metal-oxide-semiconductor M29 and drain electrode, the grid of the 4th load metal-oxide-semiconductor M31 respectively, and the grid of described the first load metal-oxide-semiconductor M28 is also connected with the input of described the tenth inverter I10 and the drain electrode of described the second input metal-oxide-semiconductor M27 respectively; The source electrode of the second load metal-oxide-semiconductor M29 meets power vd D; The source electrode of described the 4th load metal-oxide-semiconductor M31 meets power vd D; The output of described the tenth inverter I10 is the second input Vin2 of described differential voltage-controlled delay cell; The second output OUT2 that the grid of described the second input metal-oxide-semiconductor M27 is described differential voltage-controlled delay cell.
Wherein, described output latch circuit comprises the first output latch, the second output latch, the 3rd output latch and the 4th output latch with same structure; The first input end of described the first output latch is connected with the first output of the differential voltage-controlled delay cell of the described first order, the second input of described the first output latch is connected with the second output of the differential voltage-controlled delay cell of the described first order, the first output of described the first output latch is exported described the first delay clock signals ck1, and the second output of described the first output latch is exported described the first delay clock signals ck4;
The first input end of described the second output latch is connected with the first output of the differential voltage-controlled delay cell in the described second level, the second input of described the second output latch is connected with the second output of the differential voltage-controlled delay cell in the described second level, the first output of described the second output latch is exported described the second delay clock signals ck2, and the second output of described the second output latch is exported described the 5th delay clock signals ck5;
The first input end of described the 3rd output latch is connected with the first output of the differential voltage-controlled delay cell of the described third level, the second input of described the 3rd output latch is connected with the second output of the differential voltage-controlled delay cell of the described third level, the first output of described the 3rd output latch is exported described the 3rd delay clock signals ck3, and the second output of described the 3rd output latch is exported described the 6th delay clock signals ck6;
The first input end of described the 4th output latch is connected with the first output of the differential voltage-controlled delay cell of the described fourth stage, the second input of described the 4th output latch is connected with the second output of the differential voltage-controlled delay cell of the described fourth stage, and the first output of described the 4th output latch is exported described the 7th delay clock signals ck7;
Wherein each described output latch comprises:
The 11 inverter I11, the 12 inverter I12, the 13 inverter I13, the 14 inverter I14, the 15 inverter I15 and the tenth hex inverter I16;
Wherein, the first input end IN1 that the input of described the 11 inverter I11 is described output latch, the input of the 12 inverter I12 described in the output termination of described the 11 inverter I11; The output of the 12 inverter I12 is connected with the output of described the 15 inverter I15 and the input of described the tenth hex inverter I16 respectively, and the output of the 12 inverter I12 is as the first output OUT3 of described output latch; The input of described the 15 inverter I15 is connected with the output of described the 14 inverter I14 and the output of described the tenth hex inverter I16 respectively, and the output of described the 14 inverter I14 is as described output latch the second output OUT4; The input of described the 14 inverter I14 is connected with the output of described the 13 inverter I13; The input of described the 13 inverter I13 is as the second input IN2 of described output latch.
Wherein, described edge combinational circuit comprises six dutyfactor adjustment circuits with same structure;
Wherein, the first input end of the first Circuit tuning in described six dutyfactor adjustment circuits meets described the first delay clock signals ck1, the 5th delay clock signals ck5 described in the second input termination of described the first Circuit tuning, the output of described the first Circuit tuning is exported the first input clock signal A1;
The first input end of the second Circuit tuning in described six dutyfactor adjustment circuits meets described the second delay clock signals ck2, the 6th delay clock signals ck6 described in the second input termination of described the second Circuit tuning, the output of described the second Circuit tuning is exported the second input clock signal A2;
The first input end of the 3rd Circuit tuning in described six dutyfactor adjustment circuits meets described the 3rd delay clock signals ck3, the first delay clock signals ck1 described in the second input termination of described the 3rd Circuit tuning, output output the 3rd input clock signal A3 of described the 3rd Circuit tuning;
The first input end of the 4th Circuit tuning in described six dutyfactor adjustment circuits meets described the 4th delay clock signals ck4, the second delay clock signals ck2 described in the second input termination of described the 3rd Circuit tuning, output output the 4th input clock signal A4 of described the 4th Circuit tuning;
The first input end of the 5th Circuit tuning in described six dutyfactor adjustment circuits meets described the 5th delay clock signals ck5, the 3rd delay clock signals ck3 described in the second input termination of described the 3rd Circuit tuning, output output the 5th input clock signal A5 of described the 5th Circuit tuning;
The first input end of the 6th Circuit tuning in described six dutyfactor adjustment circuits meets described the 5th delay clock signals ck6, the 3rd delay clock signals ck4 described in the second input termination of described the 3rd Circuit tuning, output output the 6th input clock signal A6 of described the 6th Circuit tuning;
Wherein, each described dutyfactor adjustment circuit comprises:
The 17 inverter I17, eighteen incompatibilities phase device I18, the 19 inverter I19, the 20 inverter I20, the 21 inverter I21, the 22 inverter I22, the 23 inverter I23, the 32 metal-oxide-semiconductor M32, the 33 metal-oxide-semiconductor M33, the 34 metal-oxide-semiconductor M34, the 35 metal-oxide-semiconductor M35;
Wherein, the first input end fall that described the 17 input of inverter I17 and the grid of the 33 metal-oxide-semiconductor M33 are described dutyfactor adjustment circuit; The output of described the 17 inverter I17 is connected with the input of described eighteen incompatibilities phase device I18, and the output of described eighteen incompatibilities phase device I18 is connected with the input of described the 19 inverter I19; The output of described the 19 inverter I19 is connected with the grid of described the 32 metal-oxide-semiconductor M32; The source electrode of described the 32 metal-oxide-semiconductor M32 meets power vd D, and the drain electrode of described the 32 metal-oxide-semiconductor M32 is connected with described the 33 metal-oxide-semiconductor M33 source electrode; The drain electrode of described the 33 metal-oxide-semiconductor M33 is connected with described the 23 input of inverter I23 and the drain electrode of described the 34 metal-oxide-semiconductor M34 respectively; The output of described the 23 inverter I23 is the output OUT of described dutyfactor adjustment circuit; The second input rise that described the 20 input of inverter I20 and the grid of described the 35 metal-oxide-semiconductor M35 are described dutyfactor adjustment circuit; The output of described the 20 inverter I20 is connected with the input of described the 21 inverter I21; The output of described the 21 inverter I21 is connected with the input of described the 22 inverter I22; The output of described the 22 inverter I22 is connected with the grid of described the 34 metal-oxide-semiconductor M34; The source electrode of described the 34 metal-oxide-semiconductor M34 is connected with the drain electrode of described the 35 metal-oxide-semiconductor M35, the source ground GND of described the 35 metal-oxide-semiconductor M35.
Technique scheme of the present invention at least has following beneficial effect:
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, phase discriminator with initial control and voltage controlled delay line form the reponse system of a closed loop, can produce six groups of duty ratios 50%, the delay clock signals that phase place equal proportion increases, through edge combinational circuit, six groups of delay clock signals are recombinated again, can produce six groups of duty ratios is 20%, the input clock signal that phase place equal proportion increases, and the clock signal of the gradual approaching A/D converter that interweaves these six groups of input clock signals as six channel clocks, make the interweave input clock signal of gradual approaching A/D converter of six channel clocks more accurate, further improve the interweave overall performance of gradual approaching A/D converter of six channel clocks.
Brief description of the drawings
Fig. 1 is the structured flowchart of the clock generator based on analogue delay phase-locked loop of the embodiment of the present invention;
Fig. 2 is the physical circuit figure of the clock generator based on analogue delay phase-locked loop of the embodiment of the present invention;
Fig. 3 is the physical circuit figure of the phase discriminator of the embodiment of the present invention;
Fig. 4 is the sequential schematic diagram of the phase discriminator of the embodiment of the present invention;
Fig. 5 is the anti-phase Circuit tuning figure of the second output signals UP of the embodiment of the present invention;
Fig. 6 is the delay regulating circuit figure of the 3rd output signal DN of the embodiment of the present invention;
Fig. 7 is the main body circuit diagram of charge pump in the embodiment of the present invention;
Fig. 8 is the physical circuit figure of the voltage-controlled delay unit of the embodiment of the present invention;
Fig. 9 is the physical circuit figure of the output latch circuit of the embodiment of the present invention;
Figure 10 is the physical circuit figure of the dutyfactor adjustment circuit of the embodiment of the present invention;
Figure 11 is the sequential schematic diagram of the output clock of the clock generator based on analogue delay phase-locked loop of the embodiment of the present invention.
Description of reference numerals:
1-closed loop feedback system, 10 – phase discriminators, 11-charge pump, 12-loop filter, 13-voltage controlled delay line, the differential voltage-controlled delay cell of the 131-first order, the differential voltage-controlled delay cell in the 132-second level, the differential voltage-controlled delay cell of the 133-third level, the differential voltage-controlled delay cell of the 134-fourth stage, the differential voltage-controlled delay cell of 135-level V, 14-output latch circuit, 141-the first output latch, 142-the second output latch, 143-the 3rd output latch, 144-the 4th output latch, 2-edge combinational circuit.
Embodiment
For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
The present invention is directed to the interweave accurate not problem of input clock of gradual approaching A/D converter of six channel times in prior art, a kind of clock generator based on analogue delay phase-locked loop is provided, as shown in Figure 1, clock generator based on analogue delay phase-locked loop comprises: for according to reference clock signal, produce the closed loop feedback system 1 of many group delay clock signals, wherein, described reference clock signal comprises: the first reference clock signal CLK_P and the second reference clock signal CLK_N;
Be connected with described closed loop feedback system 1, for the duty ratio of described many group delay clock signals is adjusted, and export the edge combinational circuit 2 of the input clock signal of described time-interleaved gradual approaching A/D converter.
In the above embodiment of the present invention, six groups of delay clock signals that duty ratio is 50% of closed loop feedback system 1 concrete generation, wherein, the phase place equal proportion of described six groups of delay clock signals increases; Described six groups of delay clock signals are carried out combination of two processing by described edge combinational circuit 2, export the input clock signal that six groups of duty ratios are 20%, and set it as the interweave input clock signal of gradual approaching A/D converter of six channel clocks, make the interweave input clock signal of gradual approaching A/D converter of six channel clocks more accurate, thereby further improved the interweave overall performance of gradual approaching A/D converter of six channel clocks.
In the above embodiment of the present invention, as shown in Figure 1, described closed loop feedback system 1 comprises: phase discriminator 10, the charge pump 11 being connected with described phase discriminator 10, the loop filter 12 being connected with described charge pump 11, the respectively voltage controlled delay line 13 that is connected with described loop filter 12 and described charge pump 11 and the output latch circuit 14 being connected with described voltage controlled delay line 13;
Wherein, the first delay clock signals ck1 that described phase discriminator 10 feeds back for detection of described output latch circuit 14 and the phase difference of the 7th delay clock signals ck7, and export a testing result;
Described charge pump 11 is for being converted to electric current by described testing result;
Described loop filter 12 is for by described current conversion being control voltage Vc;
Further, as shown in Figure 2, described loop filter is specially capacitor C l, described capacitor C lone end be connected with described charge pump and described voltage controlled delay line respectively, and voltage Vc, described capacitor C are controlled in output lother end ground connection GND.
Described voltage controlled delay line 13 is for producing according to described control voltage Vc and described reference clock signal the delay clock signals that seven groups of duty ratios are 50%, wherein, described seven groups of delay clock signals comprise the first delay clock signals ck1, the second delay clock signals ck2, the 3rd delay clock signals ck3, the 4th delay clock signals ck4, the 5th delay clock signals ck5, the 6th delay clock signals ck6 and the 7th delay clock signals ck7 that phase place equal proportion increases;
The voltage controlled delay line 13 of the embodiment of the present invention, according to the difference of controlling voltage Vc value, produces than multiple delay clock signals of delayed reference clock signal different time.Wherein, the reference clock signal cycle is that T and duty ratio are 50%, voltage controlled delay line is exported the delay clock signals that seven groups of duty ratios are 50%, phase place equal proportion increases, when the time delay of last group delay clock signals is during than first group of late clock cycle T of delay clock signals, loop-locking, now, controlling voltage Vc remains unchanged.
Described output latch circuit 14 is for seven groups of delay clock signals described in latch, and the first delay clock signals ck1, the second delay clock signals ck2, the 3rd delay clock signals ck3, the 4th delay clock signals ck4, the 5th delay clock signals ck5 and the 6th delay clock signals ck6 are exported to described edge combinational circuit, described the first delay clock signals ck1 and the 7th delay clock signals ck7 are fed back to described phase discriminator 10 simultaneously.
In specific embodiments of the invention, output latch circuit 14, by by the output signal latch output of voltage controlled delay line, can improve the reversal rate of each output clock and make the not good two phase clock of anti-phase performance originally become strict anti-phase two phase clock.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 3, described phase discriminator 10 comprises:
The first inverter I1, the first rising edge flip-over type d type flip flop FF1, the second rising edge flip-over type d type flip flop FF2, the 3rd rising edge flip-over type d type flip flop FF3, the first NAND gate N1, the second NAND gate N2;
Wherein, input termination the first input signal start of described the first inverter I1, the output of described the first inverter I1 is connected with the reset terminal Rst of described the first rising edge flip-over type d type flip flop FF1; The data input pin D of described the first rising edge flip-over type d type flip flop FF1 meets power vd D, the output Q of described the first rising edge flip-over type d type flip flop FF1 exports the first output signal rdy, and be connected with the data input pin D of the 3rd rising edge flip-over type d type flip flop FF3, the input end of clock clk of described the first rising edge flip-over type d type flip flop FF1 is connected with the first delay clock signals ck1; The input end of clock clk of described the second rising edge flip-over type d type flip flop FF2 is connected with the 7th delay clock signals ck7, the data input pin D of described the second rising edge flip-over type d type flip flop FF2 is connected with power vd D, output Q output the 3rd output signal DN of described the second rising edge flip-over type d type flip flop FF2; The input end of clock clk of described the 3rd rising edge flip-over type d type flip flop FF3 meets the first delay clock signals ck1, and the output Q of described the 3rd rising edge flip-over type d type flip flop FF3 exports the second output signals UP; Two inputs of described the first NAND gate N1 meet respectively described the second output signals UP and described the 3rd output signal DN, and the output of described the first NAND gate N1 is connected with the first input end of described the second NAND gate N2; The first input signal start described in the second input termination of described the second NAND gate N2, the output of described the second NAND gate N2 is connected with the reset terminal Rst of the 3rd rising edge flip-over type d type flip flop FF3 and the reset terminal Rst of the second rising edge flip-over type d type flip flop FF2 respectively.
In specific embodiments of the invention, as shown in Fig. 2 and Fig. 3 and Fig. 4, phase discriminator 10 courses of work with initial control are as follows: when system powers on, the first input signal start signal is " 0 ", the first output signal rdy, the second output signals UP and the 3rd output signal DN of phase discriminator 10 are " 0 ", wherein, the reset signal that the first output signal rdy is charge pump.Now, the control voltage Vc that charge pump 11 is exported is high level VDD, and the initialization of voltage-controlled delay unit, and its delay value is minimum.The first input signal start signal becomes " 1 " subsequently, the arrival along with first rising edge of the first delay clock signals ck1 under the effect of the first rising edge flip-over type d type flip flop FF1 of the first output signal rdy signal becomes " 1 ", and the second output signals UP and the 3rd output signal DN are still " 0 ".The rising edge of the 7th delay clock signals ck7 arrives afterwards, and because the data input pin D of the second rising edge flip-over type d type flip flop FF2 is connected on high level VDD above, therefore, the 3rd output signal DN becomes " 1 ", and now the second output signal U is still " 0 ".Second of the first delay clock signals ck1 rising edge arrives afterwards, the second output signals UP is set to " 1 ", now the 3rd output signal DN is still " 1 ", under the acting in conjunction of the first NAND gate N1, the second NAND gate N2, the second rising edge flip-over type d type flip flop FF2, the 3rd rising edge flip-over type d type flip flop FF3 are reset, therefore, the second output signals UP and the 3rd output signal DN become " 0 " simultaneously.Now, a phase demodulation end cycle, under the effect of the 3rd output signal DN signal, control voltage Vc and constantly reduce the amount of delay to increase voltage control delay unit, and gradually eliminate output delay clock signals and reference clock between phase error, to the last one group of delay clock signals is than a clock cycle of delayed reference clock, and delay phase-locked loop DLL realizes locking.
The sequential chart of the phase discriminator with initial control as shown in Figure 4, because can making the second output signals UP and the 3rd output signal DN after system powers on, the described phase discriminator with initial control is " 0 ", now, can make the voltage controlled delay line initialization of rear class, i.e. length of delay minimum.Make subsequently the 3rd output signal DN for " 1 " second output signals UP is for " 0 ", rear class voltage controlled delay line increases length of delay, and constantly reduce the phase difference of the first delay clock signals ck1 and the 7th delay clock signals ck7, until loop-locking, the 7th delay clock signals ck7 postpones a clock cycle than the first delay clock signals ck1.Therefore, the phase discriminator with initial control can be avoided the mistake locking of loop.
The phase discriminator of the embodiment of the present invention based on initial control, delay phase-locked loop can effectively be avoided harmonic wave locking, and this delay phase-locked loop can reach lock-out state in the short period of time.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 5 and Figure 6, described charge pump 11 comprises: input signal Circuit tuning, and described input signal Circuit tuning comprises: the anti-phase Circuit tuning of the second output signals UP and the 3rd output signal DN delay regulating circuit;
Wherein, as shown in Figure 5, the anti-phase Circuit tuning of described the second output signals UP comprises:
The second inverter I2, the 3rd inverter I3, the 4th inverter I4, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2;
Wherein, the second output signals UP described in the input termination of described the second inverter I2, the output of described the second inverter I2 is connected with the drain electrode of described the first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2 respectively; The grid of described the first metal-oxide-semiconductor M1 meets power vd D, and the source electrode of described the first metal-oxide-semiconductor M1 is connected with the drain electrode of described the second metal-oxide-semiconductor M2, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with the source electrode of the second metal-oxide-semiconductor M2; The grounded-grid of the second metal-oxide-semiconductor M2; The input of described the 3rd inverter I3 is connected with the drain electrode of described the second metal-oxide-semiconductor M2 with the source electrode of described the first metal-oxide-semiconductor M1 respectively, and the output of described the 3rd inverter I3 is connected with the input of described the 4th inverter I4; The output signal of described the 4th inverter I4 is the delay inversion signal UPb of described the second output signals UP.
In specific embodiments of the invention, due to connect the signal of the first switching tube M18 grid be the second output signals UP through phase discriminator anti-phase come, therefore can make this signal open time of switching tube M18 and the 3rd output signal DN signal to open the asynchronism(-nization) step of second switch pipe M21, the input clock that is control switch pipe can be offset, and causes the asynchronous of charging and discharging currents.By the input signal Circuit tuning in the embodiment of the present invention, make charge pump input signal arrive time of switching tube separately identical, avoid the asynchronous of charging and discharging currents.
As shown in Figure 6, described the 3rd output signal DN delay regulating circuit comprises:
The 5th inverter I5, hex inverter I6, the 7th inverter I7, the 8th inverter I8;
Wherein, the 3rd output signal DN described in the input termination of described the 5th inverter I5, the output of described the 5th inverter I5 is connected with the input of described hex inverter I6; The output of described hex inverter I6 is connected with the input of described the 7th inverter I7; The output of described the 7th inverter I7 is connected with the input of described the 8th inverter I8; The output of described the 8th inverter I8 is exported the inhibit signal DN_delay of described the 3rd output signal DN;
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 7, described charge pump 11 also comprises: charge pump main body circuit, described charge pump main body circuit comprises: electric current source generating circuit and current mirror charge-discharge circuit;
Wherein, described electric current source generating circuit comprises:
The 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the first resistance R 1;
Wherein, the source electrode of described the 3rd metal-oxide-semiconductor M3 is connected with power vd D, the grid of described the 3rd metal-oxide-semiconductor M3 is connected with grid and the drain electrode of described the 5th metal-oxide-semiconductor M5 respectively, the grid of described the 3rd metal-oxide-semiconductor M3 is also connected with grid and the drain electrode of described the 4th metal-oxide-semiconductor M4 respectively, and the drain electrode of described the 3rd metal-oxide-semiconductor M3 is connected with drain electrode and the grid of described the 6th metal-oxide-semiconductor M6 respectively; The source ground GND of described the 6th metal-oxide-semiconductor M6, the drain and gate of described the 6th metal-oxide-semiconductor M6 is connected with the source electrode of described the 5th metal-oxide-semiconductor M5 after connecting, and the drain and gate of described the 6th metal-oxide-semiconductor M6 is also connected with the grid of described the 7th metal-oxide-semiconductor M7 after connecting; The grid of described the 4th metal-oxide-semiconductor M4 is connected with the drain electrode of described the 7th metal-oxide-semiconductor M7 after being connected with drain electrode, and the grid of described the 4th metal-oxide-semiconductor M4 is also connected with the grid of described the 8th metal-oxide-semiconductor M8 after being connected with drain electrode, and the source electrode of described the 4th metal-oxide-semiconductor M4 meets power vd D; The source electrode of described the 8th metal-oxide-semiconductor M8 meets power vd D, and the drain electrode of described the 8th metal-oxide-semiconductor M8 is connected with described current mirror charge-discharge circuit; One end of described the first resistance R 1 is connected with the source electrode of described the 7th metal-oxide-semiconductor M7, other end ground connection GND;
Described current mirror charge-discharge circuit comprises:
The 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11, the 12 metal-oxide-semiconductor M12, the 13 metal-oxide-semiconductor M13, the 14 metal-oxide-semiconductor M14, the 15 metal-oxide-semiconductor M15, the 16 metal-oxide-semiconductor M16, the 17 metal-oxide-semiconductor M17, the first switching tube M18, the 19 metal-oxide-semiconductor M19, the 20 metal-oxide-semiconductor M20, second switch pipe M21, the 22 metal-oxide-semiconductor M22, the 23 metal-oxide-semiconductor M23, the 24 metal-oxide-semiconductor M24;
Wherein, the source ground GND of described the 9th metal-oxide-semiconductor M9, the grid of described the 9th metal-oxide-semiconductor M9 is connected with the drain electrode of described the 8th metal-oxide-semiconductor M8, described the tenth grid of metal-oxide-semiconductor M10 and the grid of described the 13 metal-oxide-semiconductor M13 respectively after being connected with drain electrode; The source ground GND of described the tenth metal-oxide-semiconductor M10, the drain electrode of described the tenth metal-oxide-semiconductor M10 is connected with the drain and gate of described the 11 metal-oxide-semiconductor M11 respectively; The source electrode of described the 11 metal-oxide-semiconductor M11 meets power vd D, and the drain and gate of described the 11 metal-oxide-semiconductor M11 is connected with the grid of described the 12 metal-oxide-semiconductor M12 after connecting; The source electrode of described the 12 metal-oxide-semiconductor M12 meets power vd D, and described the 12 metal-oxide-semiconductor M12 drain electrode is connected with drain electrode and the grid of described the 16 metal-oxide-semiconductor M16 respectively; The drain electrode of described the 16 metal-oxide-semiconductor M16 is connected with described the 23 drain electrode of metal-oxide-semiconductor M23 and the grid of described the 20 metal-oxide-semiconductor M20 respectively after being connected with grid, and the source electrode of described the 16 metal-oxide-semiconductor M16 is connected with the drain electrode of described the 17 metal-oxide-semiconductor M17; The grid of described the 17 metal-oxide-semiconductor M17 meets power vd D, the source ground GND of described the 17 metal-oxide-semiconductor M17; The source electrode of described the 23 metal-oxide-semiconductor M23 meets power vd D, the grid of described the 23 metal-oxide-semiconductor M23 is connected with the drain electrode of described the 20 metal-oxide-semiconductor M20, and the grid of described the 23 metal-oxide-semiconductor M23 is also connected with grid, the 24 drain electrode of metal-oxide-semiconductor M24 and the drain electrode of the 19 metal-oxide-semiconductor M19 of described the 22 metal-oxide-semiconductor M22 respectively; The drain electrode of described the 24 metal-oxide-semiconductor M24 is as output V, and the grid of described the 24 metal-oxide-semiconductor M24 meets the first output signal rdy, and the source electrode of described the 24 metal-oxide-semiconductor M24 meets power vd D; The source electrode of described the 19 metal-oxide-semiconductor M19 is connected with the drain electrode of described the first switching tube M18, the grid of described the 19 metal-oxide-semiconductor M19 is connected with the drain electrode of described the 22 metal-oxide-semiconductor M22, and the grid of described the 19 metal-oxide-semiconductor M19 is also connected with grid and the drain electrode of described the 15 metal-oxide-semiconductor M15 respectively; After the grid of described the 15 metal-oxide-semiconductor M15 and drain electrode connect, be connected with the drain electrode of described the 13 metal-oxide-semiconductor M13, the source electrode of described the 15 metal-oxide-semiconductor M15 is connected with the drain electrode of described the 14 metal-oxide-semiconductor M14; The source ground GND of described the 13 metal-oxide-semiconductor M13; The source electrode of described the 14 metal-oxide-semiconductor M14 meets power vd D, the grounded-grid GND of described the 14 metal-oxide-semiconductor M14; The source electrode of described the first switching tube M18 meets power vd D, and the grid of described the first switching tube M18 meets the delay inversion signal UPb of described the second output signals UP; The source electrode of described the 20 metal-oxide-semiconductor M20 is connected with the drain electrode of described second switch pipe M21; The source ground GND of described second switch pipe M21, the grid of described second switch pipe M21 meets the inhibit signal DN_delay of described the 3rd output signal DN; The source ground GND of described the 22 metal-oxide-semiconductor M22.
In specific embodiments of the invention, the charge pump course of work is as follows: the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 in electric current source generating circuit have identical size, by " bootstrapping " function of electric current, the drain electrode of the 4th metal-oxide-semiconductor M4 produces with the drain electrode of the 3rd metal-oxide-semiconductor M3 the electric current that size is identical.The 5th metal-oxide-semiconductor M5 in the time that circuit powers on, provide one article from power vd D through the 4th metal-oxide-semiconductor M4, the 6th metal-oxide-semiconductor M6 the current path to ground GND, therefore, the 4th metal-oxide-semiconductor M4 and the 6th metal-oxide-semiconductor M6, the 3rd metal-oxide-semiconductor M3 and the 7th metal-oxide-semiconductor M7 keep not turn-offing.After circuit start, the 5th metal-oxide-semiconductor M5 will be turned off.This electric current source generating circuit produce one with the reference current Iref of independent of power voltage, and the current mirror inflow late-class circuit forming by the 4th metal-oxide-semiconductor M4, the 8th metal-oxide-semiconductor M8.The 9th metal-oxide-semiconductor M9 and the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11 and the 12 metal-oxide-semiconductor M12 form respectively current mirror, and mirror image reference current Iref flow to output V by another two groups of current mirror the 15 metal-oxide-semiconductor M15 and the 19 metal-oxide-semiconductor M19, the 16 metal-oxide-semiconductor M16 and the 20 metal-oxide-semiconductor M20 respectively.When the delay inversion signal UPb of the second output signals UP is the inhibit signal DN_delay of " 0 " and the 3rd output signal DN during for " 0 ", charged and increased thereby control voltage Vc; When the delay inversion signal UPb of the second output signals UP is the inhibit signal DN_delay of " 1 " and the 3rd output signal DN during for " 1 ", thereby Vc is discharged and reduces.When the delay inversion signal UPb of the second output signals UP is that the inhibit signal DN_delay of " 0 " and the 3rd output signal DN is during for " 1 ", control voltage Vc is discharged and recharged simultaneously, when design, should make charging and discharging currents equal and opposite in direction, make to control voltage Vc and remain unchanged.When the delay inversion signal UPb of the second output signals UP is the inhibit signal DN_delay of " 1 " and the 3rd output signal DN during for " 0 ", control voltage Vc and neither charged, be not also discharged, control voltage Vc and remain unchanged.In addition, the effect of the 22 metal-oxide-semiconductor M22 and the 23 metal-oxide-semiconductor M23 is the difference that reduces charging and discharging currents size, thereby can reduce the shake of phase-locked loop.The effect of the 24 metal-oxide-semiconductor M24 is in the time that the first output signal rdy signal is " 0 ", and the control voltage Vc of output is become to power vd D, and then the first output signal rdy becomes " 1 ", and the 24 metal-oxide-semiconductor M24 is turned off.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 1, described voltage controlled delay line 13 comprises the differential voltage-controlled delay cell 131 of the first order, the differential voltage-controlled delay cell 132 in the second level, the differential voltage-controlled delay cell 133 of the third level, the differential voltage-controlled delay cell 134 of the fourth stage and the differential voltage-controlled delay cell 135 of level V with same structure, wherein
The first input end of the differential voltage-controlled delay cell 131 of the described first order is connected with the first reference clock signal CLK_P, the second input of the differential voltage-controlled delay cell 131 of the described first order is connected with the second reference clock signal CLK_N, the first output of the differential voltage-controlled delay cell 131 of the described first order is connected with the first input end of the differential voltage-controlled delay cell in the described second level, and the second output of the differential voltage-controlled delay cell 131 of the described first order is connected with the second input of the differential voltage-controlled delay cell 132 in the described second level;
The first output of the differential voltage-controlled delay cell 132 in the described second level is connected with the first input end of the differential voltage-controlled delay cell 133 of the described third level, and the second output of the differential voltage-controlled delay cell 132 in the described second level is connected with the second input of the differential voltage-controlled delay cell 133 of the described third level;
The first output of the differential voltage-controlled delay cell 133 of the described third level is connected with the first input end of the differential voltage-controlled delay cell 134 of the described fourth stage, and the second output of the differential voltage-controlled delay cell 133 of the described third level is connected with the second input of the differential voltage-controlled delay cell 134 of the described fourth stage;
The first output of the differential voltage-controlled delay cell 134 of the described fourth stage is connected with the first input end of the differential voltage-controlled delay cell 135 of described level V, and the second output of the differential voltage-controlled delay cell 134 of the described fourth stage is connected with the second input of the differential voltage-controlled delay cell 135 of described level V;
Wherein, as shown in Figure 7, every grade of described differential voltage-controlled delay cell comprises:
Voltage control tail current source M25, the first input metal-oxide-semiconductor M26, the second input metal-oxide-semiconductor M27, the first load metal-oxide-semiconductor M28, the second load metal-oxide-semiconductor M29, the 3rd load metal-oxide-semiconductor M30, the 4th load metal-oxide-semiconductor M31, the 9th inverter I9, the tenth inverter I10;
Wherein, the source ground GND of described voltage control tail current source M25, the grid of described voltage control tail current source M25 connects controls voltage Vc, and the drain electrode of described voltage control tail current source M25 is connected with the source electrode of described the first input metal-oxide-semiconductor M26 and the source electrode of described the second input metal-oxide-semiconductor M27 respectively; Described the first input metal-oxide-semiconductor M26 the grid first output OUT1 that is described differential voltage-controlled delay cell, the drain electrode of described the first input metal-oxide-semiconductor M26 is connected with the input of described the 9th inverter I9; The output of described the 9th inverter I9 is the first input end Vin1 of described differential voltage-controlled delay cell, describedly be connected with the drain electrode of described the first load metal-oxide-semiconductor M28 and the grid of described the 3rd load metal-oxide-semiconductor M30, drain electrode respectively, the output of described the 9th inverter I9 is also connected with the grid of described the second load metal-oxide-semiconductor M29; The source electrode of described the 3rd load metal-oxide-semiconductor M30 meets power vd D; The source electrode of described the first load metal-oxide-semiconductor M28 meets power vd D, the grid of described the first load metal-oxide-semiconductor M28 is connected with the drain electrode of the second load metal-oxide-semiconductor M29 and drain electrode, the grid of the 4th load metal-oxide-semiconductor M31 respectively, and the grid of described the first load metal-oxide-semiconductor M28 is also connected with the input of described the tenth inverter I10 and the drain electrode of described the second input metal-oxide-semiconductor M27 respectively; The source electrode of the second load metal-oxide-semiconductor M29 meets power vd D; The source electrode of described the 4th load metal-oxide-semiconductor M31 meets power vd D; The output of described the tenth inverter I10 is the second input Vin2 of described differential voltage-controlled delay cell; The second output OUT2 that the grid of described the second input metal-oxide-semiconductor M27 is described differential voltage-controlled delay cell.
Voltage controlled delay line 13 is made up of 5 identical differential voltage-controlled delay cells, can suppress well the interference of common-mode noise.Wherein, front level Four is used for producing the delay clock signals that seven groups of phase place equal proportions increase.In order to make the differential voltage-controlled delay cell of the fourth stage there is identical load with first three grade of differential voltage-controlled delay cell, after the differential voltage-controlled delay cell of the fourth stage, be provided with the differential voltage-controlled delay cell of level V, be called dummy unit.Voltage control tail current source M25 is subject to charge pump through capacitor C lthe control of control voltage Vc of output, its output current determines by controlling voltage Vc, this electric current can be realized the different time delay to input signal after by mean allocation to two branch road and export.And along with controlling reducing of voltage Vc, the delay of voltage controlled delay line constantly increases.Because adopting the grid leak of described the first load metal-oxide-semiconductor M28, described the second load metal-oxide-semiconductor M29 to intersect, load unit is connected, form positive feedback structure, therefore can realize the quick upset of signal, guarantee that output waveform reaches fully differential, reduce the distortion of output signal simultaneously.In addition, this delay cell can directly be controlled by charge pump through capacitor C lthe control voltage Vc of output, without bias-voltage generating circuit.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 2, described output latch circuit 14 comprises the first output latch 141, the second output latch 142, the 3rd output latch 143 and the 4th output latch 144 with same structure; The first input end of described the first output latch 141 is connected with the first output of the differential voltage-controlled delay cell 131 of the described first order, the second input of described the first output latch 141 is connected with the second output of the differential voltage-controlled delay cell 131 of the described first order, the first output of described the first output latch 141 is exported described the first delay clock signals ck1, and the second output of described the first output latch 141 is exported described the first delay clock signals ck4;
The first input end of described the second output latch 142 is connected with the first output of the differential voltage-controlled delay cell 132 in the described second level, the second input of described the second output latch 142 is connected with the second output of the differential voltage-controlled delay cell 132 in the described second level, the first output of described the second output latch 142 is exported described the second delay clock signals ck2, and the second output of described the second output latch 142 is exported described the 5th delay clock signals ck5;
The first input end of described the 3rd output latch 143 is connected with the first output of the differential voltage-controlled delay cell 133 of the described third level, the second input of described the 3rd output latch 143 is connected with the second output of the differential voltage-controlled delay cell 133 of the described third level, the first output of described the 3rd output latch 143 is exported described the 3rd delay clock signals ck3, and the second output of described the 3rd output latch 143 is exported described the 6th delay clock signals ck6;
The first input end of described the 4th output latch 144 is connected with the first output of the differential voltage-controlled delay cell 134 of the described fourth stage, the second input of described the 4th output latch 144 is connected with the second output of the differential voltage-controlled delay cell 134 of the described fourth stage, and the first output of described the 4th output latch 144 is exported described the 7th delay clock signals ck7;
Wherein, as shown in Figure 8, each described output latch comprises:
The 11 inverter I11, the 12 inverter I12, the 13 inverter I13, the 14 inverter I14, the 15 inverter I15 and the tenth hex inverter I16;
Wherein, the first input end IN1 that the input of described the 11 inverter I11 is described output latch, the input of the 12 inverter I12 described in the output termination of described the 11 inverter I11; The output of the 12 inverter I12 is connected with the output of described the 15 inverter I15 and the input of described the tenth hex inverter I16 respectively, and the output of the 12 inverter I12 is as the first output OUT3 of described output latch; The input of described the 15 inverter I15 is connected with the output of described the 14 inverter I14 and the output of described the tenth hex inverter I16 respectively, and the output of described the 14 inverter I14 is as described output latch the second output OUT4; The input of described the 14 inverter I14 is connected with the output of described the 13 inverter I13; The input of described the 13 inverter I13 is as the second input IN2 of described output latch.
The function of output clock latch cicuit is by the not good two phase clock latch output of anti-phase performance originally, and makes them become strict anti-phase two phase clock.The delay clock signals of first input end IN1 is from the first output OUT1 output after two-stage inverter, and the delay clock signals of the second input IN2 is exported from the second output OUT2 after two-stage inverter.Wherein, the delay clock signals of the delay clock signals of first input end IN1 and the second input IN2 is the inversion signal of voltage controlled delay line output.In addition, inverter I15 and inverter I16 form static latch, make the signal of the first output OUT3 and the second output OUT4 output have rollover characteristics and good anti-phase characteristic fast.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, as shown in Figure 2, described edge combinational circuit comprises six dutyfactor adjustment circuits with same structure;
Wherein, the first input end of the first Circuit tuning in described six dutyfactor adjustment circuits meets described the first delay clock signals ck1, the 5th delay clock signals ck5 described in the second input termination of described the first Circuit tuning, the output of described the first Circuit tuning is exported the first input clock signal A1;
The first input end of the second Circuit tuning in described six dutyfactor adjustment circuits meets described the second delay clock signals ck2, the 6th delay clock signals ck6 described in the second input termination of described the second Circuit tuning, the output of described the second Circuit tuning is exported the second input clock signal A2;
The first input end of the 3rd Circuit tuning in described six dutyfactor adjustment circuits meets described the 3rd delay clock signals ck3, the first delay clock signals ck1 described in the second input termination of described the 3rd Circuit tuning, output output the 3rd input clock signal A3 of described the 3rd Circuit tuning;
The first input end of the 4th Circuit tuning in described six dutyfactor adjustment circuits meets described the 4th delay clock signals ck4, the second delay clock signals ck2 described in the second input termination of described the 3rd Circuit tuning, output output the 4th input clock signal A4 of described the 4th Circuit tuning;
The first input end of the 5th Circuit tuning in described six dutyfactor adjustment circuits meets described the 5th delay clock signals ck5, the 3rd delay clock signals ck3 described in the second input termination of described the 3rd Circuit tuning, output output the 5th input clock signal A5 of described the 5th Circuit tuning;
The first input end of the 6th Circuit tuning in described six dutyfactor adjustment circuits meets described the 5th delay clock signals ck6, the 3rd delay clock signals ck4 described in the second input termination of described the 3rd Circuit tuning, output output the 6th input clock signal A6 of described the 6th Circuit tuning;
Wherein, as shown in figure 10, each described dutyfactor adjustment circuit comprises:
The 17 inverter I17, eighteen incompatibilities phase device I18, the 19 inverter I19, the 20 inverter I20, the 21 inverter I21, the 22 inverter I22, the 23 inverter I23, the 32 metal-oxide-semiconductor M32, the 33 metal-oxide-semiconductor M33, the 34 metal-oxide-semiconductor M34, the 35 metal-oxide-semiconductor M35;
Wherein, the first input end fall that described the 17 input of inverter I17 and the grid of the 33 metal-oxide-semiconductor M33 are described dutyfactor adjustment circuit; The output of described the 17 inverter I17 is connected with the input of described eighteen incompatibilities phase device I18, and the output of described eighteen incompatibilities phase device I18 is connected with the input of described the 19 inverter I19; The output of described the 19 inverter I19 is connected with the grid of described the 32 metal-oxide-semiconductor M32; The source electrode of described the 32 metal-oxide-semiconductor M32 meets power vd D, and the drain electrode of described the 32 metal-oxide-semiconductor M32 is connected with described the 33 metal-oxide-semiconductor M33 source electrode; The drain electrode of described the 33 metal-oxide-semiconductor M33 is connected with described the 23 input of inverter I23 and the drain electrode of described the 34 metal-oxide-semiconductor M34 respectively; The output of described the 23 inverter I23 is the output OUT of described dutyfactor adjustment circuit; The second input rise that described the 20 input of inverter I20 and the grid of described the 35 metal-oxide-semiconductor M35 are described dutyfactor adjustment circuit; The output of described the 20 inverter I20 is connected with the input of described the 21 inverter I21; The output of described the 21 inverter I21 is connected with the input of described the 22 inverter I22; The output of described the 22 inverter I22 is connected with the grid of described the 34 metal-oxide-semiconductor M34; The source electrode of described the 34 metal-oxide-semiconductor M34 is connected with the drain electrode of described the 35 metal-oxide-semiconductor M35, the source ground GND of described the 35 metal-oxide-semiconductor M35.
In specific embodiments of the invention, described dutyfactor adjustment circuit as described in Figure 10.Wherein, the signal deciding that the trailing edge of output OUT output signal is inputted by first input end fall, rising edge is by the signal deciding of the second input rise input.The arrival of the trailing edge of first input end fall input signal makes the 33 metal-oxide-semiconductor M33 conducting, and now the 32 conducting of metal-oxide-semiconductor M32.Therefore, node C is charged to high level VDD, then after inverter I23 output low level GND.Thereafter, the 32 metal-oxide-semiconductor M32 disconnects prior to the 33 metal-oxide-semiconductor M33, and the signal of the state of node C and first input end fall input is irrelevant.The arrival of the rising edge of the second input rise input signal makes the 35 metal-oxide-semiconductor M35 conducting, and now the 34 conducting of metal-oxide-semiconductor M34, therefore node C is discharged to low level GND, then exports high level VDD after inverter I23.Thereafter, the 34 metal-oxide-semiconductor M34 disconnects prior to the 35 metal-oxide-semiconductor M35, and the input signal of the state of node C and the second input rise is irrelevant.As can be seen here, the trailing edge of output OUT output signal is determined by the trailing edge of the input signal of first input end fall; The rising edge of output signal is determined by the rising edge of the input signal of the second input rise.Therefore, this circuit has been realized the function that clock signal duty cycle is adjusted.
In specific embodiments of the invention, edge combinational circuit is specifically by the first delay clock signals ck1 and the 5th delay clock signals ck5 combination results the first input clock signal A1, by the second delay clock signals ck2 and the 6th delay clock signals ck6 combination results the second input clock signal A2, by the 3rd delay clock signals ck3 and the first delay clock signals ck1 combination results the 3rd input clock signal A3, by the 4th delay clock signals ck4 and the second delay clock signals ck2 combination results the 4th input clock signal A4, by the 5th delay clock signals ck5 and the 3rd delay clock signals ck3 combination results the 5th input clock signal A5, by the 6th delay clock signals ck6 and the 4th delay clock signals ck4 combination results the 6th input clock signal A6.
Wherein, the first input clock signal A1 is that duty ratio is 20% clock signal, can be used as the input clock signal of single channel gradual approaching A/D converter.As shown in figure 11, the second input clock signal A2 is that duty ratio is 20% clock signal, and its phase place postpones 60 ° than A1; The 3rd input clock signal A3 is that duty ratio is 20% clock signal, and its phase place postpones 120 ° than A1; The 4th input clock signal A4 is that duty ratio is 20% clock signal, and its phase place postpones 180 ° than A1; The 5th input clock signal A5 is that duty ratio is 20% clock signal, and its phase place postpones 240 ° than A1; The 6th input clock signal A6 is that duty ratio is 20% clock signal, and its phase place postpones 300 ° than A1.Above-mentioned six equal phase are poor, duty ratio is 20% signal and can be used as the interweave clock input signal of gradual approaching A/D converter of clock.
The clock generator based on analogue delay phase-locked loop of the embodiment of the present invention, produce six groups of duty ratios 50% by closed loop feedback system, the delay clock signals that phase place equal proportion increases, through edge combinational circuit, six groups of delay clock signals are recombinated again, can produce six groups of duty ratios is 20%, the input clock signal that phase place equal proportion increases, solved the accurate not problem of traditional frequency divider clock, further improved the interweave overall performance of gradual approaching A/D converter of six channel clocks.
The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (11)

1. the clock generator based on analogue delay phase-locked loop, is applied to time-interleaved gradual approaching A/D converter, it is characterized in that, comprising:
For according to reference clock signal, produce the closed loop feedback system of many group delay clock signals;
Be connected with described closed loop feedback system, for the duty ratio of described many group delay clock signals is adjusted, and export the edge combinational circuit of the input clock signal of described time-interleaved gradual approaching A/D converter.
2. the clock generator based on analogue delay phase-locked loop according to claim 1, is characterized in that,
Described closed loop feedback system produces the delay clock signals that six groups of duty ratios are 50%, and wherein, the phase place equal proportion of described six groups of delay clock signals increases.
3. the clock generator based on analogue delay phase-locked loop according to claim 2, is characterized in that,
Described six groups of delay clock signals are carried out combination of two processing by described edge combinational circuit, exports six groups of input clock signals that duty ratio is 20%, and wherein, the phase difference that carries out two groups of delay clock signals of combined treatment is preset value.
4. the clock generator based on analogue delay phase-locked loop according to claim 2, it is characterized in that, described closed loop feedback system comprises: phase discriminator, the charge pump being connected with described phase discriminator, the loop filter being connected with described charge pump, the respectively voltage controlled delay line that is connected with described loop filter and described charge pump and the output latch circuit being connected with described voltage controlled delay line;
Wherein, the first delay clock signals (ck1) that described phase discriminator feeds back for detection of described output latch circuit and the phase difference of the 7th delay clock signals (ck7), and export a testing result;
Described charge pump is for being converted to electric current by described testing result;
Described loop filter is used for described current conversion for controlling voltage (Vc);
Described voltage controlled delay line is for producing according to described control voltage (Vc) and described reference clock signal the delay clock signals that seven groups of duty ratios are 50%, wherein, described seven groups of delay clock signals comprise the first delay clock signals (ck1), the second delay clock signals (ck2), the 3rd delay clock signals (ck3), the 4th delay clock signals (ck4), the 5th delay clock signals (ck5), the 6th delay clock signals (ck6) and the 7th delay clock signals (ck7) that phase place equal proportion increases;
Described output latch circuit is for seven groups of delay clock signals described in latch, and the first delay clock signals (ck1), the second delay clock signals (ck2), the 3rd delay clock signals (ck3), the 4th delay clock signals (ck4), the 5th delay clock signals (ck5) and the 6th delay clock signals (ck6) are exported to described edge combinational circuit, described the first delay clock signals (ck1) and the 7th delay clock signals (ck7) are fed back to described phase discriminator simultaneously.
5. the clock generator based on analogue delay phase-locked loop according to claim 4, is characterized in that, described phase discriminator comprises:
The first inverter (I1), the first rising edge flip-over type d type flip flop (FF1), the second rising edge flip-over type d type flip flop (FF2), the 3rd rising edge flip-over type d type flip flop (FF3), the first NAND gate (N1), the second NAND gate (N2);
Wherein, input termination first input signal (start) of described the first inverter (I1), the output of described the first inverter (I1) is connected with the reset terminal (Rst) of described the first rising edge flip-over type d type flip flop (FF1); The data input pin (D) of described the first rising edge flip-over type d type flip flop (FF1) connects power supply (VDD), output (Q) output first output signal (rdy) of described the first rising edge flip-over type d type flip flop (FF1), and be connected with the data input pin (D) of the 3rd rising edge flip-over type d type flip flop (FF3), the input end of clock (clk) of described the first rising edge flip-over type d type flip flop (FF1) is connected with the first delay clock signals (ck1); The input end of clock (clk) of described the second rising edge flip-over type d type flip flop (FF2) is connected with the 7th delay clock signals (ck7), the data input pin (D) of described the second rising edge flip-over type d type flip flop (FF2) is connected with power supply (VDD), output (Q) output the 3rd output signal (DN) of described the second rising edge flip-over type d type flip flop (FF2); The input end of clock (clk) of described the 3rd rising edge flip-over type d type flip flop (FF3) connects the first delay clock signals (ck1), output (Q) output second output signal (UP) of described the 3rd rising edge flip-over type d type flip flop (FF3); Two inputs of described the first NAND gate (N1) connect respectively described the second output signal (UP) and described the 3rd output signal (DN), and the output of described the first NAND gate (N1) is connected with the first input end of described the second NAND gate (N2); The first input signal (start) described in the second input termination of described the second NAND gate (N2), the output of described the second NAND gate (N2) is connected with the reset terminal (Rst) of the 3rd rising edge flip-over type d type flip flop (FF3) and the reset terminal (Rst) of the second rising edge flip-over type d type flip flop (FF2) respectively.
6. the clock generator based on analogue delay phase-locked loop according to claim 5, it is characterized in that, described charge pump comprises: input signal Circuit tuning, and described input signal Circuit tuning comprises: the anti-phase Circuit tuning of the second output signal (UP) and the 3rd output signal (DN) delay regulating circuit;
Wherein, the anti-phase Circuit tuning of described the second output signal (UP) comprises:
The second inverter (I2), the 3rd inverter (I3), the 4th inverter (I4), the first metal-oxide-semiconductor (M1), the second metal-oxide-semiconductor (M2);
Wherein, the second output signal (UP) described in the input termination of described the second inverter (I2), the output of described the second inverter (I2) is connected with the drain electrode of described the first metal-oxide-semiconductor (M1) and the source electrode of the second metal-oxide-semiconductor (M2) respectively; The grid of described the first metal-oxide-semiconductor (M1) connects power supply (VDD), the source electrode of described the first metal-oxide-semiconductor (M1) is connected with the drain electrode of described the second metal-oxide-semiconductor (M2), and the drain electrode of the first metal-oxide-semiconductor (M1) is connected with the source electrode of the second metal-oxide-semiconductor (M2); The grounded-grid of the second metal-oxide-semiconductor (M2); The input of described the 3rd inverter (I3) is connected with the drain electrode of described the second metal-oxide-semiconductor (M2) with the source electrode of described the first metal-oxide-semiconductor (M1) respectively, and the output of described the 3rd inverter (I3) is connected with the input of described the 4th inverter (I4); The output signal of described the 4th inverter (I4) is the delay inversion signal (UPb) of described the second output signal (UP).
Described the 3rd output signal (DN) delay regulating circuit comprises:
The 5th inverter (I5), hex inverter (I6), the 7th inverter (I7), the 8th inverter (I8);
Wherein, the 3rd output signal (DN) described in the input termination of described the 5th inverter (I5), the output of described the 5th inverter (I5) is connected with the input of described hex inverter (I6); The output of described hex inverter (I6) is connected with the input of described the 7th inverter (I7); The output of described the 7th inverter (I7) is connected with the input of described the 8th inverter (I8); The output of described the 8th inverter (I8) is exported the inhibit signal (DN_delay) of described the 3rd output signal (DN);
7. the clock generator based on analogue delay phase-locked loop according to claim 6, is characterized in that, described charge pump also comprises: charge pump main body circuit, and described charge pump main body circuit comprises: electric current source generating circuit and current mirror charge-discharge circuit;
Wherein, described electric current source generating circuit comprises:
The 3rd metal-oxide-semiconductor (M3), the 4th metal-oxide-semiconductor (M4), the 5th metal-oxide-semiconductor (M5), the 6th metal-oxide-semiconductor (M6), the 7th metal-oxide-semiconductor (M7), the 8th metal-oxide-semiconductor (M8), the first resistance (R1);
Wherein, the source electrode of described the 3rd metal-oxide-semiconductor (M3) is connected with power supply (VDD), the grid of described the 3rd metal-oxide-semiconductor (M3) is connected with grid and the drain electrode of described the 5th metal-oxide-semiconductor (M5) respectively, the grid of described the 3rd metal-oxide-semiconductor (M3) is also connected with grid and the drain electrode of described the 4th metal-oxide-semiconductor (M4) respectively, and the drain electrode of described the 3rd metal-oxide-semiconductor (M3) is connected with drain electrode and the grid of described the 6th metal-oxide-semiconductor (M6) respectively; The source ground (GND) of described the 6th metal-oxide-semiconductor (M6), the drain and gate of described the 6th metal-oxide-semiconductor (M6) is connected with the source electrode of described the 5th metal-oxide-semiconductor (M5) after connecting, and the drain and gate of described the 6th metal-oxide-semiconductor (M6) is also connected with the grid of described the 7th metal-oxide-semiconductor (M7) after connecting; The grid of described the 4th metal-oxide-semiconductor (M4) is connected with the drain electrode of described the 7th metal-oxide-semiconductor (M7) after being connected with drain electrode, the grid of described the 4th metal-oxide-semiconductor (M4) is also connected with the grid of described the 8th metal-oxide-semiconductor (M8) after being connected with drain electrode, and the source electrode of described the 4th metal-oxide-semiconductor (M4) connects power supply (VDD); The source electrode of described the 8th metal-oxide-semiconductor (M8) connects power supply (VDD), and the drain electrode of described the 8th metal-oxide-semiconductor (M8) is connected with described current mirror charge-discharge circuit; One end of described the first resistance (R1) is connected with the source electrode of described the 7th metal-oxide-semiconductor (M7), other end ground connection (GND);
Described current mirror charge-discharge circuit comprises:
The 9th metal-oxide-semiconductor (M9), the tenth metal-oxide-semiconductor (M10), the 11 metal-oxide-semiconductor (M11), the 12 metal-oxide-semiconductor (M12), the 13 metal-oxide-semiconductor (M13), the 14 metal-oxide-semiconductor (M14), the 15 metal-oxide-semiconductor (M15), the 16 metal-oxide-semiconductor (M16), the 17 metal-oxide-semiconductor (M17), the first switching tube (M18), the 19 metal-oxide-semiconductor (M19), the 20 metal-oxide-semiconductor (M20), second switch pipe (M21), the 22 metal-oxide-semiconductor (M22), the 23 metal-oxide-semiconductor (M23), the 24 metal-oxide-semiconductor (M24),
Wherein, the source ground (GND) of described the 9th metal-oxide-semiconductor (M9), the grid of described the 9th metal-oxide-semiconductor (M9) is connected with the drain electrode of described the 8th metal-oxide-semiconductor (M8), described the tenth grid of metal-oxide-semiconductor (M10) and the grid of described the 13 metal-oxide-semiconductor (M13) respectively after being connected with drain electrode; The source ground (GND) of described the tenth metal-oxide-semiconductor (M10), the drain electrode of described the tenth metal-oxide-semiconductor (M10) is connected with the drain and gate of described the 11 metal-oxide-semiconductor (M11) respectively; The source electrode of described the 11 metal-oxide-semiconductor (M11) connects power supply (VDD), and the drain and gate of described the 11 metal-oxide-semiconductor (M11) is connected with the grid of described the 12 metal-oxide-semiconductor (M12) after connecting; The source electrode of described the 12 metal-oxide-semiconductor (M12) connects power supply (VDD), and described the 12 metal-oxide-semiconductor (M12) drain electrode is connected with drain electrode and the grid of described the 16 metal-oxide-semiconductor (M16) respectively; After the drain electrode of described the 16 metal-oxide-semiconductor (M16) is connected with grid, be connected respectively with described the 23 drain electrode of metal-oxide-semiconductor (M23) and the grid of described the 20 metal-oxide-semiconductor (M20), the source electrode of described the 16 metal-oxide-semiconductor (M16) is connected with the drain electrode of described the 17 metal-oxide-semiconductor (M17); The grid of described the 17 metal-oxide-semiconductor (M17) connects power supply (VDD), the source ground (GND) of described the 17 metal-oxide-semiconductor (M17); The source electrode of described the 23 metal-oxide-semiconductor (M23) connects power supply (VDD), the grid of described the 23 metal-oxide-semiconductor (M23) is connected with the drain electrode of described the 20 metal-oxide-semiconductor (M20), and the grid of described the 23 metal-oxide-semiconductor (M23) is also connected with grid, the 24 drain electrode of metal-oxide-semiconductor (M24) and the drain electrode of the 19 metal-oxide-semiconductor (M19) of described the 22 metal-oxide-semiconductor (M22) respectively; The drain electrode of described the 24 metal-oxide-semiconductor (M24) connects controls voltage (Vc), the grid of described the 24 metal-oxide-semiconductor (M24) connects the first output signal (rdy), and the source electrode of described the 24 metal-oxide-semiconductor (M24) connects power supply (VDD); The source electrode of described the 19 metal-oxide-semiconductor (M19) is connected with the drain electrode of described the first switching tube (M18), the grid of described the 19 metal-oxide-semiconductor (M19) is connected with the drain electrode of described the 22 metal-oxide-semiconductor (M22), and the grid of described the 19 metal-oxide-semiconductor (M19) is also connected with grid and the drain electrode of described the 15 metal-oxide-semiconductor (M15) respectively; After the grid of described the 15 metal-oxide-semiconductor (M15) and drain electrode connect, be connected with the drain electrode of described the 13 metal-oxide-semiconductor (M13), the source electrode of described the 15 metal-oxide-semiconductor (M15) is connected with the drain electrode of described the 14 metal-oxide-semiconductor (M14); The source ground (GND) of described the 13 metal-oxide-semiconductor (M13); The source electrode of described the 14 metal-oxide-semiconductor (M14) connects power supply (VDD), the grounded-grid (GND) of described the 14 metal-oxide-semiconductor (M14); The source electrode of described the first switching tube (M18) connects power supply (VDD), and the grid of described the first switching tube (M18) connects the delay inversion signal (UPb) of described the second output signal (UP); The source electrode of described the 20 metal-oxide-semiconductor (M20) is connected with the drain electrode of described second switch pipe (M21); The source ground GND of described second switch pipe (M21), the grid of described second switch pipe (M21) connects the inhibit signal (DN_delay) of described the 3rd output signal (DN); The source ground (GND) of described the 22 metal-oxide-semiconductor (M22).
8. the clock generator based on analogue delay phase-locked loop according to claim 4, is characterized in that, described loop filter is specially electric capacity (C l), described electric capacity (C l) one end be connected with described charge pump and described voltage controlled delay line respectively, and output control voltage (Vc), described electric capacity (C l) other end ground connection (GND).
9. the clock generator based on analogue delay phase-locked loop according to claim 4, it is characterized in that, described voltage controlled delay line comprises the differential voltage-controlled delay cell of the first order, the differential voltage-controlled delay cell in the second level, the differential voltage-controlled delay cell of the third level, the differential voltage-controlled delay cell of the fourth stage and the differential voltage-controlled delay cell of level V with same structure, wherein
The first input end of the differential voltage-controlled delay cell of the described first order is connected with the first reference clock signal (CLK_P), the second input of the differential voltage-controlled delay cell of the described first order is connected with the second reference clock signal (CLK_N), the first output of the differential voltage-controlled delay cell of the described first order is connected with the first input end of the differential voltage-controlled delay cell in the described second level, and the second output of the differential voltage-controlled delay cell of the described first order is connected with the second input of the differential voltage-controlled delay cell in the described second level;
The first output of the differential voltage-controlled delay cell in the described second level is connected with the first input end of the differential voltage-controlled delay cell of the described third level, and the second output of the differential voltage-controlled delay cell in the described second level is connected with the second input of the differential voltage-controlled delay cell of the described third level;
The first output of the differential voltage-controlled delay cell of the described third level is connected with the first input end of the differential voltage-controlled delay cell of the described fourth stage, and the second output of the differential voltage-controlled delay cell of the described third level is connected with the second input of the differential voltage-controlled delay cell of the described fourth stage;
The first output of the differential voltage-controlled delay cell of the described fourth stage is connected with the first input end of the differential voltage-controlled delay cell of described level V, and the second output of the differential voltage-controlled delay cell of the described fourth stage is connected with the second input of the differential voltage-controlled delay cell of described level V;
Wherein, every grade of described differential voltage-controlled delay cell comprises:
Voltage control tail current source (M25), the first input metal-oxide-semiconductor (M26), the second input metal-oxide-semiconductor (M27), the first load metal-oxide-semiconductor (M28), the second load metal-oxide-semiconductor (M29), the 3rd load metal-oxide-semiconductor (M30), the 4th load metal-oxide-semiconductor (M31), the 9th inverter (I9), the tenth inverter (I10);
Wherein, the source ground (GND) of described voltage control tail current source (M25), the grid of described voltage control tail current source (M25) connects controls voltage (Vc), and the drain electrode of described voltage control tail current source (M25) is connected with the source electrode of described the first input metal-oxide-semiconductor (M26) and the source electrode of described the second input metal-oxide-semiconductor (M27) respectively; Described the first input metal-oxide-semiconductor (M26) grid the first output (OUT1) that is described differential voltage-controlled delay cell, the drain electrode of described the first input metal-oxide-semiconductor (M26) is connected with the input of described the 9th inverter (I9); The first input end (Vin1) that the output of described the 9th inverter (I9) is described differential voltage-controlled delay cell, describedly be connected with the drain electrode of described the first load metal-oxide-semiconductor (M28) and the grid of described the 3rd load metal-oxide-semiconductor (M30), drain electrode respectively, the output of described the 9th inverter (I9) is also connected with the grid of described the second load metal-oxide-semiconductor (M29); The source electrode of described the 3rd load metal-oxide-semiconductor (M30) connects power supply (VDD); The source electrode of described the first load metal-oxide-semiconductor (M28) connects power supply (VDD), the grid of described the first load metal-oxide-semiconductor (M28) respectively with the second load metal-oxide-semiconductor (M29)
Drain electrode and the drain electrode of the 4th load metal-oxide-semiconductor (M31), grid connect, the grid of described the first load metal-oxide-semiconductor (M28) is also connected with the input of described the tenth inverter (I10) and the drain electrode of described the second input metal-oxide-semiconductor (M27) respectively; The source electrode of the second load metal-oxide-semiconductor (M29) connects power supply (VDD); The source electrode of described the 4th load metal-oxide-semiconductor (M31) connects power supply (VDD); The second input (Vin2) that the output of described the tenth inverter (I10) is described differential voltage-controlled delay cell; The second output (OUT2) that the grid of described the second input metal-oxide-semiconductor (M27) is described differential voltage-controlled delay cell.
10. the clock generator based on analogue delay phase-locked loop according to claim 9, it is characterized in that, described output latch circuit comprises the first output latch, the second output latch, the 3rd output latch and the 4th output latch with same structure; The first input end of described the first output latch is connected with the first output of the differential voltage-controlled delay cell of the described first order, the second input of described the first output latch is connected with the second output of the differential voltage-controlled delay cell of the described first order, the first output of described the first output latch is exported described the first delay clock signals (ck1), and the second output of described the first output latch is exported described the first delay clock signals (ck4);
The first input end of described the second output latch is connected with the first output of the differential voltage-controlled delay cell in the described second level, the second input of described the second output latch is connected with the second output of the differential voltage-controlled delay cell in the described second level, the first output of described the second output latch is exported described the second delay clock signals (ck2), and the second output of described the second output latch is exported described the 5th delay clock signals (ck5);
The first input end of described the 3rd output latch is connected with the first output of the differential voltage-controlled delay cell of the described third level, the second input of described the 3rd output latch is connected with the second output of the differential voltage-controlled delay cell of the described third level, the first output of described the 3rd output latch is exported described the 3rd delay clock signals (ck3), and the second output of described the 3rd output latch is exported described the 6th delay clock signals (ck6);
The first input end of described the 4th output latch is connected with the first output of the differential voltage-controlled delay cell of the described fourth stage, the second input of described the 4th output latch is connected with the second output of the differential voltage-controlled delay cell of the described fourth stage, and the first output of described the 4th output latch is exported described the 7th delay clock signals (ck7);
Wherein, each described output latch comprises:
The 11 inverter (I11), the 12 inverter (I12), the 13 inverter (I13), the 14 inverter (I14), the 15 inverter (I15) and the tenth hex inverter (I16);
Wherein, the first input end (IN1) that the input of described the 11 inverter (I11) is described output latch, the input of the 12 inverter (I12) described in the output termination of described the 11 inverter (I11); The output of the 12 inverter (I12) is connected with the output of described the 15 inverter (I15) and the input of described the tenth hex inverter (I16) respectively, and the output of the 12 inverter (I12) is as first output (OUT3) of described output latch; The input of described the 15 inverter (I15) is connected with the output of described the 14 inverter (I14) and the output of described the tenth hex inverter (I16) respectively, and the output of described the 14 inverter (I14) is as described output latch the second output (OUT4); The input of described the 14 inverter (I14) is connected with the output of described the 13 inverter (I13); The input of described the 13 inverter (I13) is as second input (IN2) of described output latch.
11. clock generators based on analogue delay phase-locked loop according to claim 4, is characterized in that, described edge combinational circuit comprises six dutyfactor adjustment circuits with same structure;
Wherein, the first input end of the first Circuit tuning in described six dutyfactor adjustment circuits connects described the first delay clock signals (ck1), the 5th delay clock signals (ck5) described in the second input termination of described the first Circuit tuning, the output of described the first Circuit tuning is exported the first input clock signal (A1);
The first input end of the second Circuit tuning in described six dutyfactor adjustment circuits connects described the second delay clock signals (ck2), the 6th delay clock signals (ck6) described in the second input termination of described the second Circuit tuning, the output of described the second Circuit tuning is exported the second input clock signal (A2);
The first input end of the 3rd Circuit tuning in described six dutyfactor adjustment circuits connects described the 3rd delay clock signals (ck3), the first delay clock signals (ck1) described in the second input termination of described the 3rd Circuit tuning, output output the 3rd input clock signal (A3) of described the 3rd Circuit tuning;
The first input end of the 4th Circuit tuning in described six dutyfactor adjustment circuits connects described the 4th delay clock signals (ck4), the second delay clock signals (ck2) described in the second input termination of described the 3rd Circuit tuning, output output the 4th input clock signal (A4) of described the 4th Circuit tuning;
The first input end of the 5th Circuit tuning in described six dutyfactor adjustment circuits connects described the 5th delay clock signals (ck5), the 3rd delay clock signals (ck3) described in the second input termination of described the 3rd Circuit tuning, output output the 5th input clock signal (A5) of described the 5th Circuit tuning;
The first input end of the 6th Circuit tuning in described six dutyfactor adjustment circuits connects described the 5th delay clock signals (ck6), the 3rd delay clock signals (ck4) described in the second input termination of described the 3rd Circuit tuning, output output the 6th input clock signal (A6) of described the 6th Circuit tuning;
Wherein, each described dutyfactor adjustment circuit comprises:
The 17 inverter (I17), eighteen incompatibilities phase device (I18), the 19 inverter (I19), the 20 inverter (I20), the 21 inverter (I21), the 22 inverter (I22), the 23 inverter (I23), the 32 metal-oxide-semiconductor (M32), the 33 metal-oxide-semiconductor (M33), the 34 metal-oxide-semiconductor (M34), the 35 metal-oxide-semiconductor (M35);
Wherein, the first input end (fall) that described the 17 input of inverter (I17) and the grid of the 33 metal-oxide-semiconductor (M33) are described dutyfactor adjustment circuit; The output of described the 17 inverter (I17) is connected with the input of described eighteen incompatibilities phase device (I18), and the output of described eighteen incompatibilities phase device (I18) is connected with the input of described the 19 inverter (I19); The output of described the 19 inverter (I19) is connected with the grid of described the 32 metal-oxide-semiconductor (M32); The source electrode of described the 32 metal-oxide-semiconductor (M32) connects power supply (VDD), and the drain electrode of described the 32 metal-oxide-semiconductor (M32) is connected with described the 33 metal-oxide-semiconductor (M33) source electrode; The drain electrode of described the 33 metal-oxide-semiconductor (M33) is connected with described the 23 input of inverter (I23) and the drain electrode of described the 34 metal-oxide-semiconductor (M34) respectively; The output (OUT) that the output of described the 23 inverter (I23) is described dutyfactor adjustment circuit; The second input (rise) that described the 20 input of inverter (I20) and the grid of described the 35 metal-oxide-semiconductor (M35) are described dutyfactor adjustment circuit; The output of described the 20 inverter (I20) is connected with the input of described the 21 inverter (I21); The output of described the 21 inverter (I21) is connected with the input of described the 22 inverter (I22); The output of described the 22 inverter (I22) is connected with the grid of described the 34 metal-oxide-semiconductor (M34); The source electrode of described the 34 metal-oxide-semiconductor (M34) is connected with the drain electrode of described the 35 metal-oxide-semiconductor (M35), the source ground (GND) of described the 35 metal-oxide-semiconductor (M35).
CN201410310797.5A 2014-07-01 2014-07-01 Clock generator based on analog delay phase-locked loop Active CN104113332B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410310797.5A CN104113332B (en) 2014-07-01 2014-07-01 Clock generator based on analog delay phase-locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410310797.5A CN104113332B (en) 2014-07-01 2014-07-01 Clock generator based on analog delay phase-locked loop

Publications (2)

Publication Number Publication Date
CN104113332A true CN104113332A (en) 2014-10-22
CN104113332B CN104113332B (en) 2017-02-15

Family

ID=51709980

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410310797.5A Active CN104113332B (en) 2014-07-01 2014-07-01 Clock generator based on analog delay phase-locked loop

Country Status (1)

Country Link
CN (1) CN104113332B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106374925A (en) * 2015-07-20 2017-02-01 英飞凌科技股份有限公司 Method and apparatus for use in measurement data acquisition
CN110071718A (en) * 2019-03-11 2019-07-30 西安电子科技大学 A kind of sub-sampling phase discriminator and its phaselocked loop
CN110212915A (en) * 2019-05-08 2019-09-06 东南大学 A kind of manifold type frequency multiplication delay locked-loop circuit of uniform split-phase output
CN110545095A (en) * 2019-07-17 2019-12-06 南开大学 Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter
CN113014233A (en) * 2021-03-10 2021-06-22 苏州芯捷联电子有限公司 Clock duty ratio calibration circuit
CN113691259A (en) * 2021-08-27 2021-11-23 中山大学 ADC with four-channel time-interleaved structure and working principle thereof
CN115987083A (en) * 2023-03-14 2023-04-18 合肥乘翎微电子有限公司 Control circuit for reducing electromagnetic radiation, control method thereof and isolated power supply system
CN116388734A (en) * 2023-03-28 2023-07-04 合芯科技有限公司 Duty cycle adjusting circuit and system

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242671A (en) * 1998-07-18 2000-01-26 三星电子株式会社 Digital TV receivers with poly-phase analog-to-digital conversion of baseband symbol coding
CN1551090A (en) * 2003-01-29 2004-12-01 �����ɷ� Display apparatus drive circuit having plurality of cascade connnected drive ics
CN101030779A (en) * 2006-02-01 2007-09-05 沃福森微电子有限公司 Delay-locked loop circuits
CN102075167A (en) * 2010-11-22 2011-05-25 西安电子科技大学 Clock adjustment circuit and adjustment method for clock circuit
CN201869179U (en) * 2010-10-09 2011-06-15 中国电子科技集团公司第五十八研究所 Multi-phase clock generating circuit with programmable dutyfactor
CN102118168A (en) * 2011-04-08 2011-07-06 中国科学院半导体研究所 Sequential-approximation analog-digital converter based on multi-bit serial conversion
CN102369669A (en) * 2009-04-02 2012-03-07 高通股份有限公司 Techniques for non-overlapping clock generation
CN102522994A (en) * 2011-12-07 2012-06-27 清华大学 Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision
CN103856187A (en) * 2012-11-30 2014-06-11 爱思开海力士有限公司 Semiconductor apparatus and duty cycle correction method thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1242671A (en) * 1998-07-18 2000-01-26 三星电子株式会社 Digital TV receivers with poly-phase analog-to-digital conversion of baseband symbol coding
CN1551090A (en) * 2003-01-29 2004-12-01 �����ɷ� Display apparatus drive circuit having plurality of cascade connnected drive ics
CN101030779A (en) * 2006-02-01 2007-09-05 沃福森微电子有限公司 Delay-locked loop circuits
CN102369669A (en) * 2009-04-02 2012-03-07 高通股份有限公司 Techniques for non-overlapping clock generation
CN201869179U (en) * 2010-10-09 2011-06-15 中国电子科技集团公司第五十八研究所 Multi-phase clock generating circuit with programmable dutyfactor
CN102075167A (en) * 2010-11-22 2011-05-25 西安电子科技大学 Clock adjustment circuit and adjustment method for clock circuit
CN102118168A (en) * 2011-04-08 2011-07-06 中国科学院半导体研究所 Sequential-approximation analog-digital converter based on multi-bit serial conversion
CN102522994A (en) * 2011-12-07 2012-06-27 清华大学 Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision
CN103856187A (en) * 2012-11-30 2014-06-11 爱思开海力士有限公司 Semiconductor apparatus and duty cycle correction method thereof

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10575071B2 (en) 2015-07-20 2020-02-25 Infineon Technologies Ag Method and apparatus for use in measurement data acquisition
CN106374925A (en) * 2015-07-20 2017-02-01 英飞凌科技股份有限公司 Method and apparatus for use in measurement data acquisition
CN110071718A (en) * 2019-03-11 2019-07-30 西安电子科技大学 A kind of sub-sampling phase discriminator and its phaselocked loop
CN110212915B (en) * 2019-05-08 2023-01-03 东南大学 Coupling type frequency multiplication delay phase-locked loop circuit with uniform split-phase output
CN110212915A (en) * 2019-05-08 2019-09-06 东南大学 A kind of manifold type frequency multiplication delay locked-loop circuit of uniform split-phase output
CN110545095A (en) * 2019-07-17 2019-12-06 南开大学 Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter
CN110545095B (en) * 2019-07-17 2021-02-12 南开大学 Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter
CN113014233A (en) * 2021-03-10 2021-06-22 苏州芯捷联电子有限公司 Clock duty ratio calibration circuit
CN113014233B (en) * 2021-03-10 2024-01-26 苏州芯捷联电子有限公司 Clock duty cycle calibration circuit
CN113691259A (en) * 2021-08-27 2021-11-23 中山大学 ADC with four-channel time-interleaved structure and working principle thereof
CN115987083A (en) * 2023-03-14 2023-04-18 合肥乘翎微电子有限公司 Control circuit for reducing electromagnetic radiation, control method thereof and isolated power supply system
CN116388734A (en) * 2023-03-28 2023-07-04 合芯科技有限公司 Duty cycle adjusting circuit and system
CN116388734B (en) * 2023-03-28 2024-02-09 合芯科技有限公司 Duty cycle adjusting circuit and system

Also Published As

Publication number Publication date
CN104113332B (en) 2017-02-15

Similar Documents

Publication Publication Date Title
CN104113332A (en) Clock generator based on analog delay phase-locked loop
CN105049043B (en) A kind of high-speed comparator with offset correction function
CN104113303B (en) 50% duty ratio clock generation circuit
ES2646551T3 (en) Circuit to generate precise clock phase signals for a high-speed serializer / deserializer
CN105958971A (en) Clock duty ratio calibration circuit
CN100454755C (en) Annular voltage controlled oscillator
CN106656116A (en) High-linearity phase interpolator
CN104124968A (en) Clock duty ratio calibration circuit for streamlined analog-digital converter
CN103684438B (en) Delay phase-locked loop
CN104868880B (en) Clock generating circuit
CN107231150A (en) Clock correction device and clock correction method
CN103427798B (en) A kind of multiphase clock generation circuit
CN106921391A (en) System-level error correction SAR analog-digital converters
CN110034762A (en) A kind of adjustable analog-digital converter of sample frequency
WO2023123795A1 (en) Duty cycle correction circuit
CN109586696A (en) Offset voltage correcting circuit for dynamic comparer
CN110212915A (en) A kind of manifold type frequency multiplication delay locked-loop circuit of uniform split-phase output
CN104143975A (en) DLL delay link and method for reducing duty cycle distortion of DLL clock
CN106856405B (en) A kind of switching current device and the digital analog converter based on the device
CN102324928B (en) Frequency calibration circuit of active RC (Resistor-Capacitor) filter
CN115576884B (en) Duty ratio adjustable single-end clock-to-differential circuit
CN107395166A (en) Clock duty cycle stabilizing circuit based on delay lock phase
WO2024045269A1 (en) Data sampling circuit, data receiving circuit, and memory
CN106027055A (en) Low-power-consumption two-step flicker type analog to digital converter
CN105577173A (en) Delay locked loop and duty cycle correction circuit for detecting final clock output

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant