CN104112471B - Storage arrangement and the method by reading data in storage arrangement - Google Patents
Storage arrangement and the method by reading data in storage arrangement Download PDFInfo
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Abstract
The present invention provides a kind of storage arrangement and the method by reading data in storage arrangement, wherein the method that a storage arrangement reads data, comprises the following steps：The first memory cell array is provided, the first memory cell array includes the first word-line, and the first data are stored in the first memory cell array；The second memory cell array is provided, the second memory cell array includes the second word-line, and the second memory cell array separates with the first memory cell array, and the second data storage is in the second memory cell array；Select in same time or in overlapping time one of first word-line and one of the second word-line；The first address of the first memory cell array and the second address of the second memory cell array are alternately selected, alternately to read the second corresponding part of the first of the first data the corresponding part and the second data from the first memory cell array and the second memory cell array.With this, solves the restricted problem of reading speed of legacy memory devices.
Description
Technical field
The present invention be on a kind of storage arrangement, especially with regard to the storage arrangement with high speed read functions and
Method by reading data in storage arrangement.
Background technology
Fig. 1 is the schematic diagram for showing a traditional storage arrangement 100.Storage arrangement 100 includes a memory cell battle array
The sensing amplifier 160 of row 110 and one.More pen datas, such as：Bit group（byte）Also it is called byte 0-7, it is single is stored in storage
In element array 110.Memory cell array 110 includes a plurality of word-line（word lines）111st, 112 and multiple bit lines to select
Select the address of data（address）.When reading data during an external device (ED) is intended to by memory cell array 110, in a sensing week
It is interim to be only capable of selecting a word-line, otherwise it will make a mistake.For example, if word-line 111,112 is chosen in the same time,
It is to come from bit group 0 or bit group 4 that then sensing amplifier 160, which will be unable to differentiate reading data,.Therefore, legacy memory devices
100 reading speed will be restricted.
The content of the invention
It is an object of the invention to provide a kind of storage arrangement not limited by reading speed and by storage arrangement
The method for reading data, to solve the problems, such as that the reading speed of legacy memory devices is restricted.
Include to solve the above problems, the present invention provides a kind of storage arrangement：One first memory cell array, including it is more
Individual first word-line and multiple first bit lines, wherein more the first data are stored in first memory cell array；One
Two memory cell arrays, separated with first memory cell array, and including multiple second word-lines and multiple second bit lines, its
In more the second data be stored in second memory cell array；One control logic circuit, it is allowed in a same time or
One of the plurality of first word-line and one of the plurality of second word-line are selected in an overlapping time, and alternately
Select one first address of first memory cell array and one second address of second memory cell array, with from this first
Alternately read in memory cell array and second memory cell array one first corresponding part of more first data with
And one second corresponding part of more second data；One first sensing amplifier, this is coupled to via the plurality of first bit line
First memory cell array, and amplify the first corresponding part of more first data；And one second sensing amplifier, warp
Second memory cell array is coupled to by the plurality of second bit line, and amplifies the second corresponding portion of more second data
Part.
In addition, the present invention provides a kind of method by reading data in a storage arrangement, comprise the following steps：There is provided one
First memory cell array, wherein first memory cell array include multiple first word-lines and multiple first bit lines, and more
The first data of pen are stored in first memory cell array；One second memory cell array is provided, wherein second storage
Cell array includes multiple second word-lines and multiple second bit lines, second memory cell array and the first memory cell battle array
Row separation, and more the second data are stored in second memory cell array；In a same time or in an overlapping time
One of middle the plurality of first word-line of selection and one of the plurality of second word-line；Alternately select first storage single
One first address of element array and one second address of second memory cell array, with from first memory cell array and should
The one first corresponding part and more second data of more first data are alternately read in second memory cell array
One second corresponding part；And amplify the first corresponding part of more first data and being somebody's turn to do for more second data
Second corresponding part.
The advantageous effects of the present invention are：It by the present invention, can obtain the reading speed of legacy memory devices
Significantly increase, provide while the reading speed for solving the problems, such as its legacy memory devices is restricted and read faster
Speed.
Brief description of the drawings
Fig. 1 is the schematic diagram for showing traditional storage arrangement；
Fig. 2 is the schematic diagram of storage arrangement of the display according to one embodiment of the invention；
Fig. 3 A are first memory cell array and second memory cell array of the display according to one embodiment of the invention
Schematic diagram；
Fig. 3 B are first memory cell array and second memory cell battle array of the display according to another embodiment of the present invention
The schematic diagram of row；
Fig. 4 A are the signal waveforms of storage arrangement of the display according to one embodiment of the invention；
Fig. 4 B are the signal waveforms of storage arrangement of the display according to another embodiment of the present invention；
Fig. 5 is the flow of method by storage arrangement read data of the display according to one embodiment of the invention
Figure；
Fig. 6 A are first memory cell array and second memory cell array of the display according to one embodiment of the invention
Schematic diagram；And
Fig. 6 B are first memory cell array and second memory cell battle array of the display according to another embodiment of the present invention
The schematic diagram of row.
Reference
100th, 200~storage arrangement；
110th, 210,220~memory cell array；
111st, 112,211,212,221,222~word-line；
160th, 260,270~sensing amplifier；
215th, 216,225,226~bit line；
250~control logic circuit；
280~multiplexing data device；
290~displacement buffer；
CLK~clock pulse signal；
The corresponding part of S1, S2~data；
SA1, SA2,410-1,410-2 ..., 410-7~address；
SE1, SE2~sensing enable signal；
SIN~input signal；
SOUT~output data；
T1, T2~sensing time.
Embodiment
Fig. 2 is the schematic diagram for showing the storage arrangement 200 according to one embodiment of the invention.Storage arrangement 200
Can be a NOR flash memory, but not limited to this.As shown in Fig. 2 storage arrangement 200 includes：One first memory cell battle array
Row 210, one second memory cell array 220, a control logic circuit 250, one first sensing amplifier 260, one second sensing
Amplifier 270, a multiplexing data device 280, and a displacement buffer 290.
First memory cell array 210 is separated with the second memory cell array 220.More the first data (such as：Bit
Group) it is stored in the first memory cell array 210, and more the second data (such as：Bit group) it is stored in the second storage
In cell array 220.More first data are combined as complete continuous data with more second data.However, one
In a little embodiments, it is stored in 210 more first data in the first memory cell array and is stored in the second memory cell
More second data in array 220 are all discrete date.First memory cell array 210 includes a plurality of first word-line
211st, 212 and a plurality of first bit line 215,216.First sensing amplifier 260 is to be coupled to first via the plurality of first bit line
Memory cell array 210.Second memory cell array 220 also includes a plurality of second word-line 221,222 and a plurality of second bit line
225、226.Second sensing amplifier 270 is to be coupled to the second memory cell array 220 via the plurality of second bit line.Read one
During taking, foregoing word-line and bit line are the address for selecting any memory cell array.In order to simplify accompanying drawing, not
All word-lines and bit line are all shown in Fig. 2.It is to be understood that each memory cell array all may include in the present embodiment
More word-lines and bit line.
Control logic circuit 250 is to be used to read more first data, Yi Jicong from the first memory cell array 210
More second data are read in second memory cell array 220.In certain embodiments, control logic circuit 250 receives one
Input signal SIN, it indicates a starting address of any memory cell array, and control logic circuit 250 is again from the start bit
Location starts to perform a reading program.During the reading program, control logic circuit 250 can allow in a same time or in one
One of the plurality of first word-line and one of the plurality of second word-line are selected in overlapping time.For example, first
First word-line 211 of memory cell array 210 and the second word-line 221 of the second memory cell array 220 can be in the same as the moment
Between in be chosen.Because the first memory cell array 210 is separated with the second memory cell array 220, first word-line
Selection be separate with the selection of another the second word-line, and sensing amplifier 260,270 can be differentiated unambiguously
Read data.In the preferred embodiment, control logic circuit 250 is alternately select the first memory cell array 210 one
One address SA1 and the second memory cell array 220 one second address SA2, to be deposited from the first memory cell array 210 and second
The one first corresponding part S1 and more second data of more first data are alternately read in storage unit array 220
One second corresponding part S2.It must be noted that each corresponding part all may include one or more pen datas.Next, the first sense
Amplifier 260 amplifies the corresponding part S1 of first read, and the second sensing amplifier 270 amplifies the second correspondence read
Part S2.Multiplexing data device 280 is coupled to the first sensing amplifier 260 and the second sensing amplifier 270.Multiplexing data device
280 be optionally to transmit the first corresponding part S1 of amplification and the second corresponding part S2 of amplification to displacement buffer 290.Position
Move buffer 290 and produce more output data SOUT in order further according to the first corresponding corresponding part S2 of part S1 and second.
In more detail, control logic circuit 250 more receives a clock pulse signal CLK.Connect in control logic circuit 250
After receiving the input signal SIN for indicating the starting address, control logic circuit 250 transmits sensing enable signal SE1, SE2
To start the reading program.The detailed operating process of storage arrangement 200 will explain in the following example.
Fig. 3 A are to show the first memory cell array 210 and the second memory cell battle array according to one embodiment of the invention
The schematic diagram of row 220.As shown in Figure 3A, more first data being stored in the first memory cell array 210 include not connecting
Continuous bit group 0,2,4,6, and more second data being stored in the second memory cell array 220 include discontinuous position
Tuple 1,3,5,7.Each tuple all can be considered a pen data.The combination of more first data and more second data can
Partial data is formed, it includes continuous bit group 0 to 7.In order to simplify accompanying drawing, Fig. 3 A do not show all bit groups, but must
It will be understood that each memory cell array can all store more bit groups.
Fig. 4 A are the signal waveforms for showing the storage arrangement 200 according to one embodiment of the invention.Please join in the lump
Examine Fig. 2, Fig. 3 A, and Fig. 4 A.If after having been received by input signal SIN, before output data SOUT is produced, it is necessary to first expend several
Individual empty cycle (Dummy Cycles) is to initialize a reading program.Address 410-0 to 410-7 in Fig. 4 A (does not show whole
Address) it is the bit group 0 to 7 being respectively corresponding in Fig. 3 A.As shown in Figure 4 A, during the reading program, control logic circuit
250 be alternately select the first memory cell array 210 the first address SA1 (such as：Address 410-0,410-2,410-4,
One of 410-6) and the second memory cell array 220 the second address SA2 (such as：Address 410-1,410-3,410-5,
One of 410-7), alternately to read this more from the first memory cell array 210 and the second memory cell array 220
One data the first corresponding part S1 (such as：Bit group 0,2,4, one of 6) and more second data the second correspondence
Part S2 (such as：Bit group 1,3,5, one of 7).Even if more first data of storage and this more second numbers of storage
According to being all discontinuous, but output data SOUT can be complete and continuous data.In the present embodiment, whenever the first address SA1
(such as：Address 410-2) when being chosen, the first corresponding part S1 of reading (such as：Bit group 2) data bulk be 1, it is and every
When the second address SA2 (such as：Address 410-3) when being chosen, the second corresponding part S2 of reading (such as：Bit group 3) number
Data bulk is also 1.For example, in figure 3 a, if selection one of the first word-line 211, more first data (example
Such as：Bit group 2) it will be read；And if select one of the second word-line 221, more second data (such as：Bit group
3) will be read, wherein the first word-line 211 and the second word-line 221 can be chosen in a same time or in an overlapping time
Select.In the present embodiment, the first address SA1 and the second address SA2 is all every by increasing by 2 two clock cycles.One
Sensing time T1 be used to reading the first corresponding part S1 (such as：Bit group 2) or for reading the second corresponding part S2 (examples
Such as：Bit group 3), during the initialization procedure in addition to, the maximum of sensing time T1 is two clock cycles.Compare
Under, the maximum of a sensing time of the legacy memory devices 100 shown in Fig. 1 is a clock cycle.Therefore,
2nd, the embodiment shown in 3A, 4A figure can provide faster reading speed, and it is about twice of traditional reading speed.
Fig. 3 B are to show the first memory cell array 210 and the second memory cell according to another embodiment of the present invention
The schematic diagram of array 220.As shown in Figure 3 B, more first data being stored in the first memory cell array 210 are included not
Continuous bit group 0,1,4,5, and more second data being stored in the second memory cell array 220 are including discontinuous
Bit group 2,3,6,7.Each tuple all can be considered a pen data.The combination of more first data and more second data
Partial data can be formed, it includes continuous bit group 0 to 7.In order to simplify accompanying drawing, Fig. 3 B do not show all bit groups, but
It is to be understood that each memory cell array can all store more bit groups.Fig. 3 B are similar to Fig. 3 A, and both difference exists
In, in Fig. 3 B, wantonly two of the storage of each memory cell array neighbouring bit groups (such as：Bit group 0,1) can be continuous
Data.This design method can will further accelerate the reading speed of storage arrangement 200.
Fig. 4 B are the signal waveforms for showing the storage arrangement 200 according to another embodiment of the present invention.Please in the lump
With reference to figure 2, Fig. 3 B, and Fig. 4 B.If after having been received by input signal SIN, before output data SOUT is produced, it is necessary to first expend
Several empty cycles are to initialize a reading program.Address 410-0 to 410-7 (not showing whole address) in Fig. 4 B is right respectively
Should be to the bit group 0 to 7 in Fig. 3 B.As shown in Figure 4 B, during the reading program, control logic circuit 250 is alternately to select
Select the first memory cell array 210 the first address SA1 (such as：One of address 410-0,410-4) and the second memory cell
Array 220 the second address SA2 (such as：One of address 410-2,410-6), with from the first memory cell array 210 and
Alternately read in two memory cell arrays 220 more first data the first corresponding part S1 (such as：Bit group 0,1, or
Be bit group 4,5) and more second data the second corresponding part S2 (such as：Bit group 2,3, or bit group 6,7).
Even if more first data of storage and more second data of storage are all discontinuous, but output data SOUT can be
Whole and continuous data.In the present embodiment, whenever the first address SA1 (such as：Address 410-4) when being chosen, the of reading
One corresponding part S1 (such as：Bit group 4, data bulk 5) are 2, and whenever the second address SA2 (such as：Address 410-6) quilt
During selection, the second corresponding part S2 of reading (such as：Bit group 6, data bulk 7) are also 2.For example, in figure 3b,
If the first word-line 212 of selection, more first data it is continuous the two (such as：Bit group 4,5) it will be read together；And
If the second word-line 222 of selection, more second data it is continuous the two (such as：Bit group 6,7) it will be read together, its
In the first word-line 212 and the second word-line 222 can be chosen in a same time or in an overlapping time.In the present embodiment
In, the first address SA1 and the second address SA2 are all that every process increases by 4 four clock cycles.One sensing time T2 is to use
In read the first corresponding part S1 (such as：Bit group 4,5) or for read the second corresponding part S2 (such as：Bit group 6,7),
In addition to during the initialization procedure, the maximum of sensing time T2 is four clock cycles.In comparison, shown in Fig. 1
Legacy memory devices 100 one sensing the time maximum be a clock cycle.Therefore, Fig. 2, Fig. 3 B, Fig. 4 B
Shown embodiment can provide faster reading speed, and it is about four times of traditional reading speed.
Fig. 5 is the flow for showing the method by reading data in a storage arrangement according to one embodiment of the invention
Figure.First, in step S510, there is provided one first memory cell array, wherein first memory cell array include multiple first
Word-line and multiple first bit lines, and more the first data are stored in first memory cell array.In step S520, carry
For one second memory cell array, wherein second memory cell array includes multiple second word-lines and multiple second bit lines,
Second memory cell array separates with first memory cell array, and more the second data are stored in the second storage list
In element array.In step S530, in a same time or select in an overlapping time one of the plurality of first word-line with
And one of the plurality of second word-line.In step S540, one first address of first memory cell array is alternately selected
With one second address of second memory cell array, with from first memory cell array and second memory cell array
Alternately read one first corresponding part of more first data and one second corresponding part of more second data.Most
Afterwards, in step S550, the first corresponding part and the second couple of more second data of more first data are amplified
Should part.It is worth noting that, above method step all need not be performed sequentially.Fig. 2, Fig. 3 A, Fig. 3 B, Fig. 4 A, Fig. 4 B are related
Embodiment, its all detail characteristic can be applied in the method shown in Fig. 5.
Although described above, in each memory cell array, each word-line is only corresponded to two bit groups, the present invention
It is not limited to this.Fig. 6 A are to show the first memory cell array 210 and the second storage list according to one embodiment of the invention
The schematic diagram of element array 220.As shown in Figure 6A, in each memory cell array, each word-line can be corresponded to four bit groups,
And Fig. 6 A design method can be similar to Fig. 4 A embodiment generation signal waveform.Fig. 6 B are displays according to another reality of the present invention
Apply the schematic diagram of the first memory cell array 210 and the second memory cell array 220 described in example.As shown in Figure 6B, respectively depositing
In storage unit array, each word-line can be corresponded to four bit groups, and Fig. 6 B design method can produce with Fig. 4 B embodiment
Raw similar signal waveform.It is worth noting that, the present invention can more be applied to various various memory cell arrays, for example, its
Each word-line is corresponding to 2,4,8,16,32,64,128,256, the memory cell array of even more bit groups.
Ordinal number in this specification and claim, such as " first ", " second ", " the 3rd " etc., each other
Between not precedence relationship sequentially, it is only used for sign and distinguishes two different elements with same name.
Though the present invention is disclosed above with preferred embodiment, so it is not limited to the scope of the present invention, any this area
Person skilled, the claim of the present invention is not being departed from, when can do a little change and retouching, therefore the right of the present invention
It is required that it is defined when being defined depending on above-mentioned claims.
Claims (18)
1. a kind of storage arrangement, it is characterised in that the storage arrangement includes：
One first memory cell array, including multiple first word-lines and multiple first bit lines, wherein more the first data are storages
It is stored in first memory cell array；
One second memory cell array, separated with first memory cell array, and including multiple second word-lines and multiple
Second bit line, wherein more the second data are stored in second memory cell array；
One control logic circuit, it is allowed to select in a same time or in an overlapping time the one of the multiple first word-line
One of person and the multiple second word-line, and alternately select one first address of first memory cell array
With one second address of second memory cell array, with from first memory cell array and second memory cell
One first that more first data are alternately read in array corresponds to the one second of part and more second data
Corresponding part；
One first sensing amplifier, first memory cell array is coupled to via the multiple first bit line, and amplifies institute
State the described first corresponding part of more the first data；And
One second sensing amplifier, second memory cell array is coupled to via the multiple second bit line, and amplifies institute
State the described second corresponding part of more the second data；
Wherein described storage arrangement also includes：
One multiplexing data device；And
One displacement buffer, wherein the multiplexing data device is coupled to first sensing amplifier and second sensing is put
Big device, the multiplexing data device optionally transmits the described first corresponding part and the described second corresponding part is temporary to the displacement
Storage, and the displacement buffer be produced in order according to the described first corresponding part and the described second corresponding part it is multiple defeated
Go out data.
2. storage arrangement according to claim 1, it is characterised in that first address and second address are all
Often increase by 2 by two clock cycles.
3. storage arrangement according to claim 1, it is characterised in that the sensing time is to be used to read described first pair
Should be partly or for reading the described second corresponding part, and the maximum of the sensing time is two clock cycles.
4. storage arrangement according to claim 1, it is characterised in that when being chosen first address, read
The data bulk of the described first corresponding part be 1, and when being chosen second address, second correspondence of reading
The data bulk of part is 1.
5. storage arrangement according to claim 1, it is characterised in that first address and second address are all
Often increase by 4 by four clock cycles.
6. storage arrangement according to claim 1, it is characterised in that the sensing time is to be used to read described first pair
Should be partly or for reading the described second corresponding part, and the maximum of the sensing time is four clock cycles.
7. storage arrangement according to claim 1, it is characterised in that when being chosen first address, read
The data bulk of the described first corresponding part be 2, and when being chosen second address, second correspondence of reading
The data bulk of part is 2.
8. storage arrangement according to claim 1, it is characterised in that be stored in first memory cell array
More first data and more second data being stored in second memory cell array are all discontinuous
Data.
9. storage arrangement according to claim 1, it is characterised in that more first data and described more second
Data are combined as complete continuous data.
A kind of 10. method by reading data in a storage arrangement, it is characterised in that under the method for reading data includes
Row step：
One first memory cell array is provided, wherein first memory cell array includes multiple first word-lines and multiple the
One bit line, and more the first data are stored in first memory cell array；
One second memory cell array is provided, wherein second memory cell array includes multiple second word-lines and multiple the
Two bit lines, second memory cell array is separated with first memory cell array, and more the second data are stored in
In second memory cell array；
Select in a same time or in an overlapping time one of the multiple first word-line and the multiple second
One of word-line；
Alternately select first memory cell array one first address and second memory cell array one second
Address, alternately to read more first numbers from first memory cell array and second memory cell array
According to one first corresponding part and more second data one second corresponding part；And
Amplify the described first corresponding part of more first data and second correspondence of more second data
Partly；
By a multiplexing data device, optionally transmit more first data described first corresponds to part and described more
The described second corresponding part to a displacement buffer of second data；And
By the displacement buffer, produced in order according to the described first corresponding part and the described second corresponding part multiple defeated
Go out data.
11. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that described first
Address and second address are all every by increasing by 2 two clock cycles.
12. the method according to claim 10 by reading data in a storage arrangement a, it is characterised in that during sensing
Between be to be used to reading the described first corresponding part or for reading the described second corresponding part, and the maximum of the sensing time
For two clock cycles.
13. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that whenever described
When first address is chosen, the data bulk of the described first corresponding part of reading is 1, and whenever second address is chosen
When, the data bulk of the described second corresponding part of reading is 1.
14. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that described first
Address and second address are all every by increasing by 4 four clock cycles.
15. the method according to claim 10 by reading data in a storage arrangement a, it is characterised in that during sensing
Between be to be used to reading the described first corresponding part or for reading the described second corresponding part, and the maximum of the sensing time
For four clock cycles.
16. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that whenever described
When first address is chosen, the data bulk of the described first corresponding part of reading is 2, and whenever second address is chosen
When, the data bulk of the described second corresponding part of reading is 2.
17. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that be stored in institute
State more first data in the first memory cell array and be stored in described in second memory cell array
More the second data are all discrete date.
18. the method according to claim 10 by reading data in a storage arrangement, it is characterised in that described more
First data and more second data are combined as complete continuous data.
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| US7681005B1 (en) * | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
| WO2002035546A1 (en) * | 2000-10-27 | 2002-05-02 | Thomson Licensing S.A. | Method and apparatus for preliminarily erasing parts of a bitstream recorded on a storage medium, and corresponding storage medium |
| US20090187701A1 (en) * | 2008-01-22 | 2009-07-23 | Jin-Ki Kim | Nand flash memory access with relaxed timing constraints |
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