CN104112066A - Epilepsy state closed-loop control experiment platform based on FPGA - Google Patents
Epilepsy state closed-loop control experiment platform based on FPGA Download PDFInfo
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Abstract
The invention provides an epilepsy state closed-loop control experiment platform based on an FPGA. The FPGA serves as a lower computer of the experiment platform, and discharging waveform observation and parameter setting are carried out with the help of an upper computer interface compiled through VB. An epilepsy nerve cluster mathematic model is achieved through the FPGA, discharge mode control of an epilepsy nerve cluster network is achieved by means of closed-loop feedback control, and an upper computer is used for conducting parameter adjustment and discharging waveform observation. The method has the advantages that modeling for a complicated epilepsy neuron network is achieved through the experiment platform serving as non-animal experimenting of a biological neural network and based on the high-speed calculation FPGA neuron network, and the time scale is consistent with that of real biological neurons. The visualization research platform more close to a real neural network is provided for researching a discharge mechanism of neuron clusters of the epileptic disease, epilepsy nerve cluster network closed-loop control under the action of an electric field and the like, and has great practical value for epileptic disease treatment research.
Description
Technical field
The present invention relates to biomedical engineering technology, particularly a kind of epilepsy closed-loop control FPGA experiment porch based on neural cluster model.
Background technology
Epilepsy is because the abnormal synchronous over-discharge can of brain cell causes the not normal a kind of the nervous system disease of temporary central functions, up to the present also there is no thoroughly effectively methods for the treatment of.This impels us to go to explore the method for new treatment epilepsy.A large amount of researchs show, the propagation of epileptic attack comes from or through hippocampal tissue, and hippocampus is that sacred disease epilepsy produces and the important area of outbreak.Because electro photoluminescence has dirigibility with respect to clinical operation treatment epilepsy, the characteristics such as reversibility and less intrusion, have become a kind of important method of eliminating epileptic attack.Researcher tests to weaken or eliminate the outbreak of epilepsy by different electrical field stimulations, as DC electric field, low frequency and the pulse of high frequency superthreshold etc.Its parameter and agreement that above-mentioned these research moderate stimulations are open loops still depend critically upon experience adjustments.Due to height scrambling and the intermittence of epileptic attack, rely on the parameter of experience adjustments and agreement effect possibility undesirable.By hippocampal slices and the experiment of clinical close-loop feedback are confirmed, to compare with open loop control, the state that closed-loop control can moment tracker, optimizes whole outbreak control procedure, comprises that result for the treatment of, spinoff minimize, minimum energy losses etc.Depend on the accurate measurement of system state in the effect of close-loop control scheme moderate stimulation.
Brain wave (electroencephalogram, EEG) conventionally can record and comprise abnormal high amplitude and rhythmical epilepsy shape spike in the time that epilepsy shows effect.Neural cluster model does not need single neuron to carry out modeling, and its modeling process, for the neural cluster overall permanence of specific cells composition, only needs one or two state variable can describe whole neural group's mean activity.In the epileptic attack intermittent phase, in the transfer process of quick outbreak, the dynamics of the real EEG electric wave signal that the neural cluster model of hippocampus can simulated experiment records, for research treatment epileptic condition provides new thinking.Neural cluster model after coupling forms neural cluster network model, regulating networks connect parameter can produce different discharge waveforms, as produced the spike of epileptic attack under certain parameter, and then can study the incorgruous impact on epileptic attack of local function.
The core concept of iterative learning control is " skill comes from practice ", any task with repeat property, according to front once operation observation, in the upper once chance of improving tasks carrying performance that all exists in service.Iterative learning method is divided into open loop and two kinds of algorithms of closed loop iterative learning at present, wherein open loop Iterative Algorithm has only utilized the information that system was last time moved, closed loop iterative learning has improved control performance under the condition of utilizing the current operation information of system, given up the information data that system was last time moved simultaneously, therefore on the whole, the performance of closed loop iterative learning control is better than Open-loop iterative learning control.This patent uses PI type Iterative Learning Control Algorithm, the iterative learning control law of closed loop PI type is basic Iterative Algorithm form, its control inputs of the k+1 time is the control inputs of the k time and the PI correction term sum of the k+1 time output error, experimental result shows, the method can be in the control of epileptic condition.
Simultaneously, under PI type iterative learning control thinking, relatively control action is put on to the control result and control signal on different neural clusters, consider and control the validity of epilepsy shape spike and control the factors such as required control energy size, optimum control scheme is proposed, definite theoretical foundation that provides of stimulation sites and quantity of stimulus during further for electronic stimulation epilepsy.
In the last few years, field programmable gate array (Field Programmable Gate Array, FPGA) technology obtained important application in the computational neuroscience field taking biological nervous system as object gradually.In the implementation method of hardware, than extensive Analogous Integrated Electronic Circuits very flexible, the shortcomings such as the construction cycle is long, FPGA has the feature of concurrent operation, have that computing velocity is fast, density is high, volume is little concurrently simultaneously, flexible in programming, can repeated configuration, the advantage such as easy, the low cost of amendment parameter, low-power consumption, high reliability.Neuron based on FPGA and the calculating of neuroid and specificity analysis, can realize in actual time and moving under yardstick, speed is fast, operation efficiency is high, integrated level is high, therefore be convenient to be applied in the aspect such as characteristic research and sacred disease treatment of bionics, intelligent system, neuron and network thereof, thereby realize significant for the hardware of the epilepsy closed-loop control based on neural cluster model.
Also in foundation phase, therefore still there is following shortcoming in existing technology: the special epilepsy control experiment porch that there is no the perfect in shape and function based on FPGA; The simulation hardware neural network model that uses FPGA to realize is relatively simple for structure, and precision is not high; Man-machine interface is not yet perfect, cannot carry out real-time control operation and data analysis, therefore more difficult to the Operations Analyst of FPGA hardware neuroid.
Summary of the invention
For the deficiency existing in above-mentioned technology, the object of this invention is to provide a kind of epilepsy state closed-loop control FPGA experiment porch based on neural cluster model, the thought structure control signal of proportion of utilization integration control and Iterative Algorithm, and realize the control of class epileptic spike by its structure control signal, the spike in output waveform is eliminated.
For achieving the above object, the technical solution used in the present invention is to provide a kind of epilepsy state closed-loop control FPGA experiment porch based on neural cluster model, wherein: this experiment porch includes interconnective fpga chip and host computer, the neural cluster network model of epilepsy state closed-loop control and PI type iterative learning controller adopt VHDL language programming, and be integrated in fpga chip, host computer is responsible for the upper computer software interface of graphic programming and is carried out communication with fpga chip;
The neural cluster network model of described epilepsy state closed-loop control adopts Euler method discretize, being programmed and compiled by VHDL language downloads in fpga chip, and the signal of upper computer software interface input produces neural cluster film potential by the calculating of the neural cluster network model of epilepsy state closed-loop control and PI type iterative learning controller and outputs in host computer and process; The neural cluster model of the epilepsy intercoupling in the neural cluster network model of epilepsy state closed-loop control comprises excitability centrum cellular neural unit, excitability astrocyte neuron, three kinds of neuron models of inhibitory interneuron of intercoupling and connecting, between described excitability centrum cellular neural unit and inhibitory interneuron neuron, is of coupled connections by interaction constant C1, constant C2; The neural cluster network model of described epilepsy state closed-loop control also includes interconnective normal neural cluster network pipeline data model module, the neural cluster pipeline data of epilepsy model module, accepts to be stored in the noise signal of the initial value signal in initial value module, the PI type iterative learning control signal producing by PI type iterative learning controller, the stiffness of coupling signal of being inputted by upper computer software interface, excitatory synapse gain signal and the generation of noise generation module;
Described PI type iterative learning controller is realized by VHDL language programming, compiling downloads in fpga chip, the amendment of controller parameter is realized at upper computer software interface, via data input bus (DIB), scale parameter signal, integral parameter signal are transferred to and in memory module, carry out data storage, be input to again in PI type iterative learning controller, configure the PI type iterative learning control signal of PI type iterative learning controller operation generation waveform, amplitude, pulsewidth and frequency characteristic; PI type iterative learning control signal is transferred in the neural cluster network pipeline data of epilepsy model as external signal, and makes PI type iterative learning control signal between the neural cluster of difference, realize switching by data selector;
Described upper computer software interface is connected and realizes data communication with fpga chip by USB interface, upper computer software interface receives the data that produced by the neural cluster network model of epilepsy state closed-loop control that USB interface is transmitted via data-out bus from fpga chip, the set parameter in upper computer software interface is inputted data by USB interface in fpga chip via data input bus (DIB), and the neural cluster network model of epilepsy state closed-loop control and PI type iterative learning controller are carried out to parameter configuration.
The invention has the beneficial effects as follows that this Simulation Experimental Platform realized the modeling of the neural cluster network of complicated epileptics epilepsy, design and had visual and man-machine interface operability concurrently, improve dirigibility and the operability of system, can be to carrying out emulation with biological neuron mathematical model in time scale; Meanwhile, this experiment porch is the discharge mechanism of research epilepsy state disease, and the neural cluster of PI type iterative learning control epilepsy state provides the visualized experiment platform in yardstick actual time, and the research of epileptic condition treatment is had to important practical value.The FPGA neuroid emulation of calculating based on high-speed parallel is a kind of without zooperal method, and the applied research of its experiment porch worldwide belongs to the sciemtifec and technical sphere in a forward position.The proposition of this research and innovation the closed-loop control experiment porch of the neural cluster network of epilepsy state, it has following some advantage: 1, designed hardware simulation model can keep and the consistance of true biological neuron in time scale, its chips maximum operation frequency is 200MHz, concurrent operation ensures that film potential output frequency is within 1 millisecond, meet the requirement of true neuron time scale, for the research of epileptic condition provides quicker, portable hardware experiment platform; 2, in this platform, the key parameter of neural cluster network model, cynapse gain, controller parameter can pass through upper computer software interface configurations, have completed the various characteristics that utilizes computer user's operation interface configuration experimental facilities; 3, in this platform, comprise PI type iterative learning controller, can realize the control for ill epileptic neuron network, by regulating PI type iterative learning controller parameter to realize modulation to optimal control parameter; 4, the waveform of dotted state and control signal can be put by real-time monitored epilepsy network in upper computer software interface, and can quantitatively record amplitude and the energy of signal, be convenient to the analytical work of follow-up data, for the research for the treatment of epileptic condition provides better visualized experiment research platform.
Brief description of the drawings
Fig. 1 is FPGA hardware experiment platform structural representation of the present invention;
Fig. 2 is the neural cluster pipeline data of epilepsy model;
Fig. 3 is the neural cluster network model of epilepsy state closed-loop control;
Fig. 4 is PI type iterative learning controller module;
Fig. 5 is upper computer software operation interface schematic diagram of the present invention.
In figure:
The 1.FPGA chip 2 PC 3 epileptic state loop control neural cluster network model of 4.PI type iterative learning controller 5 PC software interface 6.USB interface data input bus 8 and 7 data output bus 9 normal nerve cluster network pipeline data model 10 epilepsy nerve cluster network line data model 11 digital PI controller of 12 digital PI controller II 13 digital PI iterative learning controller III 14 module I 15 iterative learning module II 16 iterative learning module III 17 nerve cluster membrane potential signals of 18 noise generating module 19 module 20 coupling matrix of 21 initial strength of excitatory synaptic gain matrix of 22 scale parameter matrix of 23 integral parameter matrix of 24 initial signals in 25.PI type iterative learning control signal 26 signal 27 excitatory coupling strength synaptic gain signal 28 proportional parameters signal 29 integral parameter signal 30 memory module 31 PC software interface button part 32 PC software interface controller configuration section 33 PC software interface nerve cluster configuration parameters Part 34 PC software interface waveform display? Part 35 PC software interface signal characteristics of quantization display part 36 data selector 37 epilepsy Neural cluster model 38 synaptic current signal 39 signal to noise 40 normal nerve cluster membrane potential data of 41 epileptic neural cluster membrane potential data of 42 excitatory pyramidal cells of pipelined data paths 43 excitatory neurons astrocytes neurons pipeline channel 44 inhibitory interneurons of pipelined data paths 45 inhibitory interneurons II pipelined data path 46 random Gauss distribution generator 47 pyramidal cells and intermediate nerve group interaction constant C148. pyramidal cells and intermediate nerve group interaction constant C2
Embodiment
Below in conjunction with accompanying drawing, the closed-loop control FPGA experiment porch structure of the neural cluster network of epilepsy of the present invention is illustrated.
The design philosophy of the closed-loop control FPGA experiment porch of the neural cluster network of epilepsy of the present invention is first on FPGA, to set up the neural cluster network model of epilepsy with polyneural cluster, complicated coupling; Then on FPGA, be independent of neural cluster network modelling PI type iterative learning controller, PI type iterative learning control signal stimulates and imposes on model as foreign current, change the ill discharge mode of the neural cluster network of epilepsy by stimulation, make it produce regular picture; Finally design upper computer software interface, upper computer software interface is by parameters and be transferred to fpga chip, realize the configuration to network coupled structure, excitatory synapse gain, controller parameter and original state, different network coupled structure parameters and excitatory synapse gain can be simulated the flash-over characteristic of normal condition and epilepsy state, also neural cluster network electric discharge dynamic data in fpga chip can be uploaded to host computer, the demonstration of the dynamic waveform that discharges at upper computer software interface simultaneously.This experiment porch is made up of interconnective fpga chip and host computer.Wherein fpga chip is used for realizing the neural cluster network model of epilepsy and PI type iterative learning controller, and host computer is used for designing upper computer software interface and carries out communication with FPGA.
The neural cluster network model of described epilepsy is made up of the neural cluster model intercoupling.The basic thought of the neural cluster model of epilepsy is to make excitability and the interaction of SC faciation to produce Nerve concussion, for the neural cluster model of single epilepsy, in FPGA, adopt Euler method discretize, and adopt pipelining to build, make complicated ordinary differential equation parallel computation.In fact streamline thought be exactly to utilize delay register to make mathematical model be divided into several sub-calculating processes, within each clock period, every sub-calculating process can carry out different neural clusters, not computing in the same time simultaneously, model data intersects in SRAM register and preserves, and transmits with clock.In the neural cluster model of epilepsy, excitability and the interaction of SC faciation, produce Nerve concussion.A cerebral cortex region can be regarded as by excitability astrocyte, three kinds of different neural groups of excitability centrum cell and inhibitory interneuron and form.Network coupled structure can be represented by stiffness of coupling matrix, the stiffness of coupling matrix of network and neural group's excitatory synapse gain matrix is inputted by host computer operation interface, be stored in peripheral hardware register SRAM, synchronization call when calculating, so just, can realize the independent parameter adjustment of neural cluster and the network structure of neural cluster network and change, finally realize network model.Different model parameters can produce different discharge modes, therefore different parameters can be set from operation interface and make model produce respectively the discharge mode of normal and epilepsy.
Epilepsy state closed-loop control FPGA experiment porch based on neural cluster model; neural cluster is set as hysterical; except excitatory synapse gain, its all parameter is taken as standard value; operation epilepsy operating platform; progressively increase the control energy on each neural cluster; to liken the control energy presenting on the neural cluster of normal activity for other two scripts to and want large owing to acting on control energy on hysterical neural cluster, thereby determine hysterical neural cluster in network.Because the object of direct proportional plus integral control now is just determined hysterical neural cluster, not control epilepsy shape spike, therefore its value is very little and working time is very short, the energy that acts on each neural cluster is very little to ensure harmless, after determining hysterical neural cluster, utilize control strategy by control action in this neural cluster, to control epilepsy shape spike, can complete complete diagnosis with control experiment flow.
Described PI type iterative learning controller: iterative learning control is different from most of existing control methods, the control information in the utilization past of its maximum possible builds present control action, and the control information in past comprises tracking error signal and control inputs signal in the past.Iterative learning control realizes by the storer based on study, first utilize the control information in memory stores past, then the control information of storage combines in some way, form the feedforward part of current control action, can, in conjunction with the feedback fraction of current control information, jointly form current control action simultaneously.PI type iterative learning control signal is connected to the input end of controlled neural cluster model as stimulating input, in different neural clusters, apply control signal and can improve epilepsy symptom, therefore need to design a data selector, realize the switching of control signal between the neural cluster of difference, to realize the control to different symptoms.Different control signal control effect differences, therefore can be by regulate scale parameter, the integral parameter of control signal at upper computer software interface, being transferred to FPGA by USB is configured PI type iterative learning controller, carry out the optimization of fast quantification to controlling parameter, make in disease least in power-consumingly controlling, realize the target of optimum control.
Described upper computer software interface: writing of upper computer software interface adopts VB (Visual Basic) software development to realize, performance history is convenient directly perceived, visual, object-oriented, by event driven high-level programming language, finally be presented on and in face of user be and the similar operation interface of real experimental apparatus, can realize real-time data acquisition, waveform shows and data analysis processing.
The PI type iterative learning control FPGA experiment porch of the neural cluster network of epileptic condition of the present invention is made up of interconnective fpga chip 1 and host computer 2.Wherein fpga chip 1 is used for realizing the neural cluster network model 3 of epilepsy state closed-loop control and PI type iterative learning controller 4, and host computer 2 is used for designing upper computer software interface 5 communication with fpga chip 1 by USB interface 6 realizations.Below be illustrated:
The neural cluster network model 3 of epilepsy state closed-loop control
As shown in Figure 1, hardware experiment platform is designed, adopt Altera low-power consumption Cyclone IV EP4CE115F29C7N model fpga chip 1, a digital signal processing developing instrument DSP Builder who utilizes Altera to release carries out graphic programming and then changes into VHDL language, according to the mathematical model of neural cluster, adopt Euler method discretize and build the pipeline data model 9 of normal neural cluster network, the neural cluster network pipeline data of epilepsy path model 10, each neural cluster network pipeline data path model is made up of the neural cluster model 37 of the epilepsy intercoupling.Data input bus (DIB) 7 receives the data that arranged by upper computer software interface 5 in FPGA epilepsy state closed-loop control system, and the critical datas such as neural cluster film potential signal 17 and PI type iterative learning control signal 25 upload to real-time demonstration and the analysis of in host computer, carrying out the neural cluster network dynamic perfromance of epilepsy state by data-out bus 8.As shown in Figure 2, the neural cluster model 37 of epilepsy is mainly by addition, multiplication, look-up table, shift register computing module forms the excitability centrum cellular neural unit pipeline data path 42 intercoupling, excitability astrocyte stream of neuron line data path 43, inhibitory interneuron I pipeline data path 44, inhibitory interneuron II pipeline data path 45, receive the noise signal 39 being produced by random Gaussian distribution generator 46, by the interaction C1 constant 47 of centrum cell and intermediate nerve cluster, C2 constant 48 configures neural cluster characteristic, and according to neural cluster network scale design pipeline depth.The synchronous operation under unified clock of all data paths, and according to the structure of FPGA, realize the conversion of hardware description language by QUARTUS II software.Wherein S (y) is non-linear Sigmoid function, in the model of multiple neural cluster couplings, single neural group can be represented by eight ordinary differential equations, every two-way is a module, and its output simulation EEG signals, finally obtains neural cluster film potential signal 17.
The coupled relation of well setting up between them at neural cluster model buildings builds neural cluster network model later.As shown in Figure 3, change stiffness of coupling signal 26, excitatory synapse gain signal 27 by upper computer software interface 5, can change the structure of network, thereby obtain normal neural cluster and two kinds of networks of ill neural cluster.Normal neural cluster pipeline data model 9, the neural cluster pipeline data of epilepsy model 10 receives the initial value signal 24 that initial value module 19 is stored, the PI type iterative learning control signal 25 that PI type iterative learning controller 4 produces, the excitatory synapse gain signal 27 that excitatory synapse gain matrix 21 is stored carries out calculation process, model 9, the noise signal 39 that the 10 noise generation modules 18 of simultaneously accepting to be realized by lookup table technology produce, through normal neural cluster network pipeline data model 9, the neural cluster film potential signal 17 that the computing of the neural cluster network pipeline data of epilepsy model 10 produces, be input in PI type Iterative Algorithm controller 4, to complete the control based on Iterative Algorithm.Stiffness of coupling matrix 20 is kept in memory module with excitatory synapse gain matrix 21, the neural cluster network pipeline data of epilepsy model 10 is above both except calling in the time calculating, and also needs to call the PI type iterative learning control signal 25 of being exported by PI type iterative learning controller 4.While coupling between computational grid, method is to be multiplied by the input value of stiffness of coupling matrix 20 as network coupling with the cynapse current signal 38 producing in the neural cluster model 37 of epilepsy, so just, can realize the coupled relation of neural cluster network, finally realize the neural cluster network model 2 of epilepsy.
The relevant parameter that memory module 30 is accepted to be inputted by upper computer software interface 5 is stored, in the computation process of streamline, realize synchronization call, it comprises scale parameter matrix 22, integral parameter matrix 23, stiffness of coupling matrix 20 and excitatory synapse gain matrix 21, completed by the sheet external memory technology storer SRAM based on FPGA.
PI type iterative learning controller 4
PI type iterative learning controller 4 is to use pipeline model modelled signal generator in fpga chip 1 to simulate, it comprises three identical controllers, formed by digital PI controller I 11 and iterative learning module I 14, digital PI controller II 12 and iterative learning module II 15, digital PI controller III 13 and iterative learning module III 16 respectively, as shown in Figure 4.Taking wherein one group as example, it receives normal neural cluster film potential data 40 and the neural cluster film potential of epilepsy data 41 are carried out streamline calculating, produce PI type iterative learning control signal 25, be applied to the neural cluster pipeline data of epilepsy model 10 as foreign current, then design a data selector 36 switches between different neural clusters, the size of observing control signal with and different-effect when acting on diverse location, to realize the control for epilepsy symptom; PI type iterative learning controller 4 can receive the scale parameter signal 28, the integral parameter signal 29 that transmit at upper computer software interface 5 simultaneously, optimizes PI type iterative learning controller 4, makes it in reaching control effect, make control signal energy consumption minimum.
Upper computer software interface 5
As shown in Figure 5, in host computer 2, use VB Programming with Pascal Language mode to design upper computer software interface 5.FPGA chip 1 and realize data communication by USB device and upper computer software interface 5, upper computer software interface 5 receives the data that obtained by neural cluster network model 3 computings of epilepsy state closed-loop control and PI type iterative learning controller 4 of transmitting from fpga chip 1, USB interface 6 by USB device; Upper computer software interface 5 parameters are inputted data in fpga chip 1 by USB device, and the neural cluster network model 3 of epilepsy state closed-loop control and PI type iterative learning controller 4 are carried out to parameter configuration.VB be visual, by event driven, OO high-level programming language, it has adopted the GUI system that can simply set up application program, simultaneously can develop again complicated program, can take into account data processing and storage, and ensure that data implement continuous acquisition function.Upper computer software interface 5 design is divided into five parts: the control that upper computer software operation interface button part 31 has been realized for host computer basic operation, comprise control apply, the switching of start/stop state, refresh data, analysis data, help menu and display waveform; Upper computer software operation interface controller configuration section 32 can change control device key parameter; The neural swarm parameter configuration section 33 of upper computer software operation interface can be realized the configuration of neural cluster initial parameter, network structure, cynapse gain parameter; The control signal waveform of putting a waveform and correspondence of different neural groups in neural group network can be realized in upper computer software operation interface waveform display section 34; Energy and the amplitude of corresponding control signal can be realized in upper computer software operation interface characteristics of signals display section 35, is convenient to the quality that quantitatively judgement is controlled.
FPGA experiment porch
Write discrete, epilepsy state closed-loop control nerve cluster network model fixed step size, fixed-point number computing based on module by DSP Builder, then change into hardware description language.Through QUARTUS II software programming complete operation logic and program structure; Compiling, analysis integrated, placement-and-routing, download to operation in fpga chip 1.Upload through USB the neural cluster film potential data 41 of normal neural cluster film potential data 40, epilepsy and the PI type iterative learning control signal 25 that fpga chip 1 computing produces, at the upper computer software interface 5 of VB language compilation, the neural cluster network model characteristics of epilepsy is analyzed and researched.
Claims (5)
1. the epilepsy state closed-loop control FPGA experiment porch based on neural cluster model, it is characterized in that: this experiment porch includes interconnective fpga chip (1) and host computer (2), the neural cluster network model of epilepsy state closed-loop control (3) and PI type iterative learning controller (4) adopt VHDL language programming, and be integrated in fpga chip (1), host computer (2) is responsible for the upper computer software interface (5) of graphic programming and is carried out communication with fpga chip (1);
The neural cluster network model of described epilepsy state closed-loop control (3) adopts Euler method discretize, being programmed and compiled by VHDL language downloads in fpga chip (1), and the signal of upper computer software interface (5) input produces neural cluster film potential (17) by the calculating of the neural cluster network model of epilepsy state closed-loop control (3) and PI type iterative learning controller (4) and outputs in host computer (2) and process, the neural cluster model of the epilepsy intercoupling (37) in the neural cluster network model of epilepsy state closed-loop control (3) comprises (44) the three kinds of neuron models of excitability centrum cellular neural unit (42), excitability astrocyte neuron (43), inhibitory interneuron that intercouple and connect, and between described excitability centrum cellular neural unit (42) and inhibitory interneuron neuron (44), is of coupled connections by interaction constant C1 (47), constant C2 (48), the neural cluster network model of described epilepsy state closed-loop control (3) also includes interconnective normal neural cluster network pipeline data model (9) module, neural cluster pipeline data model (10) module of epilepsy, acceptance is stored in the initial value signal (24) in initial value module (19), the PI type iterative learning control signal (25) producing by PI type iterative learning controller (4), by the stiffness of coupling signal (26) of upper computer software interface (5) input, the noise signal (39) that excitatory synapse gain signal (27) and noise generation module (18) produce,
Described PI type iterative learning controller (4) is realized by VHDL language programming, compiling downloads in fpga chip (1), the amendment of controller parameter is realized at upper computer software interface (5), via data input bus (DIB) (7) by scale parameter signal (28), integral parameter signal (29) is transferred in memory module (30) and carries out data storage, be input to again in PI type iterative learning controller (4), configure PI type iterative learning controller (4) operation and produce waveform, amplitude, the PI type iterative learning control signal (25) of pulsewidth and frequency characteristic, PI type iterative learning control signal (25) is transferred in the neural cluster network pipeline data model of epilepsy (10) as external signal, and makes PI type iterative learning control signal (25) between the neural cluster of difference, realize switching by data selector (36),
Described upper computer software interface (5) is connected and realizes data communication with fpga chip (1) by USB interface (6), upper computer software interface (5) receives the data that produced by the neural cluster network model of epilepsy state closed-loop control (3) that USB interface (6) is transmitted via data-out bus (8) from fpga chip (1), the set parameter in upper computer software interface (5) arrives in fpga chip (1) via data input bus (DIB) (7) input data by USB interface (6), the neural cluster network model of epilepsy state closed-loop control (3) and PI type iterative learning controller (4) are carried out to parameter configuration.
2. the epilepsy state closed-loop control FPGA experiment porch based on neural cluster model according to claim 1, it is characterized in that: described PI type iterative learning controller (4) comprises digital PI controller I (11), digital PI controller II (12), digital PI controller III (13) and iterative learning module I (14), iterative learning module II (15), iterative learning module III (16), and accept the scale parameter signal (28) that configured by host computer, integral parameter signal (29) and the normal neural cluster film potential data (40) that produce by the neural cluster network model of epilepsy state closed-loop control (3), the neural cluster film potential data of epilepsy (41), produce PI type iterative learning control signal (25) through calculating, and act on the neural cluster of epilepsy state in the neural cluster network pipeline data model of epilepsy (10) by data selector (36), realize the control to the neural cluster network of epilepsy state.
3. the epilepsy state closed-loop control FPGA experiment porch based on neural cluster model according to claim 1, it is characterized in that: the described neural cluster network pipeline data model of ill epilepsy (10) comprises the multiple neural cluster model intercoupling, each neural cluster model comprises the stream of neuron line data path intercoupling, it is excitability centrum cellular neural unit's pipeline data path (42), excitability astrocyte stream of neuron line data path (43), inhibitory interneuron I pipeline data path (44), inhibitory interneuron II pipeline data path (45), every pipeline data path includes multiplier, totalizer, look-up table and register module, produce the neural cluster film potential data of epilepsy (41) through parallel computation, upload to and in host computer, carry out neural cluster discharge waveform and show and critical data storage operation through USB interface (6) by data-out bus (8), upper computer software interface (5) can arrange stiffness of coupling signal (26), excitatory synapse gain signal (27) size, enter data in the neural cluster network pipeline data model of epilepsy (10) by data input bus (DIB) (7), thereby neural cluster network is configured to normal and epilepsy two states.
4. the epilepsy state closed-loop control FPGA experiment porch based on neural cluster model according to claim 1, it is characterized in that: described initial value module (19) receives the data of being transmitted by upper computer software interface (5) by data input bus (DIB) (7), the neural cluster network model of epilepsy state closed-loop control (3) is carried out to the setting of initial value, and initial value module (19) is inputted different initial parameters by upper computer software interface (5).
5. the epilepsy state closed-loop control FPGA experiment porch based on neural cluster model according to claim 1, it is characterized in that: described memory module (30) comprises stiffness of coupling matrix (20), excitatory synapse gain matrix (21), scale parameter matrix (22), integral parameter matrix (23), and respectively to the stiffness of coupling signal (26) from upper computer software interface (5) input, excitatory synapse gain signal (27), scale parameter signal (28), integral parameter signal (29) is stored, and by stiffness of coupling signal (26), excitatory synapse gain signal (27) storing value is input in the neural cluster network pipeline data model of epilepsy (10) and calculates, by scale parameter signal (28), integral parameter signal (29) is input in PI type iterative learning controller (4) and calculates.
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| CN106407568A (en) * | 2016-10-26 | 2017-02-15 | 天津大学 | A Parkinson-state basal nuclei stimulation real-time simulation platform based on finite element analysis |
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| CN109640810A (en) * | 2016-07-18 | 2019-04-16 | 艾克斯-马赛大学 | Adjust the epileptic method of cause in patient's brain |
| CN111967572A (en) * | 2020-07-10 | 2020-11-20 | 逢亿科技(上海)有限公司 | FPGA-based YOLO V3 and YOLO V3 Tiny network switching method |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070239210A1 (en) * | 2006-04-10 | 2007-10-11 | Imad Libbus | System and method for closed-loop neural stimulation |
| CN102613971A (en) * | 2012-03-30 | 2012-08-01 | 北京品驰医疗设备有限公司 | Electroencephalograph (EEG)-based epilepsy detection and intervention device |
-
2014
- 2014-08-18 CN CN201410310856.9A patent/CN104112066B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070239210A1 (en) * | 2006-04-10 | 2007-10-11 | Imad Libbus | System and method for closed-loop neural stimulation |
| CN102613971A (en) * | 2012-03-30 | 2012-08-01 | 北京品驰医疗设备有限公司 | Electroencephalograph (EEG)-based epilepsy detection and intervention device |
Non-Patent Citations (3)
| Title |
|---|
| J.CHEN ETC: "《Proceedings of the 2011 4th International Symposium on Avanced Control of Industrial Processes》", 26 May 2011 * |
| 刘仙 等: ""神经群模型中癫痫状棘波的闭环控制性能研究"", 《物理学报》 * |
| 张荣华 等: ""神经元网络的FPGA硬件仿真方法"", 《计算机应用研究》 * |
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