CN104103312A

CN104103312A - Writing method of nonvolatile memory unit array

Info

Publication number: CN104103312A
Application number: CN201410344930.9A
Authority: CN
Inventors: 朱金桥
Original assignee: BEIJING MENMA TECHNOLOGY Co Ltd
Current assignee: Shanghai core semiconductor Co., Ltd.
Priority date: 2014-07-21
Filing date: 2014-07-21
Publication date: 2014-10-15

Abstract

The invention discloses a writing method of a nonvolatile memory unit array. An array structure is optimized; when a writing operation is executed, a selected memory unit realizes a purpose of removing electrons in a floating gate through tunnelling effect to lower a threshold value by reasonable voltage configuration; a grid electrode and a drain electrode of the unselected memory unit do not exhibit a voltage difference which is big enough for realizing tunneling so as to guarantee that the threshold value of the memory unit is constant.

Description

A kind of wiring method of nonvolatile storage location array

Invention field

The present invention relates to integrated circuit fields, relate in particular to the wiring method that a kind of nonvolatile storage location array is provided in memory area.

Background technology

In non-volatility memorizer field, there are much dissimilar technique, circuit and structure, because the mechanism of then wearing is easily controlled tunnel area, can effectively reduce failure risk, so in the field that needs high reliability, wipe with data writing more commonly by the mode of wearing then, most typical is electricallyerasable ROM (EEROM) (EEPROM).Its each memory cell comprises two transistors, selects transistor, a floating boom transistor for one, it in Fig. 1, is a typical eeprom memory unit, (a) being schematic diagram, is (b) structural drawing, the voltage of respective terminal while being (c) erasable operation.Memory cell injects in floating boom by tunneling effect or removes electronics, thereby causes the variation of floating boom transistor threshold to realize 0 and 1 difference.

Electricallyerasable ROM (EEROM) (EEPROM) technology is very ripe, but because its each memory cell needs two transistors, and two transistors all need to meet high pressure resistant demand, make device be not easy, along with area is dwindled in technique upgrading, to apply more widely thereby seriously restrict it.

So in current integrated circuit fields, the non-volatility memorizer that a kind of high reliability and area are less still has the very large market demand.

Summary of the invention

In view of the above problems, the object of the invention is to propose a kind of wiring method of nonvolatile storage location array, make each storage unit only need a floating boom transistor.

In Fig. 2, for the memory cell in the present invention, (a) being schematic diagram, is (b) structural drawing, the voltage of respective terminal while being (c) erasable operation.While carrying out erase operation, memory cell grounded drain, source ground, grid meets VPP0, by the tunneling effect between grid and drain electrode, by electronic injection floating boom, the threshold value of memory cell is raise.While carrying out write operation, the drain electrode of memory cell meets VPP1 (writing " 0 ") or VPP2 (one writing), source electrode is for floating empty, grounded-grid, by the tunneling effect between drain electrode and grid, electronics is removed from floating boom, the threshold value of memory cell is declined, the drain-gate voltage that the memory cell that meets VPP1 due to drain electrode meets VPP2 than drain electrode is poor larger, from floating boom, remove more electronics, thereby cause the difference of two kinds of situation memory cell threshold values to realize 0 and 1 difference.In order to ensure that the non-memory cell data of choosing page is not misused, need to, in the time carrying out write operation, the non-grid of choosing memory cell be met to VPP2 simultaneously, ensure enough little drain-to-gate voltage.

Memory cell in this invention physical arrangement with traditional EEPROM in storage tube similar, but this invention has changed structure and the wiring method of array completely, do not revising under the condition of manufacturing process, directly reduce the area that storer need to take, thereby provide a kind of storer solution of high performance-price ratio for industry.

Brief description of the drawings

Fig. 1 is classical electricallyerasable ROM (EEROM) (EEPROM) memory cell and operating voltage;

Fig. 2 is non-volatility memorizer memory cell of the present invention and operating voltage;

Fig. 3 is nonvolatile storage location array of the present invention and operating voltage;

Embodiment

Describe the wiring method of nonvolatile storage location array of the present invention in detail below with reference to accompanying drawing.

Fig. 3 is nonvolatile storage location array of the present invention, (a) is schematic diagram, the voltage of respective terminal while being (b) erasable operation.As shown in Figure 3, (a) in figure, I40 is one and has n bar word line, the memory array of m bit lines, in figure for example: WL<0> is selected word line, even bitlines writes logical zero, and odd bit lines writes logical one.So, in whole array, there are four kinds of memory cells in different voltage environment, as follows:

I30: selected word line, bit line writes logical zero

I31: selected word line, bit line writes logical one

I32: non-selected word line, bit line writes logical zero

I33: non-selected word line, bit line writes logic " 1

In the time of erasable operation, by connecting different voltage in the memory cell respective terminal dissimilar, realize writing of the memory cell data chosen, and the maintenance of non-selected cell data.

While wiping:

The grid of I30, I31 connects VPP0 (representative value 15V), source electrode and grounded drain.By the electric field between grid leak, by electronic injection in floating boom.The threshold value of rising I30 and I31.The grounded-grid of I32, I33, source electrode and grounded drain.Between grid leak, without electric field, I32 and I33 are not operated, therefore its threshold value is constant, internal data is constant.

Write fashionable:

The memory cell I30 of selected word line, the grounded-grid of I31, source electrode floating empty (in fact can source voltage be filled to height by the non-memory cell of choosing).I30 will write logical zero and drain and meet VPP1 (representative value 12V), I31 will write logical one and drain and meet VPP2 (representative value 8V), wherein VPP1 is greater than VPP2, because I30 is poor larger than the drain-gate voltage of I31, the electronics removing from floating boom is also more, (I31 allows to remove a small amount of electronics from floating boom, or do not remove electronics completely), so I30 is lower than the threshold value of I31 after write operation, I30 presents different threshold values from I31, thereby has realized the storage of information.The memory cell I32 of non-selected word line, I33 grid meet VPP2 (representative value 8V), source electrode is floating empty (in fact can source voltage be filled to height by the non-memory cell of choosing), I32 the connect VPP1 identical with I30 that drain, I33 the connect VPP2 identical with I31 that drain, the drain-to-gate voltage of I32 is 4V, the drain-gate voltage of I33 is 0V, and two voltages are all less, cannot produce tunneling effect and can not affect the non-data of choosing in memory cell I32, I33.

While reading:

The grid of memory cell I30, the I31 of selected word line meets VREAD (representative value is 3V), source ground, and drain terminal is connected to outside sensor amplifier.Judge that according to the size of On current storage unit is for " 0 " or " 1 ".

The memory cell I32 of non-selected word line, the grounded-grid of I33, source ground, drain terminal is connected to outside sensor amplifier together with I30, I31.Due to non-all not conductings of memory cell of choosing, Gu Buhui affects correctly reading of data.

The foregoing is only exemplary embodiment of the present invention.Any amendment of having done within spirit of the present invention and improvement, within all should being included in claim protection domain of the present invention.

Claims

1. the wiring method of a nonvolatile storage location array.This memory cell array comprises: many word lines, multiple bit lines, many source electrode lines.The drain electrode of the storage unit of each row in this memory cell array all connects a corresponding bit lines; The control grid of the storage unit of every a line all connects a corresponding word line; The source class of the storage unit of every a line all connects a corresponding source electrode line, allows the source electrode line of many source electrode line interconnection formation less amount in array, and many source electrode lines in permission array all interconnect and form a total source electrode line; The substrate of all storage unit is all connected to ground.

The wiring method of above-mentioned memory array comprises:

In the time carrying out write operation, can only choose a word line simultaneously, the word line ground connection that selected storage unit connects, applies the first positive voltage on the word line at the non-storage unit place of choosing.On the bit line at storage unit place that needs data writing " 1 ", apply the first positive voltage (or floating empty), on the bit line at storage unit place that needs data writing " 0 ", apply the second positive voltage.All source class lines are set to floating empty (or first positive voltage).

2. storage unit as claimed in claim 1 requires the N-type injection zone of drain terminal and floating boom and control gate to have overlapping region, and tunnel oxidation layer THICKNESS CONTROL between overlapping region floating boom and N-type are injected is worn mechanism reliably then in applicable realization.

3. the first positive voltage as claimed in claim 1 is 4V～8V left and right.

4. the second positive voltage as claimed in claim 1 is 8V～12V left and right.

5. as claimed in claim 1 being written into behind data " 0 " or " 1 ", the threshold value of storage unit is all greater than 0V.