CN104092371A - RFID (Radio Frequency Identification) EEPROM (Electrical Erasable Programmable Read Only Memory) charge pump - Google Patents
RFID (Radio Frequency Identification) EEPROM (Electrical Erasable Programmable Read Only Memory) charge pump Download PDFInfo
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Abstract
The invention provides an RFID (Radio Frequency Identification) EEPROM (Electrical Erasable Programmable Read Only Memory) charge pump. The RFID EEPROM charge pump comprises a two-grade charge pump, an electrical level converter and a clock generator, wherein the two-grade charge pump is composed of a first-grade charge pump and a second-grade charge pump; the first-grade charge pump is powered by power supply voltage Vdd of a chip to generate a low-voltage output signal higher than the power supply voltage Vdd; the output end of the first-grade charge pump is connected with the second-grade charge pump; the output end of the clock generator is connected with the first-grade charge pump; the output end of the clock generator is connected with the second-grade charge pump through the electrical level converter; the electrical level converter is connected with the output end of the first-grade charge pump. The RFID EEPROM charge pump provided by the invention adopts the double grades of charge pumps to obtain the voltage needed by EEPROM erasing; a high-voltage clock needed by the second-grade charge pump is obtained through the electrical level converter and the substrate effect is not obvious; a high-voltage signal needed by EEPROM programming can be generated from the relatively low voltage; meanwhile, the consumption of peak current can be reduced to the greatest extent so that the sensitivity and the read-write distance of a label chip are improved.
Description
Technical field
The present invention relates to EEPROM field, relate in particular to the EEPROM charge pump in a kind of RFID of being applied to integrated circuit.
Background technology
Radio frequency identification (Radio Frequency Identification, abbreviation RFID) system comprises RFID reader and one group of RFID label conventionally.RFID reader is completed and is communicated by letter by wireless mode with label, and for transmitting ID and data, these data are all stored on the embedded EEPROM in RFID chip conventionally.RFID label is all passive conventionally, by the radiofrequency field sending from RFID reader, obtains required energy.Due to the retrievable finite energy of RFID label, and along with the distance with RFID reader increases and reduces, so reduce the power consumption of RFID label as far as possible, just become very important, particularly just all the more so for UHF rfid system.Conventionally, under the power that be operated in-20dBm of RFID label is even lower, operating voltage is generally 1V.
RFID label adopts EEPROM storage ID and data conventionally, in EEPROM, thereby is the storage that realizes data bit for 16V high-voltage signal pressure iunjected charge by executing to floating boom.Electric charge is transferred on floating boom by quantum tunneling effect, and after high-voltage signal disappears, electric charge still can retain.This just makes transistor in " ON " state, on the contrary, while there is no electric charge on floating boom in " OFF " state.
Charge pump normally first gives capacitor charging until power supply electrical level, then two terminals of switched capacitor, so that in charging process the electric capacity bottom in ground potential through conversion after in supply power voltage electromotive force, so just make other one end in doubling supply power voltage level.Then electric charge in electric capacity can transfer to next electric capacity, and repeats said process.By a series of like this processing, just can obtain the voltage signal more much higher than input voltage." Dixon " charge pump is a kind of typical charge pump configuration, as shown in Figure 1, for discrete component implementation, diode 1 is used for preventing that electric charge from passing through reverse leakage, and a diphasic clock output 2 provides bidirectional clock signal to be used for switched capacitor in order to pass through the high pressure Vout of the low pressure Vin generation high-pressure side 4 of low-pressure end 5.The major defect of this scheme is the restriction that voltage transfer effect is subject to diode forward voltage.
Fig. 2 is that a kind of Dixon charge pump is for the structure principle chart of integrated circuit, the mode that adopts transistor 2 to connect into diode has substituted the mode of original diode 1, adopted diphasic clock the same as discrete component mode is for driving charge pump, its diphasic clock signal as shown in Figure 3, this circuit is the same with discrete component, owing to being subject to nmos pass transistor threshold voltage V
threstriction, voltage transfer efficiency is not very good.Another one problem is commonly referred to " body effect ", i.e. the transistorized V of CMOS
thvoltage signal is along with the voltage between source electrode and drain electrode increases and increases.Every increase one-level, the efficiency of charge pump is just lower than upper level.This effect is just more obvious when the progression boosting is more.
Fig. 4 is a kind of charge pump circuit that overcomes " body effect ", the grid voltage of each transistor 6 is realized " bootstrapping " by extra transistor, bootstrap transistor has increased the voltage that is applied to main transistor, at this moment just need a kind of non-superimposed four-phase clock circuit, its signal waveforms as shown in Figure 5.Even if adopted the boostrap circuit of this mode, be also difficult to produce the required 16V high pressure of programming from the voltage signal lower than 1.8V.Therefore, present most RFID labels all can only be realized the asymmetric operation of read-write, and this is because read operation needs the voltage signal of 1V left and right conventionally, writes and needs higher voltage, common about 1.5V.This has just caused the asymmetric of read-write operation distance, writes distance only reads distance conventionally half.
Under quiescent conditions, at output voltage, reached maximum and entered after stable state, the current sinking of charge pump depends primarily on load value.The output impedance of charge pump, such as electric current power supply capacity, depends primarily on the frequency of the driving clock of charge pump.Except attempt improving the efficiency of charge pump, do not have too many room for improvement improving aspect charge pump quiescent current consumption.
Yet in the initial charge stage of charge pump, current sinking is than high a lot of under static state.Initial current drain is the emphasis that passive RFID tags chip need to be considered.Passive RFID tags chip obtains energy from the electromagnetic wave of reader transmitting, and incoming signal level may be very low, conventionally need to use radio frequency charge pump to be used for producing sufficiently high operating voltage.Charge pump generally has a lot of levels, causes output resistance very high.In addition, label antenna is all tuned at high Q state conventionally with the input stage of coupling charge pump.All above-mentioned these factors all can limit RFI D input stage the ability that larger electric current is provided.In addition, the decoupling capacitance that increases a larger capacity also can bring many problems, as volume and cost increase etc.So the initial current size of the reduction EEPROM charge pump of maximum possible just becomes very important, the most critical factor that this also becomes restriction tag sensitivity and reads distance.
Summary of the invention
The object of this invention is to provide a kind of EEPROM charge pump for RFID label chip, when reducing required supply power voltage, reduce to greatest extent the consumption of peak current, thereby improve sensitivity and the reading/writing distance of label chip.
The technical scheme that the present invention adopted is for achieving the above object: a kind of RFID EEPROM charge pump, comprise the two-stage charge pump that first order charge pump and second level charge pump form, level translator and clock generator, first order charge pump produces the low-voltage output signal higher than supply power voltage Vdd by chip power supply voltage Vdd power supply, first order charge pump output connects second level charge pump, second level charge pump produces the erasable required voltage Vo2 of EEPROM by the output voltage V o1 power supply of first order charge pump, the output of clock generator connects first order charge pump, the output of clock generator connects second level charge pump by level translator and produces the required high pressure clock of second level charge pump, level translator connects first order electric charge delivery side of pump, level translator is powered by the output voltage V o1 of first order charge pump.
Described clock generator comprise one-level Clock dividers at least, in order to select different fractions frequently device output signal multiplexer and be used for controlling multiplexer to select the counter of different output, frequency divider is connected in series, master clock only connects the input of first order Clock dividers, and the output of the first order is as the input of second level Clock dividers; Multiplexer connects master clock and Clock dividers output at different levels, and counter connects master clock and multiplexer.
Described clock generator is voltage controlled oscillator, increases the frequency of output signal by increasing voltage signal.
Described clock generator output frequency is increased and is produced by the mode of going forward one by one or continuation mode.
Described clock generator is output as diphasic clock signal, non-overlapped diphasic clock signal or four phase clock signals.
Described first order charge pump is low voltage transistor circuit, adopts low pressure intrinsic NMOS transistor.
Described second level charge pump is high voltage transistor circuit, adopts high voltage intrinsic NMOS transistor.
Described first order charge pump and second level charge pump all adopt Dixon charge pump circuit or with the charge pump of body effect compensating circuit.
Described chip power supply voltage Vdd is lower than 1.5V, and the erasable required voltage Vo2 of EEPROM is 16V.
RFID EEPROM charge pump of the present invention, adopt twin-stage charge pump to obtain the erasable required voltage of EEPROM, by level translator, obtain the required high pressure clock of second level charge pump, body effect is not obvious, can be integrated in the RFID chip simultaneously with low voltage transistor (as 1.8V) and high pressure (as 16V) semiconductor processes flow process, can produce the EEPROM required high-voltage signal of programming from low voltage, can also reduce to greatest extent peak-current consumption, thereby improve sensitivity and the reading/writing distance of label chip simultaneously.
Accompanying drawing explanation
Fig. 1 is the Dixon charge pump schematic diagram that discrete component forms.
Fig. 2 is the Dixon charge pump schematic diagram in integrated circuit.
Fig. 3 is the diphasic clock figure of the Dixon charge pump in integrated circuit.
Fig. 4 is with the charge pump schematic diagram of body effect compensating circuit.
Fig. 5 is with four phase clock figure of the charge pump of body effect compensating circuit.
Fig. 6 is RFID EEPROM charge pump schematic diagram of the present invention.
Fig. 7 is the input and output signal oscillogram of level translator of the present invention.
Fig. 8 is that the present invention is for driving the clock generator schematic diagram of charge pump.
Fig. 9 is the output waveform figure of clock generator of the present invention.
Figure 10 is the current drain figure of charge pump.
The output voltage waveform of Figure 11 charge pump.
In figure: 1, diode, 2, diphasic clock output, 3, electric capacity, 4, high-voltage output end, 5, low pressure input, 6, transistor.
Embodiment
Charge pump principle for RFID chip of the present invention as shown in Figure 6, comprises the two-stage charge pump that a first order charge pump and second level charge pump form, a level translator and a clock generator.The present invention can be integrated in the RFID chip simultaneously with low voltage transistor (as 1.8V) and high pressure (as 16V) semiconductor processes flow process.
The first order of twin-stage charge pump is powered by chip power supply voltage Vdd, in order to produce the Voltage-output signal higher than Vdd, but simultaneously also enough low, thus this charge pump can all adopt low voltage transistor circuit to realize.First order charge pump output connects second level charge pump, and second level charge pump produces the erasable required voltage Vo2 of EEPROM by the output voltage V o1 power supply of first order charge pump, adopts high voltage transistor design.Chip power supply voltage Vdd can be lower than 1.5V, is minimumly low to moderate 1V or lower.The final output voltage of charge pump, also can be according to the required suitable variation of EEPROM technology adopting up to 16V.Two-stage charge pump can adopt Dixon charge pump circuit or with the charge pump of body effect compensating circuit, wherein one or two also can adopt the charge pump of other form.
Clock generator can be driven by outside or internal master clock crystal oscillator, comprise one or more levels Clock dividers, in order to select different fractions frequently device output signal multiplexer and be used for controlling multiplexer to select the counter of different output, different frequency dividers can connect in serial connection mode, master clock is only connected to the input of first order Clock dividers like this, the output of the first order is as the input of the second level, and by that analogy, the output of next stage frequency divider is half of upper level clock frequency.Clock generator also can have a counter in order to record the different time periods, and counter can be used for controlling multiplexer to select different output.Such as, the counter first stage is selected the output of last frequency divider, and second stage is selected the output of penultimate frequency divider, the like, along with per a period of time increases, the output of multiplexer just increases or doubles like this.
Can also be by other means in order to produce the required cumulative clock frequency of charge pump.Crystal oscillator can also be a voltage controlled oscillator, by increasing voltage signal in order to increase the frequency of output signal.
The output of clock generator can be diphasic clock, and one of them clock phase is another inverted phase, can be also non-overlapped diphasic clock, and namely two clock phases can not be high simultaneously.Output signal can also be four phase clocks, or other form of above-mentioned twin-stage charge pump needs.Clock generator can all be realized by the low voltage logic circuit identical with chip power supply voltage Vdd.The output of clock generator can be directly connected to first order charge pump.The output of clock generator can produce the required high pressure clock of second level charge pump by level translator, and this level translator can have the output power supply of first order charge pump.Clock generator output frequency is increased and is produced by the mode of going forward one by one or continuation mode.Clock generator is output as diphasic clock signal, non-overlapped diphasic clock signal or four phase clock signals.
Specific embodiment:
RFID EEPROM charge pump of the present invention can be used for having low pressure (1.8V), middle pressure (3.3V) and the transistorized situation of high pressure (16V), RFID EEPROM charge pump to comprise a clock generator, low pressure first charge pump stage, high pressure second charge pump stage and a level translator in production process of semiconductor.
The input voltage of first order charge pump is Vdd, is 1V in typical case, can be also low-voltage more.The low pressure diphasic clock that this grade generated by clock generator drives.The output of first order charge pump is as the input Vo1 of second level charge pump, the about 3.3V of voltage.Vo1 returns level translator power supply, and its input is two low-voltage diphasic clock φ
l1and φ
l2, output is two middle pressure diphasic clock φs consistent with Vo1
h1and φ
h2, as shown in Figure 7.φ
h1and φ
h2be used as the clock signal of second level charge pump, the output signal Vo2 of second level charge pump can reach 16V.
First order charge pump only needs to produce about 3.3V voltage, only needs 4 grades of booster circuits, and body effect is not obvious, can adopt common Dixon charge pump construction shown in Fig. 2, also can use low pressure (1.8V) intrinsic NMOS transistor to use as diode.
Second level charge pump need to boost to 16V from 3.3V, and because clock at the corresponding levels adopts 3.3V, so only need 6 grades of booster circuits, same body effect is also not obvious.Can adopt the common Dixon charge pump construction shown in Fig. 1, can adopt high pressure (16 V) intrinsic NMOS transistor to be used as diode and use.
Fig. 8 is the schematic diagram of clock generator, clock generator comprises two-stage frequency divider, be first order Clock dividers and second level Clock dividers, a multiplexer and a counter, the input clock signal of clock generator is produced by inside or external crystal-controlled oscillation, each grade of frequency divider all removes 2 by clock signal frequency, so produce output waveform figure a as shown in Figure 9, output waveform figure b, output waveform figure c, counter is used for to three time period countings, in first period, multiplexer selects oscillogram c as output, second time period, multiplexer selects oscillogram b as output, last time period, multiplexer selects oscillogram a as output, so final output waveform d is exactly the frequency increasing progressively step by step.Such as, when clock input is 1MHz, the output of the first period is exactly 250KHz, and the output of the second time period is 500KHz, and in the remaining period, output is exactly 1MHz.
Figure 10 has provided the circuitry consumes comparison diagram of charge pump.Only adopt the charge pump current of single clock frequency to consume e, actual current of the present invention consumes f and has lower peak value.Figure 11 has provided actual output voltage oscillogram g in single-frequency clock output voltage waveforms h comparison diagram.Diagram waveform shows that output voltage is almost linear, and the design of single clock frequency signal will be logarithmic form increase.As can be seen here, EEPROM charge pump of the present invention, when reducing required supply power voltage, reduces the consumption of peak current to greatest extent.
The present invention is described by embodiment, and those skilled in the art know, without departing from the spirit and scope of the present invention, can carry out various changes or equivalence replacement to these features and embodiment.In addition, under instruction of the present invention, can modify to adapt to concrete situation and material and can not depart from the spirit and scope of the present invention these features and embodiment.Therefore, the present invention is not subject to the restriction of specific embodiment disclosed herein, and the embodiment within the scope of all the application's of falling into claim belongs to protection scope of the present invention.
Claims (9)
1. a RFID EEPROM charge pump, it is characterized in that: comprise the two-stage charge pump that first order charge pump and second level charge pump form, level translator and clock generator, first order charge pump produces the low-voltage output signal higher than supply power voltage (Vdd) by chip power supply voltage (Vdd) power supply, first order charge pump output connects second level charge pump, second level charge pump produces the erasable required voltage of EEPROM (Vo2) by output voltage (Vo1) power supply of first order charge pump, the output of clock generator connects first order charge pump, the output of clock generator connects second level charge pump by level translator and produces the required high pressure clock of second level charge pump, level translator connects first order electric charge delivery side of pump, level translator is by output voltage (Vo1) power supply of first order charge pump.
2. a kind of RFID EEPROM charge pump according to claim 1, it is characterized in that: described clock generator comprise one-level Clock dividers at least, in order to select different fractions frequently device output signal multiplexer and be used for controlling multiplexer to select the counter of different output, frequency divider is connected in series, master clock only connects the input of first order Clock dividers, and the output of the first order is as the input of second level Clock dividers; Multiplexer connects master clock and Clock dividers output at different levels, and counter connects master clock and multiplexer.
3. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described clock generator is voltage controlled oscillator, increases the frequency of output signal by increasing voltage signal.
4. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described clock generator output frequency is increased and produced by the mode of going forward one by one or continuation mode.
5. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described clock generator is output as diphasic clock signal, non-overlapped diphasic clock signal or four phase clock signals.
6. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described first order charge pump is low voltage transistor circuit, adopts low pressure intrinsic NMOS transistor.
7. a kind of RFID EEPROM charge pump according to claim 6, is characterized in that: described second level charge pump is high voltage transistor circuit, adopts high voltage intrinsic NMOS transistor.
8. a kind of RFID EEPROM charge pump according to claim 7, is characterized in that: described first order charge pump and second level charge pump all adopt Dixon charge pump circuit or with the charge pump of body effect compensating circuit.
9. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described chip power supply voltage (Vdd) is lower than 1.5V, and the erasable required voltage of EEPROM (Vo2) is 16V.
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| CN201410375603.XA CN104092371B (en) | 2014-08-01 | 2014-08-01 | RFID (Radio Frequency Identification) EEPROM (Electrical Erasable Programmable Read Only Memory) charge pump |
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| CN201410375603.XA CN104092371B (en) | 2014-08-01 | 2014-08-01 | RFID (Radio Frequency Identification) EEPROM (Electrical Erasable Programmable Read Only Memory) charge pump |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290983A (en) * | 2011-06-16 | 2011-12-21 | 北京大学 | Charge pump |
| CN102647184A (en) * | 2012-04-28 | 2012-08-22 | 北京握奇数据***有限公司 | Phase-locked loop, active radio frequency identification (RFID) label, double-interface card and control method of phase-locked loop |
| CN103138568A (en) * | 2011-12-01 | 2013-06-05 | 国民技术股份有限公司 | Rectifying circuit and radio frequency identification (RFID) chip |
| US20130222050A1 (en) * | 2012-02-29 | 2013-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low Voltage and High Driving Charge Pump |
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- 2014-08-01 CN CN201410375603.XA patent/CN104092371B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102290983A (en) * | 2011-06-16 | 2011-12-21 | 北京大学 | Charge pump |
| CN103138568A (en) * | 2011-12-01 | 2013-06-05 | 国民技术股份有限公司 | Rectifying circuit and radio frequency identification (RFID) chip |
| US20130222050A1 (en) * | 2012-02-29 | 2013-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low Voltage and High Driving Charge Pump |
| CN102647184A (en) * | 2012-04-28 | 2012-08-22 | 北京握奇数据***有限公司 | Phase-locked loop, active radio frequency identification (RFID) label, double-interface card and control method of phase-locked loop |
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