CN104090405B - Tiled display panel and display device - Google Patents
Tiled display panel and display device Download PDFInfo
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- CN104090405B CN104090405B CN201410312918.XA CN201410312918A CN104090405B CN 104090405 B CN104090405 B CN 104090405B CN 201410312918 A CN201410312918 A CN 201410312918A CN 104090405 B CN104090405 B CN 104090405B
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Abstract
The embodiment of the invention provides a tiled display panel and a display device and relates to the technical field of display. By the adoption of the tiled display panel and the display device, the edge joint width of the tiled display panel can be reduced, and display effect can be improved. The tiled display panel comprises a first display panel part and a second display panel part. The first display panel part comprises a first substrate and a second substrate, wherein the first substrate comprises a first display area and a first non-display area, the first non-display area comprises first wiring bonding areas, the second substrate is exposed from the first wiring bonding areas, and the first wiring bonding areas are distributed on the two opposite sides of the second substrate at least. The second display panel part comprises a third substrate and a fourth substrate, wherein the third substrate comprises a second display area and a second non-display area, the second non-display area comprises second wiring bonding areas, the fourth substrate is exposed from the second wiring bonding areas, and the second wiring bonding areas are distributed on the two opposite sides of the fourth substrate at least. The first wiring bonding areas of the first substrate correspond to the second wiring bonding areas close to the third substrate.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of tiled display panel and display device.
Background technology
At present, in many occasions such as exhibition center, public place of entertainment, control and command center, need using with jumbotron
Display floater carry out display image, due to the processing technology difficulty for directly making ultra-large type display floater it is very big, it is existing super
Larger display panels are spliced by multiple display floaters mostly.Because the viewing area periphery of each display floater has
There is the non-display area of certain wide cut, thus the viewing area of the ultra-large type display floater being spliced into by multiple display floaters is really
Be made up of the spaced little viewing area of multiple tools, so since, the zone line of spliced ultra-large type display floater is deposited
In the splicing gap that multiple transverse and longitudinals are intersected, the visual effect of display image is affected.
Because each display floater for splicing is required for adjacent display floater para-position and by corresponding attachment means
Interfix, the display floater quantity of splicing is more, then display floater aligning accuracy each other is lower, spliced super large
Splicing gap in type display floater is also more, reduce further the visual effect of display image.Therefore, in order to reach reduction
Splicing quantity and the purpose in splicing gap, are generally used for splicing each display floater of ultra-large type display floater with larger
Size.
However, as depicted in figs. 1 and 2, when each display floater for being used for splicing is respectively provided with large-size, in order to meet
The altofrequency of large scale display floater drives, it usually needs using the array base palte in the pattern of bilateral driving, i.e. display floater
The conducting lead district 03 (i.e. Bonding areas) not covered by color membrane substrates 02 on 01 is located at least in the relative of color membrane substrates 02
Both sides, conducting lead district 03 makes array base palte 01 be connected with external circuit；Wherein, the array in two adjacent display floaters
Outer ledge distance difference labelling of the edge (A is labeled as in figure) of the viewing area of substrate 01 to close conducting lead district 03
For a10With a20。
As seen from Figure 2, compared to being spliced using the less display floater of multiple sizes, when using by many
When all larger display floater of individual size is spliced, although the quantity in splicing gap can be reduced, however, due to adjacent two
When individual display floater is spliced, the conducting lead district 03 in each display floater is two that is, adjacent display surfaces side by side
Spacing between the viewing area of plate cannot reduce.The centre of ultra-large type display floater after splicing is respectively positioned on due to splicing gap
Region.Therefore, prior art is still difficult to solve ultra-large type display floater the asking with significantly splicing gap of splicing composition
Topic, causes its image to show and is difficult to reach ideal effect.
The content of the invention
Embodiments of the invention provide a kind of tiled display panel and display device, when by multiple larger-size displays
When panel is spliced, the width in the splicing gap of tiled display panel can be effectively reduced, improve tiled display Display panel figure
The visual effect of picture.
To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that：
On the one hand a kind of tiled display panel, is embodiments provided, the tiled display panel includes phase mutual connection
Tactile the first display floater and the second display floater；First display floater includes first substrate and the second base arranged to box
Plate；The first substrate includes the first viewing area and the first non-display area, and first non-display area walks wire bonding including first
Area；The second substrate exposes the first cabling bonding land, and the first cabling bonding land is at least distributed in described second
The opposite sides of substrate；Second display floater includes the 3rd substrate and the tetrabasal arranged to box；3rd substrate
Including the second viewing area and the second non-display area, second non-display area includes the second cabling bonding land；The tetrabasal
Expose the second cabling bonding land, and the second cabling bonding land is at least distributed in the opposite sides of the tetrabasal；
Wherein, the first substrate contacts with the close tetrabasal, the second substrate and close the 3rd substrate
Contact；Wire bonding is walked with described the second of close the 3rd substrate in the first cabling bonding land of the first substrate
Area is corresponding.
Preferably, the first substrate includes being located at first array of first underlay substrate near the second substrate side
Structure sheaf, the second substrate includes being located at first packed layer and first of second underlay substrate near the first substrate side
Color membrane structure layer；3rd substrate includes being located at second array structure of the 3rd underlay substrate near the tetrabasal side
Layer and the second color membrane structure layer, the tetrabasal includes being located at the 4th underlay substrate near the second of the 3rd substrate side
Packed layer；Or, the 3rd substrate includes being located at second array structure of the 3rd underlay substrate near the tetrabasal side
Layer, the tetrabasal includes being located at second color membrane structure layer and second of the 4th underlay substrate near the 3rd substrate side
Packed layer；Wherein, the second substrate is identical with the 3rd substrate thickness；The tetrabasal and the first substrate thickness
It is identical.
Optionally, the feelings of the second array structure layer and the second color membrane structure layer are included for the 3rd substrate
Condition, the second color membrane structure layer is located between the 3rd underlay substrate and the second array structure layer.
Optionally, the second array structure layer is included for the 3rd substrate, the tetrabasal includes described the
The situation of two color membrane structure layers and second packed layer, the 3rd substrate also includes the first black matrix layer；Wherein, described
One black matrix layer is located between the 3rd underlay substrate and the second array structure layer, and the figure of first black matrix layer
Case is corresponding with the pattern of the thin film transistor (TFT) in the second array structure layer.
Optionally, the first array structure layer includes being located at first underlay substrate near the second substrate side
First film transistor array, the first insulating barrier, the first pixel electrode, the first protective layer and the first public electrode；It is described
Second array structure layer includes being located at second thin film transistor (TFT) battle array of second underlay substrate near the tetrabasal side
Row, the second insulating barrier, the second pixel electrode, the second protective layer and the second public electrode.
Optionally, the second substrate also includes first transparency electrode layer；The tetrabasal also includes the second transparent electricity
Pole layer；Wherein, the first transparency electrode layer is arranged away from first liquid crystal layer；The second transparency electrode layer is away from described
Second liquid crystal layer is arranged.
Preferred on the basis of the above, first display floater also includes being located at the first substrate and second base
The first liquid crystal layer between plate；Second display floater also includes being located between the 3rd substrate and the tetrabasal
Second liquid crystal layer；Wherein, the thickness of first liquid crystal layer is identical with the thickness of second liquid crystal layer.
It is preferred on the basis of the above, multiple spaced first circuit welderings are provided with the first cabling bonding land
Panel；Multiple spaced second circuit pad areas are provided with the second cabling bonding land；Wherein, first circuit
Pad area interlocks corresponding with the second circuit pad area.
Preferred on the basis of the above, the first cabling junction profile is in three sides of periphery of the second substrate
Face；The second cabling junction profile is in three sides of periphery of the tetrabasal.
On the other hand, the embodiment of the present invention provides a kind of display device again, and the display device includes any of the above-described
Described tiled display panel.
In the tiled display panel provided in an embodiment of the present invention, due to the first substrate and the close the described 4th
Substrate contacts, and the second substrate contacts with close the 3rd substrate, also, described on the first substrate
One cabling bonding land is corresponding with the second cabling bonding land on close the 3rd substrate, therefore, along perpendicular to spelling
The plate face direction of display floater is connect, the first cabling bonding land is overlapped with the projection of the second cabling bonding land, i.e.,
First display floater contacts with being staggered with second display floater to intersect.
Due to tiled display panel splicing gap producing cause just because of the viewing area in display floater outside
The non-display area of certain wide cut is inevitably present, and in the tiled display panel provided in an embodiment of the present invention, due to
First display floater and second display floater are intersected the carrying out being staggered to splice so that the institute on the outside of first viewing area
The a part of region for stating second non-display area on the outside of the first non-display area and close second viewing area overlaps,
Compared to the mode that two adjacent display floaters of the prior art splice side by side, hence it is evident that shorten the first viewing area and second
The distance between viewing area, realizes the purpose in the splicing gap for reducing tiled display panel, so as to improve tiled display face
The visual effect of plate display image.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
A kind of overlooking the structure diagram of tiled display panel that Fig. 1 is provided for prior art；
Fig. 2 is the cross-sectional view of the tiled display panel in the AA' directions along Fig. 1；
Fig. 3 is a kind of overlooking the structure diagram one of tiled display panel provided in an embodiment of the present invention；
Fig. 4 is the cross-sectional view of the tiled display panel in the BB' directions along Fig. 3；
Fig. 5 (a) is a kind of each hierarchical structure schematic diagram one of tiled display panel provided in an embodiment of the present invention；
Fig. 5 (b) is a kind of each hierarchical structure schematic diagram two of tiled display panel provided in an embodiment of the present invention；
Fig. 6 is a kind of overlooking the structure diagram two of tiled display panel provided in an embodiment of the present invention.
Reference：
01- array base paltes；02- color membrane substrates；03- turns on lead district；The display floaters of 10- first；11- first substrates；
The underlay substrates of 110- first；111- the first array structure layers；1111- first film transistor arrays；The grid metals of 1111a- first
Layer；The active layers of 1111b- first；The Source and drain metal levels of 1111c- first；The insulating barriers of 1112- first；The pixel electrodes of 1113- first；
The protective layers of 1114- first；The public electrodes of 1115- first；The first circuit lands of 112- area；12- second substrates；The substrates of 120- second
Substrate；The packed layers of 121- first；122- the first color membrane structure layers；1221- the first black matrix patterned layer；The colored filters of 1222- first
Photosphere；The protective layers of 1223- first；1224- the first chock insulator matter patterned layer；123- first transparency electrode layers；The liquid crystal layers of 13- first；
The display floaters of 20- second；The substrates of 21- the 3rd；The underlay substrates of 210- the 3rd；211- the second array structure layers；The thin film of 2111- second
Transistor array；The barrier metal layers of 2111a- second；The active layers of 2111b- second；The Source and drain metal levels of 2111c- second；2112- second
Insulating barrier；The pixel electrodes of 2113- second；The protective layers of 2114- second；The public electrodes of 2115- second；2116- the second chock insulator matter figures
Pattern layer；212- second circuit pad areas；212- the second color membrane structure layers；2121- the second black matrix patterned layer；2122- second is color
Color filtering optical layer；The protective layers of 2123- second；The black matrix layers of 213- first；22- tetrabasals；The underlay substrates of 220- the 4th；221-
Two packed layers；222- second transparency electrode layers；The liquid crystal layers of 23- second.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
A kind of tiled display panel is embodiments provided, as shown in Figure 3 and Figure 4, the tiled display panel bag
Include the first display floater 10 and the second display floater 20；First display floater 10 include to box arrange first substrate 11 with
Second substrate 12；The first substrate 11 (is labeled as A including the first viewing area1) (it is labeled as NA with the first non-display area1), institute
State the first non-display area S1(B is labeled as including the first cabling bonding land1)；The second substrate 12 exposes first cabling and connects
Close area B1, and the first cabling bonding land B1At least it is distributed in the opposite sides of the second substrate 12.
Second display floater 20 includes the 3rd substrate 21 and the tetrabasal 22 arranged to box；3rd substrate 21
(A is labeled as including the second viewing area2) (it is labeled as NA with the second non-display area2), the second non-display area NA2Including second
Cabling bonding land (is labeled as B2)；The tetrabasal 22 exposes the second cabling bonding land B2, and described second walk wire bonding
Area B2At least it is distributed in the opposite sides of the tetrabasal 22.
Wherein, the first substrate 11 contacts with the close tetrabasal 22, the second substrate 12 with it is close
The 3rd substrate 21 contact；The first cabling bonding land B of the first substrate 111With close the 3rd base
The second cabling bonding land B of plate 212It is corresponding.
It should be noted that the tiled display panel is only symbolically provided in first, Fig. 3 and Fig. 4 by an institute
The situation that the first display floater 10 and second display floater 20 are spliced is stated, but the embodiment of the present invention is not limited to
This, the tiled display panel can also be spliced by multiple first display floaters 10 and multiple second display floaters 20 and
Into.
Secondth, described first cabling bonding land B1With the second cabling bonding land B2Effect be respectively by described first
Drive circuit (such as chip on film, the Chip On Flex/ of each holding wire in substrate 11 and the 3rd substrate 21 and outside
Film, abbreviation COF) the region that crimped of lead.
With reference to shown in Fig. 4, in the tiled display panel provided in an embodiment of the present invention, due to the first substrate 11 with
The close tetrabasal 22 contacts, and the second substrate 12 contacts with close the 3rd substrate 21, also, institute
State the first cabling bonding land B on first substrate 111Connect with second cabling on close the 3rd substrate 21
Close area B2It is corresponding, therefore, along perpendicular to the plate face direction of tiled display panel, the first cabling bonding land B1With described
Two cabling bonding land B2Projection it is overlapped, i.e., described first display floater 10 and second display floater 20 are to intersect phase
Contact wrongly.
Due to tiled display panel splicing gap producing cause just because of the viewing area in display floater outside
The non-display area of certain wide cut is inevitably present, and in the tiled display panel provided in an embodiment of the present invention, due to
First display floater 10 and second display floater 20 are intersected the carrying out being staggered to splice so that the first viewing area A1Outward
The first non-display area NA of side1With close the second viewing area A2The second non-display area NA in outside2One
Subregion overlaps, compared to the mode that two adjacent display floaters of the prior art splice side by side, hence it is evident that shorten
The distance between one viewing area and second viewing area, have reached the purpose in the splicing gap for reducing tiled display panel, so as to can
Improve the visual effect of tiled display Display panel image.
Concrete analysis is as follows, for simplicity, with reference to shown in Fig. 4, by first display floater 10, described first
Viewing area A1To close the first cabling bonding land B1Outer ledge (edge of i.e. described first substrate 11) spacing mark
It is designated as a10, in the same manner, by second display floater 10, the second viewing area A2To close the second cabling bonding land
B2Outer ledge (edge of i.e. described 3rd substrate 21) pitch mark be a20；Therefore, compared to existing shown in Fig. 2
Two display floaters adjacent in technology side by side after viewing area between spacing L=a10+a20, provide in the embodiment of the present invention
The tiled display panel in, due to a10With a20Region in, corresponding to the first cabling bonding land B1Wire bonding is walked with second
Area B2Region be to overlap, therefore, spacing L' between adjacent the first viewing area and the second close viewing area<a10+a20,
It is possible thereby to prove that the tiled display panel provided in an embodiment of the present invention has less splicing gap.
For example, as the first viewing area A1Edge to the edge of the close second substrate 12 spacing with it is described
Second viewing area A2Edge to the edge of the close tetrabasal 22 spacing it is equal be b when, and a10=a20=a
When, because the numerical value of b is necessarily less than a10Or a20Numerical value, then in the tiled display panel provided in an embodiment of the present invention,
Spacing L' between adjacent the first viewing area and the second close viewing area can be reduced to (a+b).
Further, for the ease of the first cabling bonding land B1With the second cabling bonding land B2On each cabling
Wiring connection, with reference to shown in Fig. 3, the first cabling bonding land B1It is distributed in three sides of periphery of the second substrate 12；
The second cabling bonding land B2It is distributed in three sides of periphery of the tetrabasal 22.
On the basis of the above, first display floater 10 and second display floater 20 for example may include in detail below
Structure：
As shown in Fig. 5 (a), the first substrate 11 includes being located at the first underlay substrate 110 near the second substrate 12
First array structure layer 111 of side, the second substrate 12 includes being located at the second underlay substrate 120 near the first substrate
First packed layer 121 and the first color membrane structure layer 122 of 11 sides；3rd substrate 21 includes being located at the 3rd underlay substrate
210 near the side of tetrabasal 22 the second array structure layer 211 and the second color membrane structure layer 212, the tetrabasal
22 include being located at second packed layer 221 of the 4th underlay substrate 220 near the side of the 3rd substrate 21.
Or, such as shown in Fig. 5 (b), the first substrate 11 includes being located at the first underlay substrate 110 near second base
First array structure layer 111 of the side of plate 12, the second substrate 12 includes being located at the second underlay substrate 120 near described first
First packed layer 121 and the first color membrane structure layer 122 of the side of substrate 11；3rd substrate 21 includes being located at the 3rd substrate base
Plate 210 near the side of tetrabasal 22 the second array structure layer 211, the tetrabasal 22 include be located at the 4th substrate
Second color membrane structure layer 212 and second packed layer 221 of the substrate 220 near the side of the 3rd substrate 21.
Wherein, the second substrate 12 is identical with the thickness of the 3rd substrate 21；The tetrabasal 22 and described first
The thickness of substrate 11 is identical.
It should be noted that first, the array structure layer, refer to that be sequentially formed in substrate surface at least includes thin film
Transistor array, insulating barrier, the level stacked structure of pixel electrode；The color membrane structure layer, refers to and is sequentially formed in substrate table
Face at least include black matrix patterned layer, the level stacked structure of chromatic filter layer.
Above-mentioned substrate surface for example can be the surface of underlay substrate, or the surface of other film layers, here is not
It is construed as limiting, should be flexibly arranged according to concrete structure.
Secondth, because the tiled display panel provided in an embodiment of the present invention is by by the first substrate 11 and institute
State tetrabasal 22 to contact, the second substrate 12 is contacted so as to realize showing to described first with the 3rd substrate 21
Show the splicing of panel 10 and second display floater 20, therefore, when the first substrate 11 and the thickness of tetrabasal 22
Difference, when the second substrate 12 is different from the thickness of the 3rd substrate 21, can not only increase the difficulty of splicing para-position, can also make
Into the quality discrepancy of first display floater and the second display floater display image.Additionally, the more color film of array structure layer
The hierarchical structure of structure sheaf is increasingly complex, and accordingly, the integral thickness of array structure layer is also greater than the entirety of color membrane structure layer
Thickness.
Based on this, second substrate 12 described in polishing is as filled in the effect of first packed layer 121, so that described second
Substrate 12 is identical with the thickness of the 3rd substrate 21；Likewise, the effect of second packed layer 221 is as filled described in polishing
Tetrabasal 22, so that the tetrabasal 22 is identical with the thickness of the first substrate 11, so as to be conducive to described first to show
Panel 10 splices with the para-position of second display floater 20, and ensures that spliced ultra-large type display floater has good figure
As display quality.
Here, in order to reduce the optics product to first display floater 10 and the display image of the second display floater 20
The impact of matter, first packed layer 121 should try one's best using the material with high permeability, example with second packed layer 221
Such as, using polyimide resin (polyimide, referred to as PI) or acrylic resin (acrylic acid polymers) etc.
Resin material.
3rd, in the second substrate 12, first packed layer 121 may be referred to be arranged on institute shown in Fig. 5 (a)
State between the second underlay substrate 120 and the first color membrane structure layer 122, or, first packed layer 121 may also be arranged on
Side of the first color membrane structure layer 122 away from second underlay substrate 120；Correspondingly, in the tetrabasal 22,
Second packed layer 221 may be referred to be arranged on the second color membrane structure layer 212 away from the described 4th shown in Fig. 5 (b)
The side of underlay substrate 220, or, second packed layer 221 may also be arranged on the 4th underlay substrate 220 with described
Between two color membrane structure layers 212.It is not limited thereto, can flexibly adjusts on the premise of technique number of times and technology difficulty is reduced as far as possible
It is whole.
On the basis of the above, with reference to shown in Fig. 5 (a), because the second array structure layer 211 is located at the 3rd substrate
On substrate 210, i.e., described second array structure layer 211 is relatively close to the display side of second display floater 20, when
Spliced ultra-large type display panel applications under the larger environment of the ambient intensity such as open air, due to second array junctions
Grid, source electrode and the drain electrode that thin film transistor (TFT) is constituted in structure layer 211 is generally prepared from by metal material, in tiled display panel
When carrying out image and showing, it is possible to the reflection of grid, source electrode and drain electrode light to external world can be caused, the viewing effect of human eye is affected
Really.
Therefore, the embodiment of the present invention is more preferably with reference to shown in Fig. 5 (a), for the 3rd substrate 21 institute to be included
The situation of the second array structure layer 211 and the second color membrane structure layer 212 is stated, the second color membrane structure layer 212 is located at institute
State between the 3rd underlay substrate 210 and the second array structure layer 211.
Since so, it is possible to use the black matrix patterned layer in the second color membrane structure layer 212 shelters from described second
Thin film transistor (TFT) pattern in array structure layer 211, so as to avoid thin film transistor (TFT) in grid, source electrode and drain electrode pattern pair
The reflection of ambient.
On the basis of the above, with reference to shown in Fig. 5 (b), for the 3rd substrate 21 the second array structure layer is included
211, the tetrabasal 22 includes the situation of the second color membrane structure layer 212 and second packed layer 221, due to described
Second color membrane structure layer 212 is relatively distant from the display side of second display floater 20, i.e., described second color membrane structure layer
Black matrix patterned layer in 212 cannot shelter from the thin film transistor (TFT) pattern in the second array structure layer 211.
Therefore, the embodiment of the present invention is more preferably with reference to shown in Fig. 5 (b), for the 3rd substrate 21 institute to be included
The second array structure layer 211 is stated, the tetrabasal 22 includes the second color membrane structure layer 212 and second packed layer
221 situation, the 3rd substrate 21 also includes the first black matrix layer 213.
Wherein, first black matrix layer 213 is located at the 3rd underlay substrate 210 and the second array structure layer
Between 211, and the figure of the thin film transistor (TFT) in the pattern of first black matrix layer 213 and the second array structure layer 211
Case is corresponding.
Since so, for the situation shown in Fig. 5 (b), by extra one layer of first increased black matrix layer 213, it is to avoid
The reflection of the pattern of grid, source electrode and drain electrode in thin film transistor (TFT) in the second array structure layer 211 light to external world.
It should be noted that due to the black matrix structure in first display floater 10 and second display floater 20
Not on same level position, optical analog need to be carried out with second display floater 20 to first display floater 10, with
Ensure that the aperture opening ratio of the two is consistent, or it is as far as possible close, so that the display quality of image of the two is identical or as far as possible close.
On the basis of the above, first display floater 10 also includes being located at the first substrate 11 and the second substrate
The first liquid crystal layer 13 between 12；Second display floater 20 also includes being located at the 3rd substrate 21 and the tetrabasal
The second liquid crystal layer 23 between 22.
Here, when the thickness of liquid crystal layer in first display floater 10 with second display floater 20 is inconsistent,
Can cause light from liquid crystal layer pass through when transmitance it is different, affect display quality, therefore, first liquid crystal layer 13 with it is described
The thickness of second liquid crystal layer 23 is identical.
Since so, the first display floater 10 each thickness degree corresponding with second display floater 20 is homogeneous
Together, it is ensured that para-position splicing is favorably carried out, it is to avoid each thickness degree inconsistent reduction to display quality of image.
Further, the first array structure layer 111 includes being located at first underlay substrate 110 near described second
The first film transistor array 1111 of the side of substrate 12, the first insulating barrier 1112, the first pixel electrode 1113, the first protective layer
1114 and first public electrode 1115.The second array structure layer 211 includes being leaned on positioned at second underlay substrate 210
Second thin film transistor (TFT) array 2111 of the nearly side of tetrabasal 22, the second insulating barrier 2112, the second pixel electrode 2113,
Second protective layer 2114 and the second public electrode 2115.
Based on this, can cause between first pixel electrode 1113 and first public electrode 1115, described
Multi-dimensional electric field is respectively formed between two pixel electrodes 2113 and second public electrode 2115 so that correspondence in the first liquid crystal layer 13
Between first pixel electrode 1113 and all aligned liquid-crystal molecules in the top of first pixel electrode 1113 can be with
Rotate, likewise, so that corresponding between second pixel electrode 2113 and described in second liquid crystal layer 23
The all aligned liquid-crystal molecules in the top of second pixel electrode 2113 can be rotated, so as to improve the work efficiency of liquid crystal molecule
And increase its light transmission efficiency.
Here, relative position of the embodiment of the present invention to first pixel electrode 1113 and first public electrode 1115
Put relation and second pixel electrode 2113 to be not construed as limiting with the relative position relation of second public electrode 2115.
In view of should as much as possible make first display floater 10 close with every display quality of second display floater 20 or
It is identical, for example, refer to shown in Fig. 5 (a), first pixel electrode 1113 is located near first liquid crystal layer 13
Side, second pixel electrode 2113 is located near the side of second pixel electrode 2113.
Wherein, the thin film transistor (TFT) type in the first film transistor array 1111 and second thin film transistor (TFT)
Thin film transistor (TFT) type in array 2111 can be with identical, also can be different, here, being equally based on above-mentioned consideration, the present invention is implemented
Woods is more preferably, the thin film transistor (TFT) type in the first film transistor array 1111 and second film crystal
Thin film transistor (TFT) type in pipe array 2111 is identical.
So, not only can ensure that every display quality of first display floater 10 and second display floater 20
It is close or identical, can also cause to prepare first display floater 10 and continue to use phase during second display floater 20 as much as possible
Same preparation technology, simplifies the preparation technology difficulty for preparing each panel for tiled display panel.
On this basis, due in first display floater 10, first pixel electrode 1113 and described first
Public electrode 1115 is respectively positioned on the first substrate 11, with the second substrate 12 of the first substrate 11 to box on not
There is electrode；Likewise, second pixel electrode 2113 is respectively positioned on the 3rd substrate 21 with second public electrode 2115
On, and not electrode on the tetrabasal 22 of the 3rd substrate to box, therefore, the second substrate 12 with it is described
Electrostatic charging is easily produced on tetrabasal 22, it is possible to affect the normal work of liquid crystal molecule so as to which orientation disorder, shadow occur
Ring display quality.
Therefore, it is further preferred that the second substrate 12 also includes first transparency electrode layer 123；The tetrabasal
22 also include second transparency electrode layer 222.Wherein, the first transparency electrode layer 123 is arranged away from first liquid crystal layer 13；
The second transparency electrode layer 222 is arranged away from second liquid crystal layer 23.
The first transparency electrode layer 123 for example can have identical current potential, institute with first public electrode 1115
State second transparency electrode layer 222 for example can have identical current potential with second public electrode 2115, i.e., equivalent to ground connection,
When the second substrate 12 is subject to extraneous static interference with the tetrabasal 22, due to the first transparency electrode layer
123 with the shielding action of the second transparency electrode layer 222, can effectively prevent external electrical field to first display floater 10 with
The impact of the internal electric field of the second display floater 20.
Here, the first transparency electrode layer 123 can for example adopt tin indium oxide with the second transparency electrode layer 222
(Indium Tin Oxide, referred to as ITO) conductive material is prepared from.
Seen from the above description, in order to avoid static interference is to first liquid crystal layer 13 and second liquid crystal layer 23
Affect, the first transparency electrode layer 123 should try one's best and be arranged away from first liquid crystal layer 13, likewise, described second is transparent
Electrode layer 222 should try one's best and be arranged away from second liquid crystal layer 23.
Based on this, with reference to shown in Fig. 5 (a) or Fig. 5 (b), in the second substrate 12, the first transparency electrode layer
123 may be provided between first packed layer 121 and the first color membrane structure layer 122, certainly, the first transparency electrode
Layer 123 may also be arranged between first packed layer 121 and second underlay substrate 120, be not limited thereto.
Correspondingly, with reference also to Fig. 5 (a) or Fig. 5 (b) Suo Shi, in the tetrabasal 22, the second transparency electrode
Layer 222 may be provided between second packed layer 221 and the 4th underlay substrate 220；Wherein, for the tetrabasal
22 situations for including the second color membrane structure layer 212 and second packed layer 221, the second transparency electrode layer 222 with
The relative position relation of the second color membrane structure layer 212 is not construed as limiting, i.e. the second transparency electrode layer 222 for example can be with
Being further located between the second color membrane structure layer 212 and the 4th underlay substrate 220 with reference to shown in Fig. 5 (b), also may be used
To be further located between second packed layer 221 and the second color membrane structure layer 212.
On the basis of the above, it is contemplated that in first substrate 11, by each holding wire in the first array structure layer 111
When being crimped with the lead of outside drive circuit, outside drive circuit (such as COF plates) needs to be fitted in described first to be walked
Wire bonding area B1It is interior, likewise, in the 3rd substrate 21, by each holding wire in the second array structure layer 211 and outside
The lead of drive circuit when being crimped, outside drive circuit (such as COF plates) needs to be fitted in described second walks wire bonding
Area B2It is interior, in order to reduce the splicing of the first substrate 11 and the tetrabasal 22 after, the 3rd substrate 21 and described second
After substrate 12 splices, the drive circuit on the first substrate 11 is overlapping with the drive circuit generation on the 3rd substrate 21,
Affect the splicing of the first display floater 10 and the second display floater 20.
Therefore, it is further preferred that as shown in fig. 6, the first cabling bonding land B1Arrange on (not indicating in figure)
There are multiple spaced first circuit land areas 112；The second cabling bonding land B2It is provided with (not indicating in figure)
Multiple spaced second circuit pad areas 212；Wherein, the first circuit land area 112 and the second circuit pad
Area 212 is staggeredly corresponding.
So, after splicing with second display floater 20 to first display floater 10, respectively described
One circuit land area 112 and the second circuit pad area 212 are fitted corresponding drive circuit board (such as COF plates), i.e., described
Between the plane of the plane and the second substrate 12 and the 3rd substrate 21 of first substrate 11 and the tetrabasal 22 only
There is the drive circuit board of a layer thickness, and correspond respectively to the drive circuit phase of the first substrate 11 and the 3rd substrate 21
Mutually staggeredly it is independent of each other.
A specific example is provided below, for describing above-mentioned tiled display panel in detail.
The specific embodiment of the invention provides a kind of tiled display panel, with reference to shown in Fig. 5 (a), the tiled display face
Plate includes the first display floater 10 and the second display floater 20；First display floater 10 includes the first substrate arranged to box
11 with second substrate 12, and the first liquid crystal layer 13 positioned there between；The first substrate 11 include the first viewing area with
First non-display area, first non-display area includes the first cabling bonding land；The second substrate 12 exposes described first and walks
Wire bonding area, and the first cabling junction profile is in three sides of the second substrate 12.
Specifically, the first substrate 11 includes being sequentially located at the first underlay substrate 110 near the second substrate 12 1
First array structure layer 111 of side is (successively including first film transistor array 1111, the first insulating barrier 1112, the first pixel
Electrode 1113, the first protective layer 1114 and the first public electrode 1115)；The second substrate 12 includes being sequentially located at second
First packed layer 121, first transparency electrode layer 123, first color film knot of the underlay substrate 120 near the side of the first substrate 11
Structure layer 122.
Wherein, the first film transistor array 1111 is included successively away from the first of first underlay substrate 110
Barrier metal layer 1111a, the first gate insulation layer, the first active layer 1111b and the first Source and drain metal level 1111c；Described first is color
Membrane structure layer 122 is included successively away from 1,221 first black matrix patterned layer, first colorized optical filtering of second underlay substrate 120
The 1222, first protective layer 1223 of layer and 1,224 first chock insulator matter patterned layer.
The barrier metal layer refers to the metal level of grid, grid line and grid line lead；The Source and drain metal level is referred to
Including the metal level of source electrode, drain electrode, data wire and data cable lead wire.
Second display floater 20 include to box arrange the 3rd substrate 21 and tetrabasal 22, and positioned at the two it
Between the second liquid crystal layer 23；3rd substrate 21 includes the second viewing area and the second non-display area, second non-display area
Including the second cabling bonding land；The tetrabasal 22 exposes the second cabling bonding land, and the second cabling bonding land
It is distributed in three sides of the tetrabasal 22.
Specifically, the 3rd substrate includes being sequentially located at the 3rd underlay substrate 210 near the side of tetrabasal 22
The second color membrane structure layer 212 it is (exhausted including the second thin film transistor (TFT) array 2111, second successively with the second array structure layer 211
Edge layer 2112, the second pixel electrode 2113, the second protective layer 2114, the second public electrode 2115 and the second dottle pin article pattern
Layer is 2116)；The tetrabasal 22 includes being sequentially located at the 4th underlay substrate 220 near the 222 of the side of the 3rd substrate 21
With the second packed layer 221.
Wherein, second thin film transistor (TFT) array 2111 is included successively away from the second of the 3rd underlay substrate 210
Barrier metal layer 2111a, the second gate insulation layer, the second active layer 2111b and the second Source and drain metal level 2111c；Described second is color
Membrane structure layer 212 is included successively away from the second black matrix patterned layer 2121, second colorized optical filtering of the 3rd underlay substrate 210
The protective layer 2123 of layer 2122 and second.
The first substrate 11 is identical with the thickness of tetrabasal 22, the second substrate 12 and the 3rd substrate 21
Thickness is identical, and first liquid crystal layer 13 is identical with the thickness of the second liquid crystal layer 23；The first substrate 11 and close institute
State tetrabasal 22 to contact, the second substrate 12 contacts with close the 3rd substrate 21；The first substrate 11
The first cabling bonding land it is corresponding with the second cabling bonding land of close the 3rd substrate 21.
With reference to shown in Fig. 4, in the tiled display panel provided in an embodiment of the present invention, due to the first substrate 11 with
The close tetrabasal 22 contacts, and the second substrate 12 contacts with close the 3rd substrate 21, also, institute
State the first cabling bonding land B on first substrate 111Connect with second cabling on close the 3rd substrate 21
Close area B2It is corresponding, therefore, along perpendicular to the plate face direction of tiled display panel, the first cabling bonding land B1With described
Two cabling bonding land B2Projection it is overlapped, i.e., described first display floater 10 and second display floater 20 are to intersect phase
Contact wrongly.
Due to tiled display panel splicing gap producing cause just because of the viewing area in display floater outside
The non-display area of certain wide cut is inevitably present, and in the tiled display panel provided in an embodiment of the present invention, due to
First display floater 10 and second display floater 20 are intersected the carrying out being staggered to splice so that the first viewing area A1Outward
The first non-display area NA of side1With close the second viewing area A2The second non-display area NA in outside2One
Subregion overlaps, compared to the mode that two adjacent display floaters of the prior art splice side by side, hence it is evident that shorten
The distance between one viewing area and second viewing area, have reached the purpose in the splicing gap for reducing tiled display panel, so as to can
Improve the visual effect of tiled display Display panel image.
The embodiment of the present invention additionally provides a kind of display device including above-mentioned tiled display panel, above-mentioned display device
Can be specifically liquid crystal indicator, can have for liquid crystal display, LCD TV, DPF, mobile phone, panel computer etc.
The product or part of any display function.
It should be noted that all accompanying drawings of the invention are the simple schematic diagrams of above-mentioned tiled display panel, it is only clear
Description this programme embodies the structure related to inventive point, for other structures unrelated with inventive point are existing structures,
Not embodiment or only realizational portion in accompanying drawing.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, all should contain
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by the scope of the claims.
Claims (10)
1. a kind of tiled display panel, it is characterised in that including the first display floater and the second display floater that contact with each other；
First display floater includes first substrate and the second substrate arranged to box；The first substrate shows including first
Area and the first non-display area, first non-display area includes the first cabling bonding land；The second substrate exposes described first
Cabling bonding land, and the first cabling bonding land is at least distributed in the opposite sides of the second substrate；
Second display floater includes the 3rd substrate and the tetrabasal arranged to box；3rd substrate shows including second
Area and the second non-display area, second non-display area includes the second cabling bonding land；The tetrabasal exposes described second
Cabling bonding land, and the second cabling bonding land is at least distributed in the opposite sides of the tetrabasal；
Wherein, first display floater intersects with second display floater and splices with being staggered, the first substrate with it is close
The tetrabasal contact, the second substrate contacts with close the 3rd substrate；The institute of the first substrate
State the first cabling bonding land corresponding with the second cabling bonding land of close the 3rd substrate.
2. tiled display panel according to claim 1, it is characterised in that
The first substrate includes being located at first array structure layer of first underlay substrate near the second substrate side, described
Second substrate includes being located at first packed layer and first color membrane structure layer of second underlay substrate near the first substrate side；
3rd substrate includes being located at second array structure layer and the of the 3rd underlay substrate near the tetrabasal side
Two color membrane structure layers, the tetrabasal includes that be located at the 4th underlay substrate fills near the second of the 3rd substrate side
Layer；Or,
3rd substrate includes being located at second array structure layer of the 3rd underlay substrate near the tetrabasal side, described
Tetrabasal includes being located at second color membrane structure layer and second packed layer of the 4th underlay substrate near the 3rd substrate side；
Wherein, the second substrate is identical with the 3rd substrate thickness；The tetrabasal and the first substrate thickness phase
Together.
3. tiled display panel according to claim 2, it is characterised in that include described second for the 3rd substrate
The situation of array structure layer and the second color membrane structure layer, the second color membrane structure layer be located at the 3rd underlay substrate with
Between the second array structure layer.
4. tiled display panel according to claim 2, it is characterised in that include described second for the 3rd substrate
Array structure layer, the tetrabasal includes the situation of the second color membrane structure layer and second packed layer,
3rd substrate also includes the first black matrix layer；
Wherein, first black matrix layer is located between the 3rd underlay substrate and the second array structure layer and described
The pattern of the first black matrix layer is corresponding with the pattern of the thin film transistor (TFT) in the second array structure layer.
5. tiled display panel according to claim 2, it is characterised in that the first array structure layer includes being located at institute
State first film transistor array, first insulating barrier, first pixel electricity of first underlay substrate near the second substrate side
Pole, the first protective layer and the first public electrode；
The second array structure layer includes being located at second thin film of second underlay substrate near the tetrabasal side
Transistor array, the second insulating barrier, the second pixel electrode, the second protective layer and the second public electrode.
6. tiled display panel according to claim 5, it is characterised in that first display floater also includes being located at institute
State the first liquid crystal layer between first substrate and the second substrate；Second display floater also includes being located at the 3rd base
The second liquid crystal layer between plate and the tetrabasal；The second substrate also includes first transparency electrode layer；4th base
Plate also includes second transparency electrode layer；
Wherein, the first transparency electrode layer is arranged away from first liquid crystal layer；The second transparency electrode layer is away from described
Second liquid crystal layer is arranged.
7. tiled display panel according to claim 6, it is characterised in that the thickness of first liquid crystal layer and described
The thickness of two liquid crystal layers is identical.
8. the tiled display panel according to any one of claim 1 to 6, it is characterised in that the first cabling bonding land
On be provided with multiple spaced first circuit land areas；It is provided with the second cabling bonding land multiple spaced
Second circuit pad area；
Wherein, the first circuit land area interlocks corresponding with the second circuit pad area.
9. the tiled display panel according to any one of claim 1 to 6, it is characterised in that the first cabling bonding land
It is distributed in three sides of periphery of the second substrate；
The second cabling junction profile is in three sides of periphery of the tetrabasal.
10. a kind of display device, it is characterised in that including the tiled display panel described in any one of claim 1-9.
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| CN201410312918.XA CN104090405B (en) | 2014-07-02 | 2014-07-02 | Tiled display panel and display device |
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| CN201410312918.XA CN104090405B (en) | 2014-07-02 | 2014-07-02 | Tiled display panel and display device |
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| CN104090405B true CN104090405B (en) | 2017-05-03 |
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| CN104464558B (en) * | 2014-12-11 | 2018-04-27 | 深圳市华星光电技术有限公司 | Multi-display apparatus |
| KR102352002B1 (en) * | 2015-07-31 | 2022-01-17 | 엘지디스플레이 주식회사 | Display Panel and Multi Display Device Using the Same |
| CN105093628A (en) * | 2015-08-21 | 2015-11-25 | 京东方科技集团股份有限公司 | Splicing type display screen and assembling method thereof |
| CN105044959B (en) * | 2015-09-14 | 2019-04-05 | 深圳市华星光电技术有限公司 | It is a kind of that seamless spliced multi-display apparatus can be achieved |
| CN105204210A (en) * | 2015-10-27 | 2015-12-30 | 南京中电熊猫液晶显示科技有限公司 | Splicing type liquid crystal panel and manufacturing method thereof |
| KR102517336B1 (en) | 2016-03-29 | 2023-04-04 | 삼성전자주식회사 | Display panel and multi-vision apparatus |
| US11175535B2 (en) | 2018-04-10 | 2021-11-16 | Huizhou China Star Optoelectronics Technology Co., Ltd. | Backlight module, liquid crystal display, and spliced display device |
| CN108563067A (en) * | 2018-04-10 | 2018-09-21 | 惠州市华星光电技术有限公司 | Backlight module, liquid crystal display and splicing display device |
| US20200064670A1 (en) | 2018-08-22 | 2020-02-27 | Innolux Corporation | Electronic device and method for manufacturing the same |
| KR102599722B1 (en) * | 2018-12-28 | 2023-11-09 | 삼성디스플레이 주식회사 | Display panel ad tiled display apparatus having the same |
| WO2021102810A1 (en) * | 2019-11-28 | 2021-06-03 | 京东方科技集团股份有限公司 | Display substrate, display panel, and spliced screen |
| CN111276474B (en) * | 2020-02-14 | 2023-11-03 | 华南理工大学 | Display panel and display device |
| TWI728786B (en) * | 2020-04-22 | 2021-05-21 | 群創光電股份有限公司 | Electronic device |
| CN111640377B (en) * | 2020-06-30 | 2022-06-03 | 上海天马微电子有限公司 | Display module and display device |
| CN214669956U (en) * | 2021-04-28 | 2021-11-09 | 惠州视维新技术有限公司 | Seamless splicing display |
| CN114863828B (en) * | 2022-05-31 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | Spliced screen |
| CN114822267B (en) * | 2022-05-31 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | Spliced screen |
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