CN1040809C

CN1040809C - High-density mask type read-only memory

Info

Publication number: CN1040809C
Application number: CN94107843A
Authority: CN
Inventors: 龚执豪
Original assignee: Sunplus Technology Co Ltd
Current assignee: Sunplus Technology Co Ltd
Priority date: 1994-07-11
Filing date: 1994-07-11
Publication date: 1998-11-18
Anticipated expiration: 2014-07-11
Also published as: CN1115107A

Abstract

The present invention relates to a decode circuit and an improved layout of a high-density mask type ROM in a parallel structure. The high-density mask type ROM comprises a plurality of memory areas, wherein one area is selected by an area selecting circuit; data is selected by a word line, and the data is delivered by a bit line; a metal-oxide-silicon filed-effect transistor (MOSFET) shared gate of an area selecting switch is formed. Thus, the present invention enhances the integration density and the reading speed greatly.

Description

High-density mask type read-only memory

The invention relates to a kind of high-density mask type read-only memory.Comprise that many memories are interval, utilize again between interval selection choice of technology given zone, so reduced bit-line load, thereby reduce consumed power, improve reading speed, in addition, constitute the MOS (metal-oxide-semiconductor) memory common grid of interval selection switch, therefore improve integration density greatly.

For the development of read-only memory, the most important thing is high reading speed, low consumpting power and high power capacity are wherein especially to be paid attention to most, to be become pursuing improved main developing direction at a high speed with high power capacity.Yet because circuit and layout have confidential relation, the design of circuit can have influence on layout usually, that is have influence on integrated density, so if can innovate the performance that circuit improves module, can save the component arrangement area again simultaneously, improving density, then is the purpose that the deviser pursued.

In existing highdensity read-only memory, owing to yield to layout sometimes, the degradation that causes module, for example the metal connecting line on the integrated circuit must detour in bending, or add other extension wire in order to improve performance and make integral body be tending towards complexity and integration density reduces, form waste, in practice, these two kinds of problems all are difficult to solve.

Fundamental purpose of the present invention promptly in the disappearance of improving above-mentioned prior art, provides a kind of high speed, high density and low consumpting power read-only memory, particularly utilizes the interval selection technology, and good layout is saved the mask read-only memory of circuit area.

High-density mask type read-only memory of the present invention comprises:

Between storage portions, each interval is made up of many memory cell transistors;

The interval selection circuit is to be made of many MOS (metal-oxide-semiconductor) memory, and per three MOS (metal-oxide-semiconductor) memory form a selector switch unit;

The bit line metal connecting line, the transistor of using by contact hole and switch connects each interval;

The virtual ground metal connecting line, the transistor of using by contact hole and switch connects each interval;

The word line polysilicon conductor, the transistorized grid of control memory cell;

Local line N buried regions is as the transistorized source electrode of memory cell or grid and line;

The interval selection polysilicon conductor, whether the conducting between control interval and bit line, the virtual ground.

The present invention is owing to comprise that many memories are interval, utilize again between interval selection choice of technology given zone, so reduced bit-line load, thereby reduce consumed power, improve reading speed, in addition, constitute the MOS (metal-oxide-semiconductor) memory common grid of interval selection switch, therefore improve integration density greatly.

Description of drawings:

Fig. 1 is existing read-only memory wiring diagram.

Fig. 2 is existing read-only memory wiring diagram.

Fig. 3 is the wiring diagram of read-only memory of the present invention.

Fig. 4 is the layout of read-only memory of the present invention.

Shown in Figure 1 is the design of present existing read-only memory, can see wherein to have especially and live stored data district (ROM DATA AREA) to show difference with wire frame, also adopted the interval selection technology in this circuit, for example M10, M11, M12 and four transistors of M13 of other configuration in the stored data district promptly are to establish for reaching the interval selection function.This circuit disadvantage is that its bit line (BIT LINE) must be crooked on layout with virtual ground (VIRTUAL GROUND), is the example that Typical Route influences layout; In addition, elements such as M10, M11, M12, M13 are to utilize traditional LOCOS manufacturing process, expend area.

Shown in Figure 2 also is design at present commonly used, and it must crooked shortcoming improve metal connecting line in Fig. 1 circuit, but additionally add left and right (R, L) the selection circuit just can reach and be correctly decoded, still be inconvenient.

Fig. 3 is a wiring diagram of the present invention, can see obviously that bit line (BIT LINE) and virtual ground (VIRTUAL GROUND) be linear pattern, and in addition bending of situation does not as shown in Figure 1 have to select circuit about shown in Figure 2 adding yet.In the present invention, the interval selection circuit also is positioned at stored data district (ROM DATA AREA) block (BLOCK A as shown, B) other, by interval selection (BLOCK SELECT) S0, S1, the selected interval of S2, S3, with the transistor that constitutes selector switch (MA～MD, M0～M4, M9～M13) decision obtains data, observes its inside in detail:

1, bit line metal connecting line, the transistor of using by contact hole (CONTACT) and switch connects each interval;

2, virtual ground metal connecting line, the transistor of using by contact hole and switch connects each interval;

3, word line polysilicon (POLY-SILICON) conductor, the transistorized grid of control memory cell (MEMORYCELL);

4, local line (LOCAL INTERCONNECTOR) N buried regions is as the transistorized source electrode of memory cell or grid and line;

5, interval selection polysilicon conductor, be used between control interval and bit line, the virtual ground conducting whether;

6, the P ion is implanted (CODE IMP), is used for adjusting transistorized cut-off voltage (THRE-SHOLD VOLTAGE), makes transistor be not conducting under normal operation.

In the present invention, the mode of reading of data (DATA) is: select an interval (BLOCK) earlier, be that a certain interval selection line (BLOCK SELECT) is noble potential, all the other are electronegative potential, a word line (WORD LINE) is a noble potential then, so data can be seen through bit line (BIT LINE) and send.Be described as follows with example, still with reference to the circuit of figure 3:

(1)S0＝HIGH， S1＝S2＝S3＝LOW；

W0＝HIGH， W1～W15＝LOW；

BIT0 and VG0 are respectively the bit line and the ground wire of selection;

At this moment, S0=HIGH, L1, L2 are connected conducting with BIT0;

L3, L4 are connected conducting with VG0;

W0=HIGH, the drain electrode of M5 (DRAIN) is via L2, M1, MB and BIT0 conducting,

The source electrode of M5 (SOURCE) is via L3, MA and VG0 conducting;

So the stored data of M5 can be taken out smoothly.

(2)S1＝HIGH， S0＝S2＝S3＝LOW；

W1＝HIGH， W0，W2～W15＝LOW；

BIT0 and VG0 are respectively the bit line and the ground wire of selection;

At this moment, S1=HIGH, L0, L1 are connected conducting with BIT0;

L2, L3 are connected conducting with VG0;

W1=HIGH, the drain electrode of M8 (DRAIN) is via L1, MC and BIT0 conducting,

The source electrode of M8 (SOURCE) is via L2, M11, MD and VG0 conducting;

So the stored data of M8 can be taken out smoothly by BIT0.

Figure 4 shows that the layout of circuit of the present invention, note constituting transistor MB, M0, the M1 common grid of selector switch near the BIT0 of the left side, save element area occupied on wafer, other transistor that constitutes selector switch also is a same case, therefore, has improved device density.

In sum, the ingenious interval selection technology of utilizing of the present invention not only reduces the load on the bit line, improves reading speed; Also utilize simultaneously the improvement of layout to save the element area, improve integration density; More, smooth formula ion can improve its function effectively because implanting the manufacturing process of insulation.

Claims

1, a kind of high-density mask type read-only memory wherein is made up of many memory cell transistors between each storage portions; It is characterized in that described high-density mask type read-only memory comprises:

2, mask type read-only memory as claimed in claim 1, wherein the MOS (metal-oxide-semiconductor) memory of interval selection circuit is implanted by the P ion, adjusts transistorized cut-off voltage, makes transistor be not conducting in normal working conditions.

3, the read-only memory bank of mask-type as claimed in claim 1, wherein in the interval selection circuit, the shared same grid of three MOS (metal-oxide-semiconductor) memory of each selector switch unit.