CN104078374B - 半导体器件的导线焊接点强化方法 - Google Patents
半导体器件的导线焊接点强化方法 Download PDFInfo
- Publication number
- CN104078374B CN104078374B CN201410308014.XA CN201410308014A CN104078374B CN 104078374 B CN104078374 B CN 104078374B CN 201410308014 A CN201410308014 A CN 201410308014A CN 104078374 B CN104078374 B CN 104078374B
- Authority
- CN
- China
- Prior art keywords
- wire
- fastener
- pad
- lead
- framework lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/48997—Reinforcing structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/85951—Forming additional members, e.g. for reinforcing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Manufacturing Of Electrical Connectors (AREA)
Abstract
本发明提供一种半导体器件的导线焊接点强化方法,在框架内引线的表面的焊接区焊接导线;在所述框架内引线与所述导线的焊接点处跨接压固件,使压固件的中部向框架内引线的一侧紧压导线,并将压固件位于导线两侧的部分与框架内引线进行焊接固定。通过在导线的焊接点处设置压固件,来将导线向框架内引线的一侧压紧。采用此结构改善了框架内引线正面跟包封塑封料之间的界面结合,在分层向导线焊接点延伸过程中,只有压固件的焊点因分层延伸而彻底剥离后才会继续向导线的焊接点延伸,故采用此结构可以预防和改善导线焊接点剥离。
Description
技术领域
本发明涉及半导体器件封装技术领域,尤其涉及一种半导体器件的导线焊接点强化方法。
背景技术
在半导体功率器件封装过程中,主要使用铝线、铝带等导线将芯片和引线框架的框架内引线之间实现有效焊接,以满足功率器件工作时的大电压、大电流等高电性能要求。铝线键合后如图1、图2所示,包括:用以散热和承载芯片2的框架载片台1;用以电连结的框架内引线3;用以连结芯片2与框架内引线3的铝线4;用以将芯片2粘接在框架载片台1的装片胶6。
由于功率产品在工作时器件内部温度较高、有时外部工作环境也比较恶劣,要求铝线4跟框架内引线3之间的焊接可靠性比较高,但是在功率产品可靠性中、实际应用时还是会因为热应力、湿气、过程质量控制的波动等使铝线4跟框架内引线3之间产生剥离,导致产品的电参数、功能失效。针对此失效,业内虽然通过键合参数、钢嘴结构、材料、过程分层控制等方面改善焊接可靠性,但是有时候还会出现铝线4跟框架内引线之间的失效,后继再改善的工艺条件比较有限。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明提供一种半导体器件的导线焊接点强化方法,
在框架内引线的表面的焊接区焊接导线;
在所述框架内引线与所述导线的焊接点处跨接压固件,使所述压固件的中部向所述框架内引线的一侧紧压所述导线,并将所述压固件位于所述导线两侧的部分与所述框架内引线进行焊接固定。
本发明提供的上述方案,通过在导线的焊接点处设置压固件,来将导线向框架内引线的一侧压紧。采用此结构改善了框架内引线正面跟包封塑封料之间的界面结合,这种界面结合因为压固件的较好延展性偏向柔性,可以缓解和阻挡框架内引线边缘分层向导线与框架内引线的焊接点方向扩展,在分层向导线与框架内引线的焊接点延伸过程中,压固件与框架内引线的焊点首先阻挡分层的进一步向内延伸,只有压固件的焊点因分层延伸而彻底剥离后才会继续向导线的焊接点延伸,故采用此结构可以预防和改善导线焊接点剥离。
附图说明
参照下面结合附图对本发明实施例的说明,会更加容易地理解本发明的以上和其它目的、特点和优点。附图中的部件只是为了示出本发明的原理。在附图中,相同的或类似的技术特征或部件将采用相同或类似的附图标记来表示。
图1为现有技术的结构示意图;
图2是图1的A-A剖面图;
图3为实施本发明实施例提供的半导体器件的导线焊接点强化方法的加工过程示意图;
图4为实施本发明实施例提供的半导体器件的导线焊接点强化方法获得的半导体器件的示意图;
图5为图4的B-B剖面图;
图6为本发明实施例提供的焊接区一导线两并排压固件的结构示意图;
图7为本发明实施例提供的焊接区一导线两交叉压固件的结构示意图;
图8为本发明实施例提供的焊接区两并排导线两并排压固件的结构示意图;
图9为本发明实施例提供的焊接区两并排导线两交叉压固件的结构示意图;
图10为本发明实施例提供的焊接区两并排导线一铝带压固件的结构示意图;
图11为本发明实施例提供的焊接区两并排导线两并排铝带压固件的结构示意图。
具体实施方式
下面参照附图来说明本发明的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。
如图3所示,本发明实施例提供的半导体器件的导线焊接点强化方法,在框架内引线3的表面的焊接区焊接导线4;在框架内引线3与导线4的焊接点处跨接压固件5,使压固件5的中部向框架内引线3的一侧紧压导线4,并将压固件5位于导线两侧的部分与框架内引线5进行焊接固定。
在本发明技术方案中,根据需要,压固件5可以设置一个或多个,导线4可以是一根或多根,在导线为多根时,各导线优选为并排设置。
本发明提供的上述方案,通过在导线4的焊接点处设置压固件5,来将导线4向框架内引线3的一侧压紧。采用此结构改善了框架内引线3正面跟包封塑封料之间的界面结合,这种界面结合因为压固件5的较好延展性偏向柔性,可以缓解和阻挡框架内引线3边缘分层向导线4与框架内引线3的焊接点方向扩展,在分层向导线4与框架内引线3的焊接点延伸过程中,压固件5与框架内引线3的焊点首先阻挡分层的进一步向内延伸,只有压固件5的焊点因分层延伸而彻底剥离后才会继续向导线4的焊接点延伸,故采用此结构可以预防和改善导线焊接点剥离。
如图4、图5所示,采用本发明实施例提供的半导体器件的导线焊接点强化方法获得的半导体器件,包括框架内引线3,框架内引线3的表面具有焊接区,焊接区焊接有导线4,导线4在框架内引线3和芯片2之间至少通过两个焊点焊接固定,焊点自导线4的端部沿导线4的延伸方向设置;导线4焊接点处跨设有压固件5,压固件5的中部向框架内引线3的一侧紧压导线4,压固件5位于导线4两侧的部分与框架内引线3焊接固定。
实际使用中,该半导体器件例如但不限于功率器件,功率器件包括框架载片台1,框架载片台1上固定连接有芯片2,可以采用装片胶6将芯片2粘接在框架载片台1上,导线4远离框架内引线3的一端与芯片2焊接。导线4另一端通过上述结构连接在焊接区。
另外,需要指出的是,本文所指的焊接点处,可以是指一个焊点,也可以是多个焊点构成的区域,焊接点为自导线端部算起的由焊接工具通过超声、挤压等方式产生形变而粘结在框架内引线3表面的部分。
实际使用中,压固件位于导线两侧的部分均至少通过一个焊点,与框架内引线进行焊接固定。该焊点的数量可以根据框架内引线的空间大小而定。
另外,压固件的焊点形状为挤压形成的梯形。压固件的焊点采用挤压形成的梯形形状,与压固件的线径相比,梯形能够增加接触面积,进而使焊接更牢固。
进一步地,焊接点处跨设有两个压固件5,两个压固件5并排设置或交叉设置。
焊接点处跨设有至少两个压固件。作为其中一种实现方式,如图6所示,框架内引线3上焊接点处跨设了两个并排设置的压固件5。作为另外一种实现方式,如图7所示,框架内引线3上焊接点处跨设了两个交叉设置的压固件5。此外,需要说明的是,除了上述列举的两种实现方式外,被压固的导线和压固件之间还可以采用其它形式。例如,可以是单跟单组合(一根导线与一个压固件的组合)、多跟多组合(多根导线与多个压固件的组合),单跟多组合(一根导线与多个压固件的组合)、多跟单组合(多根导线与一个压固件的组合),组合方式根据框架内引线空间大小、导线尺寸、压固件尺寸等确定组合数量的匹配。
通过设置两个压固件5来对导线4实施下压,连接的可靠性高,有利于提升抗剥离能力。
进一步地,框架内引线3的同一焊接区焊接有两条导线4,两条导线4并排设置,同一压固件5跨设在两条导线之上。
如图8所述,框架内引线3的同一焊接区焊接有两条导线4,两条导线4并排设置,焊接点处跨设两个并排的压固件5,且同一压固件5跨设在两条导线4之上。
如图9所示,框架内引线3的同一焊接区焊接有两条导线4,两条导线4并排设置,焊接点处跨设两个交叉的压固件5,且同一压固件5跨设在两条导线4之上。当然,在框架内引线3的同一焊接区焊接有多条导线时,同一压固件5可以同时跨设在多条导线4之上。
进一步地,压固件5为铝线或铝带。如图4-图7所示,压固件5均采用的是铝线。
另外,压固件5还可以采用铝带。
如图10所示,框架内引线3的同一焊接区焊接有两条导线4,两条导线4并排设置,焊接点处跨设一条压固件(该压固件为铝带)7,该压固件7跨设在两条导线4之上。
如图11所示,框架内引线3的同一焊接区焊接有两条导线4,两条导线4并排设置,焊接点处跨设两个并排的压固件(该压固件为铝带)7,且同一压固件7跨设在两条导线4之上。当然,框架内引线3的同一焊接区还可以焊接有多条导线4,多条导线4并排设置,焊接点处跨设三个以上并排设置的压固件7,且同一压固件7同时跨设在多条导线4之上。在设置的压固件7的数量大于三个时,压固件7优选并排设置,当然也可以采用交叉的方式设置。
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。
Claims (5)
1.一种半导体器件的导线焊接点强化方法,其特征在于,
在框架内引线的表面的焊接区焊接导线;
在所述框架内引线与所述导线的焊接点处跨接压固件,使所述压固件的中部向所述框架内引线的一侧紧压所述导线,并将所述压固件位于所述导线两侧的部分与所述框架内引线进行焊接固定;
所述焊接点处跨设有至少两个压固件,两个所述压固件并排设置或交叉设置。
2.根据权利要求1所述的半导体器件的导线焊接点强化方法,其特征在于,
所述框架内引线的同一所述焊接区焊接有至少两条所述导线,两条所述导线并排设置,同一所述压固件跨设在两条或以上所述导线之上。
3.根据权利要求1所述的半导体器件的导线焊接点强化方法,其特征在于,所述压固件为铝线或铝带。
4.根据权利要求1所述的半导体器件的导线焊接点强化方法,其特征在于,所述压固件位于所述导线两侧的部分均至少通过一个焊点,与所述框架内引线进行焊接固定。
5.根据权利要求4所述的半导体器件的导线焊接点强化方法,其特征在于,所述压固件的所述焊点形状为挤压形成的梯形。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410308014.XA CN104078374B (zh) | 2014-06-30 | 2014-06-30 | 半导体器件的导线焊接点强化方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410308014.XA CN104078374B (zh) | 2014-06-30 | 2014-06-30 | 半导体器件的导线焊接点强化方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104078374A CN104078374A (zh) | 2014-10-01 |
CN104078374B true CN104078374B (zh) | 2017-01-04 |
Family
ID=51599561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410308014.XA Active CN104078374B (zh) | 2014-06-30 | 2014-06-30 | 半导体器件的导线焊接点强化方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104078374B (zh) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192588A (ja) * | 1990-11-27 | 1992-07-10 | Sony Corp | プリント基板における一方の面の回路パターンと他方の面の回路パターンとの接続方法 |
WO2004077901A2 (de) * | 2003-02-27 | 2004-09-10 | Endress+Hauser Gmbh+Co. Kg | Leiterplatte und verfahren zur fixierung von bedrahteten bauteilen auf der leiterplatte |
JP2005252006A (ja) * | 2004-03-04 | 2005-09-15 | Sumitomo Electric Ind Ltd | 集積回路モジュール |
JP2013058553A (ja) * | 2011-09-07 | 2013-03-28 | Nikon Corp | シールド付き信号線及びこれに用いられる片面フレキシブル基板 |
-
2014
- 2014-06-30 CN CN201410308014.XA patent/CN104078374B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04192588A (ja) * | 1990-11-27 | 1992-07-10 | Sony Corp | プリント基板における一方の面の回路パターンと他方の面の回路パターンとの接続方法 |
WO2004077901A2 (de) * | 2003-02-27 | 2004-09-10 | Endress+Hauser Gmbh+Co. Kg | Leiterplatte und verfahren zur fixierung von bedrahteten bauteilen auf der leiterplatte |
JP2005252006A (ja) * | 2004-03-04 | 2005-09-15 | Sumitomo Electric Ind Ltd | 集積回路モジュール |
JP2013058553A (ja) * | 2011-09-07 | 2013-03-28 | Nikon Corp | シールド付き信号線及びこれに用いられる片面フレキシブル基板 |
Also Published As
Publication number | Publication date |
---|---|
CN104078374A (zh) | 2014-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103779340A (zh) | 半导体器件和制造半导体器件的方法 | |
CN103824834A (zh) | 一种具有改进型封装结构的半导体器件及其制造方法 | |
CN102576698A (zh) | 具有增强的接地接合可靠性的引线框封装 | |
CN100413043C (zh) | 半导体器件的制造方法 | |
CN104505375A (zh) | 半导体封装结构 | |
CN105870115A (zh) | 一种多芯片3d封装结构 | |
CN104078374B (zh) | 半导体器件的导线焊接点强化方法 | |
CN105140205B (zh) | 一种双面散热的半导体叠层封装结构 | |
CN114783895A (zh) | 一种铝带焊线在封装体内的应用方法及制得的半导体器件 | |
CN204011404U (zh) | 半导体器件的导线焊接点强化结构 | |
CN104064540B (zh) | 半导体器件的导线焊点强化结构 | |
CN204809212U (zh) | 一种半导体封装结构 | |
CN104064485B (zh) | 半导体器件的导线焊点强化方法 | |
CN107180809A (zh) | 半导体封装结构及其封装方法 | |
JP5939185B2 (ja) | 半導体装置及びその製造方法 | |
CN207122761U (zh) | 一种led连体支架灯 | |
CN104103619B (zh) | 半导体功率器件的导线强化焊接结构 | |
CN104157430A (zh) | 一种变压器的下铁轭屏蔽结构及其制造工艺 | |
JP2013242991A (ja) | 電線の接合構造 | |
CN104952857B (zh) | 一种无载体的半导体叠层封装结构 | |
CN110224055A (zh) | 一种贴片式发光二极管的封装结构及封装工艺 | |
CN203617280U (zh) | 便于打丝的引线框架 | |
CN201527975U (zh) | 一种铜线结构的功率晶体管 | |
CN104064484B (zh) | 半导体功率器件的强化导线焊接点的方法 | |
CN102456656A (zh) | 芯片封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |