CN104078324B - Stack nano wire manufacture method - Google Patents
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- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
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- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention discloses one kind to stack nano wire manufacture method, including：Step a, forms hard mask on substrate；Step b, etched substrate form first groove and fin；Step c, side wall is formed in fin side；Step d, fin is etched, in side wall second groove formed below；Step e, fin is post-processed, formed and stack nano wire.According to the stacking nano wire manufacture method of the present invention, mixing uses anisotropy and isotropic etching, and selective etch is realized under the side wall protection that side wall is formed, and which thereby enhances the precision for stacking nano wire, is advantageous to device miniaturization.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, more particularly to a kind of manufacture method for stacking nano wire.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device（FinFET or Tri-gate）It is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can suppress short compared with traditional single grid body Si or SOI MOSFET
Channelling effect（SCE）And leakage causes induced barrier to reduce（DIBL）Effect, there is lower junction capacity, can realize that raceway groove is gently mixed
It is miscellaneous, it can obtain about 2 times of driving current by setting the work function of metal gates come adjusting threshold voltage, reduce
For effective gate oxide thickness（EOT）Requirement.And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.
In loopful in the manufacturing process of nano wire multi-gate device, it is known that a kind of method it is as follows：Formed on a si substrate
Hard mask, using SF6The anisortopicpiston of etching gas be dry-etched in hard mask lower substrate formed it is slightly interior
Recessed first groove, backing material is left between relative first groove and forms fin structure；Using high density CxF（Carbon fluorine ratio
It is higher）The plasma etching of etching gas, on substrate and first groove side wall forms passivation layer；SF again6Respectively to different
Property etching, remove passivation layer on substrate, leave the passivation layer of first groove madial wall；SF6Isotropic etching, continue etching lining
Bottom, in first groove second groove formed below；The like, form multiple grooves and fin structure；Between oxidation groove
Fin structure, oxide is removed, leaves nano-wire array.This method technology controlling and process is difficult, and nanowire density is smaller, uniformity compared with
Difference.
Method includes known to another kind：Si and Ge/SiGe overlapping epitaxial layer is formed epitaxially one after the other on soi substrates,
Hard mask layer is formed in top layer, etching forms grid lines, and selective etch removes the Ge/SiGe layers between adjacent S i layers, stayed
Lower Si nano wires.This method is limited to Ge/SiGe bed boundarys poor performance, and process costs are high, it is difficult to popularize.
Another known method is included to substrate alternately anisotropy and isotropic etching, in the substrate shape
Into the groove of multiple Σ shapes sections.The method for forming the groove of Σ shape sections is, for example, to utilize Si substrates in the etching liquids such as TMAH
110 face etch rates are more than 100 face speed so that etching is terminated on selected crystal face.However, this method is difficult control groove
（Nano wire）The homogeneity of shape in vertical direction, such as the upper extreme point of groove and lower extreme point be not on vertical line（On groove
Portion's etching is very fast so that bottom is wider than top）, it is not easy to form nano wire stacked structure.
The content of the invention
From the above mentioned, inexpensive, efficient nano wire manufacture method can be stacked it is an object of the invention to provide a kind of.
Therefore, the invention provides one kind to stack nano wire manufacture method, including：Step a, formed on substrate and covered firmly
Mould；Step b, etched substrate form first groove and fin；Step c, side wall is formed in fin side；Step d, fin is etched,
In side wall second groove formed below；Step e, fin is post-processed, formed and stack nano wire.
Wherein, repeat step b to step d, the fin array that multiple fins groups stacked on top of one another are formed is formed.
Wherein, anisotropic etching is used in step b, the first groove of formation has vertical sidewall.
Wherein, step c further comprises：On substrate and fin side forms dielectric layer；Anisotropic etching medium
Layer, dielectric layer on substrate is removed, dielectric layer is only left in fin side and forms side wall.
Wherein, forming the method for dielectric layer includes deposition and/or thermal oxide.
Wherein, isotropic etching is used in step d, the second groove of formation has female parts.
Wherein, isotropic etching method includes dry etching and/or wet etching.
Wherein, the remainder of fin, or second groove break-through are remained between the second groove in step d to cause
Fin is separated from each other.
Wherein, step e further comprises：Oxide layer is formed on fin surface；Removing oxide layer is removed, exposes fin.
Wherein, step e includes：Anneal under an atmosphere of hydrogen so that fin mellow and fullization, which is formed, stacks nano wire.
According to the stacking nano wire manufacture method of the present invention, mixing uses anisotropy and isotropic etching, in side wall
Selective etch is realized under the side wall protection of formation, the precision for stacking nano wire is which thereby enhanced, is advantageous to device miniaturization.
Brief description of the drawings
Describe technical scheme in detail referring to the drawings, wherein：
Fig. 1 to Fig. 9 is the cut-away view according to each step of manufacture method of the present invention；And
Figure 10 is the indicative flowchart according to the manufacture method of the present invention.
Embodiment
Referring to the drawings and schematical embodiment is combined to describe the feature of technical solution of the present invention and its skill in detail
Art effect, disclosing can low cost, efficient stacking nano wire manufacture method.It is pointed out that similar reference table
Show similar structure, term use herein " first ", " second ", " on ", " under " etc. can be used for modifying various devices
Structure or manufacturing process.These modifications do not imply that the space, secondary of modified device architecture or manufacturing process unless stated otherwise
Sequence or hierarchical relationship.
First, the flow chart below with reference to Figure 10 and referring to figs. 1 to Fig. 9 diagrammatic cross-section come describe in detail according to
Each step of method, semi-conductor device manufacturing method of the present invention.
As shown in figure 1, hard mask 2 is formed on substrate 1.Substrate 1 is provided, substrate 1 is reasonable according to device application needs
Selection, it may include monocrystalline silicon（Si）, silicon-on-insulator（SOI）, monocrystal germanium（Ge）, germanium on insulator（GeOI）, strained silicon
（Strained Si）, germanium silicon（SiGe）, or compound semiconductor materials, such as gallium nitride（GaN）, GaAs（GaAs）, phosphorus
Change indium (InP), indium antimonide（InSb）, and carbon-based semiconductors such as graphene, SiC, carbon nanotube etc..Preferably, substrate 1 is
Body Si is used to make large scale integrated circuit so as to compatible with CMOS technology.It is highly preferred that substrate 1 is（100）Crystal face.
It is conventional by LPCVD, PECVD, UHVCVD, HDPCVD, thermal oxide, chemical oxidation, MBE, ALD, evaporation, sputtering etc.
Method, hard mask layer is formed on substrate 1, and form hard mask figure 2 using already known processes photoetching/etching.The material of hard mask 2
Material can be silica, silicon nitride, silicon oxynitride and combinations thereof.
As shown in Fig. 2 etched substrate 1 forms first groove 1G, the remainder of substrate 1 that the lower section of hard mask 2 leaves is formed
First fin 1F.Etching is preferably anisotropic etching, using cause first groove 1G side wall as（Substantially）Vertically.Anisotropy
Etching is preferably fluorine base gas plasma dry etch, in order to by controlling etching condition accurately to control etching depth dE,
And then control final nanowire height/thickness.Preferably, etching make it that first groove 1G side wall is（110）Face and（Substantially）
Vertical substrates, and the surface of substrate 1 remains as（100）Face.
As shown in figure 3, form dielectric layer 3 on substrate 1, fin 1F and first groove 1G surfaces.Can by LPCVD,
The methods of PECVD, HDPCVD, UHVCVD, MBE, ALD, deposits, and can also pass through thermal oxide（Such as heated in high temperature furnace）, change
Learn oxidation（Such as immerse in the deionized water containing ozone）Carry out oxidation growth and form dielectric layer 3.The material of dielectric layer 3 is preferred
Ground is different from hard mask 2, substrate 1, can be selected from silica, silicon nitride, silicon oxynitride, high-g value, and wherein high-g value includes
But it is not limited to nitride（Such as SiN, AlN, TiN）, metal oxide（Predominantly subgroup and lanthanide element oxide, example
Such as MgO, Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3）, nitrogen oxides（Such as HfSiON）；Perovskite Phase
Oxide（Such as PbZrxTi1-xO3（PZT）、BaxSr1-xTiO3（BST））.In a preferred embodiment of the invention, dielectric layer 3
The silica formed for thermal oxidation technology, because thermal oxidation technology can to deposit between the dielectric layer 3 of silica and the substrate 1 of silicon
It is poor in obvious growth rate, be advantageous to improve the conformality of dielectric layer 3.Dielectric layer 3 completely covers substrate 1, fin 1F,
One groove 1G surface.
As shown in figure 4, selective etch removes the certain media layer 3 on the surface of substrate 1, only in fin 1F（First groove 1G）
Side member-retaining portion dielectric layer 3, form fin side wall 3S.Lithographic method is preferably anisotropic etching, such as plasma
Dry etching, fluorine base gas-such as carbon fluorine base gas can be selected（CxHyFz）Or chlorine-based gas-such as Cl2And/or
HCl。
As shown in figure 5, continue etched substrate 1, in fin 1F second groove 1G ' formed below.Due to fin side wall 3S's
Protection, etch influences smaller for fin 1F, but forms the second groove 1G ' of indent thereunder.Etching herein is excellent
Choosing uses isotropic etching, such as dry etching and/or wet etching, can be used alone, can also be used in combination（Example
Such as first dry etching vertical direction, then wet etching side）.For dry etching, such as from RIE, carbon fluorine can be selected
Base gas simultaneously adjusts proportioning, makes it have isotropic etching.For wet etching, TMAH can be selected
（TMAH）Or KOH is corroded with the substrate 1 for Si materials.Second groove 1G ' profile morphology need not as shown in Figure 5 only
For arc-shaped, but rectangle, trapezoidal, inverted trapezoidal, Σ shapes can be included（Multistage broken line is connected, recessed towards channel region, namely ditch
Width in the middle part of groove is greater than the width of top and/or bottom）, D-shaped（1/2 curve, curve include circle, oval, hyperbola）、C
Shape（More than 1/2 curve, curve includes circle, oval, hyperbola）.In an embodiment of the invention, its hollow depth is preferably
1/3 of width less than or equal to fin 1F, for example, 1/4, namely second groove not break-through.
As shown in fig. 6, it is similar with technique shown in Fig. 2~Fig. 4 or repeat these processes, first carry out anisotropic etching
Substrate is in fin 1F another group of fin 1F ' formed below and another group of first groove 1G, then preferably to use thermal oxidation method shape
Into another dielectric layer 3, anisotropic etching dielectric layer 3 forms another fin side wall 3S '（Second group of fin side wall）.
As shown in fig. 7, Fig. 6 process or Fig. 2 to Fig. 4 process are repeated, 3rd group formed below in second group of fin
Fin, and correspondingly form the 3rd group of fin side wall 3S.
Above each group fin will be used to form nano wire, pass through second groove 1G ' institutes between neighbouring two groups of fins
The narrow 1C of clamping is connected.
As shown in figure 8, after foring multigroup fin 1F and narrow connected component 1C, process shown in reference picture 5, formed
Last group of second groove 1G '.Lithographic method can be dry etching and/or wet etching, formed second groove 1G ' have to
Interior is recessed.
As shown in figure 9, post-processed to form nano wire storehouse.
A kind of conventional method includes, using thermal oxide, the method for chemical oxidation, being formed and being aoxidized on fin structure 1F surfaces
Layer（Such as silica, it is not shown）, and cause remaining fin structure 1F to form nano wire 1NW.Then, the oxidation on surface is removed
Layer, leaves nano wire 1NW.Minimizing technology is, for example, that whole device wafer immerses HF base corrosive liquids（DHF or dBOE（Sustained release is carved
Lose agent））, the oxide layer of erosion removal silica material, only leave multiple nano wire 1NW and stack the grid line array formed.
Preferably, further can be annealed in atmosphere of hydrogen so that remaining ground fin structure 1F surfaces mellow and fullization, form receiving for circle
Rice noodles 1NW.
In addition, for the second groove 1G ' of different profile morphologies, such as when second groove 1G ' hollow depths continue
Increase to cause relative second groove 1G ' break-through when, fin 1F form prism-shaped, therefore can without using method for oxidation come
Fin is thinned, but the mellow and full nano wire 1NW for turning to circle in prismatic fin 1F surfaces is directly caused using hydrogen annealing process.
Preferably, the last hard mask 2 at the top of also further erosion removal, silicon nitride is removed for example with hot phosphoric acid corrosion
The hard mask 2 of material.
It is worth noting that, the fin, nano wire shown in figure are rectangular section, can essentially be different according to technique
And there are other various rational shapes, such as circle, ellipse, parabola, hyperbola, triangle, trapezoidal, rhombus and its group
Close.
According to the stacking nano wire manufacture method of the present invention, mixing uses anisotropy and isotropic etching, in side wall
Selective etch is realized under the side wall protection of formation, the precision for stacking nano wire is which thereby enhanced, is advantageous to device miniaturization.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art could be aware that need not
Depart from the scope of the invention and various suitable changes and equivalents are made to device architecture.In addition, can by disclosed teaching
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacture method is by all embodiments including falling within the scope of the present invention.
Claims (9)
1. one kind stacks nano wire manufacture method, including：
Step a, forms hard mask on substrate；
Step b, etched substrate form first groove and fin；
Step c, side wall is formed in fin side；
Step d, fin is etched, in side wall second groove formed below；
Step e, fin is post-processed, formed and stack nano wire；
Wherein, repeat step b to step d, the fin array that multiple fins groups stacked on top of one another are formed, above-mentioned repetitive process are formed
The side wall that middle step c is formed is retained in fin side.
2. stack nano wire manufacture method as claimed in claim 1, wherein, use anisotropic etching in step b, the of formation
One groove has vertical sidewall.
3. nano wire manufacture method is stacked as claimed in claim 1, wherein, step c further comprises：On substrate and fin side
Face forms dielectric layer；
Anisotropic etching dielectric layer, dielectric layer on substrate is removed, dielectric layer is only left in fin side and forms side wall.
4. nano wire manufacture method is stacked as claimed in claim 3, wherein, forming the method for dielectric layer includes deposition and/or hot oxygen
Change.
5. stack nano wire manufacture method as claimed in claim 1, wherein, use isotropic etching in step d, the of formation
Two grooves have female parts.
6. as claimed in claim 5 stack nano wire manufacture method, wherein, isotropic etching method include dry etching and/or
Wet etching.
7. nano wire manufacture method is stacked as claimed in claim 1, wherein, remain with fin between the second groove in step d
Remainder, or second groove break-through is to cause fin to be separated from each other.
8. nano wire manufacture method is stacked as claimed in claim 1, wherein, step e further comprises：Formed and aoxidized on fin surface
Layer；Removing oxide layer is removed, exposes fin.
9. nano wire manufacture method is stacked as claimed in claim 1, wherein, step e includes：Anneal under an atmosphere of hydrogen so that fin
Piece mellow and fullization, which is formed, stacks nano wire.
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| CN104609360B (en) * | 2013-11-05 | 2016-06-29 | 中国科学院微电子研究所 | A kind of forming method of nano wire and array |
| CN105742175B (en) * | 2014-12-11 | 2019-09-24 | 中国科学院微电子研究所 | The method for forming nano-wire array |
| CN105742232B (en) * | 2014-12-11 | 2019-01-18 | 中国科学院微电子研究所 | The method for forming nano-wire array |
| CN105742231B (en) * | 2014-12-11 | 2020-04-24 | 中国科学院微电子研究所 | Method for forming nanowire array |
| CN105742153B (en) * | 2014-12-11 | 2019-09-24 | 中国科学院微电子研究所 | The method for forming cascade nano wire |
| CN105742239B (en) * | 2014-12-11 | 2018-12-11 | 中国科学院微电子研究所 | The method for forming nano-wire array |
| CN105719961B (en) * | 2016-02-04 | 2018-08-10 | 中国科学院微电子研究所 | Stack nano wire manufacturing method |
| CN105632916A (en) * | 2016-02-22 | 2016-06-01 | 国家纳米科学中心 | Etching method for variable-cross-section silicon holes and silicon channels |
| CN107437556A (en) * | 2016-05-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | GAA structures MOSFET forming method |
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| CN107910362A (en) * | 2017-11-17 | 2018-04-13 | 北京大学 | A kind of FinFET of anti-integral dose radiation and preparation method thereof |
| CN108565218A (en) * | 2017-12-14 | 2018-09-21 | 中国科学院微电子研究所 | Ring gate nano line field-effect transistor and preparation method thereof |
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| CN108470685B (en) * | 2018-03-30 | 2022-02-01 | 中国科学院微电子研究所 | Nanowire structure and manufacturing method thereof |
| US11367783B2 (en) * | 2018-08-17 | 2022-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing a semiconductor device |
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