CN104064533A - QFN packaging structure and method for double-face semiconductor device - Google Patents
QFN packaging structure and method for double-face semiconductor device Download PDFInfo
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- CN104064533A CN104064533A CN201410315879.9A CN201410315879A CN104064533A CN 104064533 A CN104064533 A CN 104064533A CN 201410315879 A CN201410315879 A CN 201410315879A CN 104064533 A CN104064533 A CN 104064533A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a QFN packaging structure for a double-face semiconductor device, and the structure comprises a chip and frame which is in butt-joint connection with the chip. A side edge of a contact surface of the chip with the frame is provided with a wide groove. The surface of the wide groove is covered by a glass passivation layer. A part, corresponding to the inner edge of the wide groove of the chip, of the frame is provided with an overflow groove with a certain width. The chip and the frame are bonded together through conducting resin, and the excess conducting resin is placed in the overflow groove. The invention also discloses a QFN packaging method for the double-face semiconductor device. According to the invention, the wide groove is disposed on the chip, and the overflow groove is disposed on the frame. The conducting resin can flow into the overflow groove during overflowing, thereby effectively solving a problem of short circuit during the overflowing of the conducting resin. The type of the conducting resin is Kyocera 2815A. When the double-face device serves as a power device, the method and device also can meet the demands of special working conditions of an instantaneous heavy current.
Description
Technical field
The invention belongs to semiconductor device design and manufacture field, specifically a kind of QFN encapsulating structure and method of two-sided semiconductor device.
Background technology
Along with design of electronic circuits is tending towards highly integrated, the encapsulation volume of device is required also to improve thereupon, traditional two-sided semiconductor device of paster type encapsulation such as button-shaped encapsulation, SMA/SMB/SMC cannot meet the Butut needs of high side circuitry Design PCB version gradually, and more flat, more small-sized packing forms demand is urgent.
Surrounding is current the most suitable wafer-level package form without pin Flat type packaged (QFN), but this encapsulation technology is mainly used in integrated antenna package at present, for the such power device of solid discharging tube inapplicable.Its main cause is with reference to Fig. 1, two-sided semiconductor device in the time of conducting resinl flash can with chip contact short circuit, thereby cause component failure; In addition, if this device is power device, the operating state that need to bear transient high-current, QFN can only use conducting resinl to carry out bonding die, and conventional conducting resinl cannot meet this performance need.
Summary of the invention
The application is according to the technical threshold in background technology, based on the existing encapsulation technology of QFN and appointed condition, designed, designed a kind of QFN encapsulating structure and method of two-sided semiconductor device.
Technical scheme is:
A QFN encapsulating structure for two-sided semiconductor device, the framework that comprises chip and dock with it, described chip is provided with sipes at the lateral edges of the contact-making surface of itself and framework, has glass passivation layer in sipes surface coverage; Described framework has the overflow launder of certain width in its position corresponding with the inner edge of chip sipes; Chip and framework are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder.
As preferred embodiment, the section of described sipes is arc, and its width is 90～110 μ m, is highly 30～50 μ m; The width of described overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes.
Preferably, described conducting resinl model is the 2815A of KYOCERA.
This encapsulating structure also comprises the first pin and the second pin, and as the arrangement of a kind of the first pin and the second pin, the first pin is connected with chip by wire respectively with the second pin.
As the arrangement of another kind of the first pin and the second pin, the first pin is connected with chip by wire, and the second pin is arranged on framework, is connected with chip by conducting resinl.
The QFN method for packing that disclosed herein as well is a kind of two-sided semiconductor device, its concrete steps are:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 90～110 μ m, is highly 30～50 μ m;
4,, at sipes surface-coated glass dust, carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, selection conducting resinl carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packaging routinely.
More excellent, the model of the conducting resinl in step c is selected the 2815A of KYOCERA.
Beneficial effect of the present invention:
The present invention arranges sipes structure on chip, and overflow groove structure is set on framework, and conducting resinl can flow into overflow launder in the time of flash, the short circuit problem while effectively having prevented conducting resinl flash;
It is the 2815A of KYOCERA that conducting resinl of the present invention is selected model, in the time that two-sided semiconductor device is power device, also can meet particular job state needs of transient high-current.
Brief description of the drawings
Fig. 1 is the QFN encapsulating structure schematic diagram of conventional two-sided semiconductor device.
Fig. 2 is the sipes structure side view of chip of the present invention.
Fig. 3 is the sipes structure vertical view of chip of the present invention.
Fig. 4 is the overflow groove structure end view of framework of the present invention.
Fig. 5 is the overflow groove structure vertical view of framework of the present invention.
Fig. 6 is QFN encapsulating structure schematic diagram of the present invention (the first pin arrangement mode).
Fig. 7 is QFN encapsulating structure schematic diagram of the present invention (the second pin arrangement mode).
Description of reference numerals:
1-chip; 2-sipes; 3-framework; 4-overflow launder; 5-Ji island; 6-the first pin; 7-the second pin.
Embodiment
Below in conjunction with accompanying drawing, the QFN encapsulating structure of a kind of two-sided semiconductor device of the present invention is described further, but protection scope of the present invention is not limited to this:
In conjunction with Fig. 2-Fig. 5, a kind of QFN encapsulating structure of two-sided semiconductor device, the framework 3 that comprises chip 1 and dock by base island 5 with it, described chip 1 is provided with sipes 2 at the lateral edges of the contact-making surface of itself and framework 3, has glass passivation layer in sipes 2 surface coverage; Described framework 3 has the overflow launder 4 of certain width in its position corresponding with the inner edge of the sipes 2 of chip 1; Chip 1 and framework 3 are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder 4.
The section of sipes 2 is arc, and its width is 90～110 μ m, is highly 30～50 μ m; The width of overflow launder 4 is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of the interior surrounding edge of sipes 2 of chip 1.
Conducting resinl model is the 2815A of KYOCERA.
In conjunction with Fig. 6, the QFN encapsulating structure of two-sided semiconductor device of the present invention also comprises that the first pin 6 and the second pin 7, the first pins 6 are connected with chip 1 by wire respectively with the second pin 7.
In conjunction with Fig. 7, the second arrangement of the present invention's the first pin 6 and the second pin 7, the first pin 6 is connected with chip 1 by wire, and the second pin 7 is arranged on framework 3, is connected with chip 1 by conducting resinl.
Below in conjunction with specific embodiment, the QFN method for packing of a kind of two-sided semiconductor device of the present invention is described, but protection scope of the present invention is not limited to this:
Embodiment 1:
The QFN encapsulation of solid discharging tube:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 90 μ m, is highly 30 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 150 μ m, groove depth 50 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packaging routinely.
Embodiment 2:
The QFN encapsulation of solid discharging tube:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 110 μ m, is highly 50 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 200 μ m, groove depth 60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packaging routinely.
Embodiment 3:
The QFN encapsulation of bidirectional trigger diode:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 100 μ m, is highly 40 μ m;
4, in sipes surface-coated glass dust (370 type), carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 175 μ m, groove depth 55 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, the selection 2815A of conducting resinl KYOCERA carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packaging routinely.
For checking conforming product rate of the present invention greatly improves, now take three contrast schemes (1, planar chip+without overflow launder framework+solid discharging tube; 2, band sipes isolating chip+without overflow launder framework+solid discharging tube; 3, planar chip+have overflow launder framework+bidirectional trigger diode) carry out experimental verification in conjunction with the scheme of three embodiment.Each contrast scheme and embodiment scheme are all carried out the small lot batch manufacture of 50 numbers, and statistics qualification rate is as following table:
| Sample batch | Qualification rate | Technical scheme |
| 1 | 0％ | Contrast scheme 1 |
| 2 | 16％ | Contrast scheme 2 |
| 3 | 12％ | Contrast scheme 3 |
| 4 | 94％ | Embodiment 1 |
| 5 | 89％ | Embodiment 2 |
| 6 | 92％ | Embodiment 3 |
Embodiment of the present invention gained qualification rate is very nearly the same with conventional paster encapsulation qualification rate, realized QFN and encapsulate the production in enormous quantities feasibility of two-sided semiconductor device." accurate QFN encapsulates two-sided semiconductor device " on contrast market, actual its is that thinner normal sintering formula paster encapsulates, and product thickness cannot be less than 1mm, and needs independent mold developing and production test equipment, and investment of production is huge.This programme is standard QFN encapsulation, can compatible existing various QFN sealed in unit, go into operation without increasing investment, and product thickness can be down to 0.7～0.8mm, and break through conventional sintering formula and encapsulated the unsurpassable 1mm limit of two-sided semiconductor device.
The present invention program has realized chip-scale (CSP) the QFN encapsulation of two-sided semiconductor device.Wafer-level package will become the development trend of integrated circuit from now on; in a large amount of wiring boards that use wafer-level package integrated circuit; the present invention program's product (the QFN encapsulation of solid discharging tube) will can be this type circuit provides high-power overvoltage protection, breaks away from due to high-power protection device being installed simultaneously and needs to increase the drawback of pcb board installing space.
Specific embodiment described herein is only to illustrate inventing spirit.Those skilled in the art can make various amendments or supplement or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present invention or surmount the defined scope of appended claims.
Claims (7)
1. a QFN encapsulating structure for two-sided semiconductor device, the framework that comprises chip and dock with it, is characterized in that described chip is provided with sipes at the lateral edges of the contact-making surface of itself and framework, has glass passivation layer in sipes surface coverage; Described framework has the overflow launder of certain width in its position corresponding with the inner edge of chip sipes; Chip and framework are bonding by conducting resinl, and excessive conducting resinl is placed in overflow launder.
2. the QFN encapsulating structure of a kind of two-sided semiconductor device according to claim 1, the section that it is characterized in that described sipes is arc, its width is 90～110 μ m, is highly 30～50 μ m; The width of described overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes.
3. the QFN encapsulating structure of a kind of two-sided semiconductor device according to claim 1, is characterized in that described conducting resinl model is the 2815A of KYOCERA.
4. according to the QFN encapsulating structure of any the two-sided semiconductor device described in claim 1-3, it is characterized in that it also comprises the first pin and the second pin, the first pin is connected with chip by wire respectively with the second pin.
5. according to the QFN encapsulating structure of any the two-sided semiconductor device described in claim 1-3, it is characterized in that it also comprises the first pin and the second pin, the first pin is connected with chip by wire, and the second pin is arranged on framework, is connected with chip by conducting resinl.
6. a QFN method for packing for two-sided semiconductor device, is characterized in that concrete steps are:
The preparation of a, chip:
1, technological process to phosphorus diffusion finishes routinely;
2, one side etching sipes domain, another side applies photoresist exposure protection, does not do to corrode;
3, wet etching sipes, its width is 90～110 μ m, is highly 30～50 μ m;
4,, at sipes surface-coated glass dust, carry out conventional glassivation operation;
5, chip metallization, forms electrode;
The preparation of b, framework: prepared framework has the overflow launder of certain width at the inner edge correspondence position of itself and chip sipes; The width of overflow launder is 150～200 μ m, groove depth 50～60 μ m, and in it, surrounding edge length is less than the long 100 μ m of surrounding edge in chip sipes;
C, selection conducting resinl carry out bonding die;
D, technological process is carried out key pressure, plastic packaging, is cut muscle, test, braid and packaging routinely.
7. the QFN method for packing of a kind of two-sided semiconductor device according to claim 1, is characterized in that the model of the conducting resinl in step c is selected the 2815A of KYOCERA.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410315879.9A CN104064533A (en) | 2014-07-03 | 2014-07-03 | QFN packaging structure and method for double-face semiconductor device |
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| CN201410315879.9A CN104064533A (en) | 2014-07-03 | 2014-07-03 | QFN packaging structure and method for double-face semiconductor device |
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Cited By (2)
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| CN104485287A (en) * | 2014-12-08 | 2015-04-01 | 宜兴市东晨电子科技有限公司 | Preparation method of novel QFN (Quad Flat No Lead) frame comprising overflow groove |
| CN104779224A (en) * | 2015-04-15 | 2015-07-15 | 江苏晟芯微电子有限公司 | QFN (Quad Fiat Nolead) packaging structure of power device |
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|---|---|---|---|---|
| CN104485287A (en) * | 2014-12-08 | 2015-04-01 | 宜兴市东晨电子科技有限公司 | Preparation method of novel QFN (Quad Flat No Lead) frame comprising overflow groove |
| CN104485287B (en) * | 2014-12-08 | 2017-04-26 | 江苏东晨电子科技有限公司 | Preparation method of novel QFN (Quad Flat No Lead) frame comprising overflow groove |
| CN104779224A (en) * | 2015-04-15 | 2015-07-15 | 江苏晟芯微电子有限公司 | QFN (Quad Fiat Nolead) packaging structure of power device |
| CN104779224B (en) * | 2015-04-15 | 2017-07-28 | 苏州聚达晟芯微电子有限公司 | A kind of QFN encapsulating structures of power device |
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