CN104051491A - Non-volatile memory device with tsi/tsv application - Google Patents
Non-volatile memory device with tsi/tsv application Download PDFInfo
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- CN104051491A CN104051491A CN201410097862.0A CN201410097862A CN104051491A CN 104051491 A CN104051491 A CN 104051491A CN 201410097862 A CN201410097862 A CN 201410097862A CN 104051491 A CN104051491 A CN 104051491A
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Abstract
Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.
Description
Technical field
In general, the present invention relates to the field of memory devices, more particularly, relate to memory devices and forming method thereof.
Background technology
A kind of random access memory (RAM) device comprises the memory array of many internal storage locations with interconnection, with storage information.Provide control circuit so that access memory cell.For instance, Nonvolatile memory (NVM) array comprises NVM internal storage location and the control circuit for access stored information.The in the situation that of nvm array, in the time of power-off, still retain data.
But along with storing lasting demand for more jumbo, it is larger that device becomes.For instance, in order to hold assembly, follow the larger array with more internal storage locations of complicated control circuit to need larger chip area.This causes higher expense.In addition, due to the type of some internal memory, as phase-change random access internal memory (PCRAM) or MRAM internal memory (MRAM), needing needs high heat budget, and traditional RAM device with integral control circuit reduces flexibility.This may cause the processing problem of following control circuit.
From discussion above, that wants is to provide improved memory devices.
Summary of the invention
Specific embodiment relates generally to NVM device.In one embodiment, device comprises: substrate, has array surface and non-array surface; Memory array, has by the first conductor at first direction and at the second conductor of second direction and a plurality of internal storage locations that interconnect.Described memory array is configured in the array surface of substrate.Described memory array comprises silicon guide hole (TSV) contact being configured in substrate again.Described TSV contact extends to non-array surface from array surface.Described TSV contact can be electrically connected to array from non-array surface.
In another specific embodiment, present a kind of method that is used to form memory devices.Described method comprises: the substrate with array surface and non-array surface is provided.Form the TSV contact that extends to non-array surface from the array surface of described substrate.Formation has by the first conductor and the second conductor and a plurality of internal storage locations that interconnect.Described memory array couples described TSV contact.
In another specific embodiment, present a kind of method of the NVM of being used to form device.Described method comprises provides the substrate with array surface and non-array surface.Form the TSV contact that extends to non-array surface from the array surface of described substrate.Formation has by the first conductor and the second conductor and the resistance-type NVM of a plurality of internal storage locations that interconnect.Described resistance-type NVM is coupled to described TSV contact.
The advantage of these and other of specific embodiment as herein described and feature will become clear by reference description and accompanying drawing below.In addition, the feature that is understood that various specific embodiments as herein described is not mutually to repel, and can various combinations and arrange in exist.
Brief description of the drawings
In the accompanying drawings, similar Reference numeral is commonly referred to as the same components in all different views.Meanwhile, accompanying drawing is not necessarily proportional, and emphasis is to be conventionally placed in explanation principle of the present invention on the contrary.Various specific embodiment of the present invention is to describe with reference to accompanying drawing below, wherein:
The simplification view of the specific embodiment of Fig. 1 a to Fig. 1 d display device;
The cutaway view of the specific embodiment of Fig. 2 to Fig. 3 display device; And
Fig. 4 and Fig. 5 show the specific embodiment of the flow process that is used to form device.
Embodiment
Specific embodiment relates to Nonvolatile memory (NVM) device.NVM device for example can comprise phase-change random access internal memory (PCRAM), MRAM internal memory (MRAM) and resistive random access internal memory (ReRAM).Also can use NVM or the memory devices of other type.Such NVM device can be incorporated in electronic product or equipment, as phone, calculator, and movable-type intelligent product etc.
The simplification view of the specific embodiment of Fig. 1 a to 1d display device 100.As the device of its demonstration comprises the memory array 120 with a plurality of internal storage locations 130.In one embodiment, memory array is Nonvolatile memory (NVM) array with Nonvolatile memory unit.Internal storage location comprises the memory module being configured between the first conductor 150 and the second conductor 160.Memory module can be for example for being configured in the memory card between the first conductor and the second conductor.In one embodiment, memory module is the resistance-type memory module that forms resistance-type NVM unit.
Array is included in a plurality of first conductors of first direction (for example, directions X) and for example, a plurality of the second conductors in second direction (, y direction).For instance, first or upper conductor be second or lower conductor be configured in first direction while being configured in second direction.In one embodiment, upper conductor is word line (WL) and lower conductor is bit line (BL).For instance, first direction and second direction are orthogonal direction.Also can use other configuration of conductor.At the crosspoint place of upper conductor and lower conductor configuration store assembly, and then form mnemon.
Resistance-type memory module is programmable resistance-type assembly.Programmable resistance-type assembly has multiple stable ohmic states.In one embodiment, resistance-type assembly is the bistable resistance-type assembly with the first stable ohmic states and the second stable ohmic states.For instance, resistance-type assembly have one wherein corresponding to logical zero and another one stable high resistance state and the stable low resistance state corresponding to logical one.For instance, high resistance state can, in the time that low resistance state can show as logical one, can show as logical zero.Also can use and have that high resistance state shows as logical one and low resistance state shows as logical zero.Also can use other configuration for the data storage of resistance-type assembly.
In one embodiment, memory module is phase transformation (PC) memory module.Phase change memory assembly comprises the phase-change material (PCM) that forms phase-change random access internal memory (PCRAM) unit.Can use polytype PCM.For instance, PCM can be chalcogenide material.In one embodiment, chalcogenide material is Ge-Sb-Te (GeSbTe) alloy.In one embodiment, chalcogenide material is five germanium two antimony five telluriums (Ge2Sb2Te5 (GST)).Also can use chalkogenide or the PCM of other type.
PCM can be crystallization or amorphous phase.Crystalline phase is that high resistance phase time is low resistance phase in amorphous phase.PCM until reset or set (set) front be stable in arbitrary phase or state.For instance, PCM can be reset to amorphous phase by being exposed to reset condition from crystalline phase by mat, or can impose a condition and be set as crystalline phase from amorphous phase by being exposed to.
In one embodiment, impose a condition and be included in its amorphous phase and convert temperature continuous heating enough time to crystallization to convert it to crystalline phase.On the other hand, reset condition comprises crystallization PCM is heated to fusing it is fast cooling to become amorphous.Heating PCM comprises that appropriateness passes into electric current to heater or heating component.In one embodiment, memory card comprises the heating component together with PCM.
In addition, memory module can comprise that resistance material (RM) is to form resistive random access internal memory (ReRAM) unit.RM can be the material that can form filiform.For instance, RM can be non-stoichiometric metal oxide layer, as hafnium oxide (HfO2) or tantalum oxide (TaOx or Ta2Ox, wherein x is non-integer) layer.Also can use the RM of other type.Make RM form the process of the conducting path of manufacturing filiform.Filiform can reset or disconnect by making RM carry out reseting procedure or condition, and filiform can be set or again form by making RM carry out assignment procedure or condition.For example, in the time following the setting RM of the filiform forming or again form to cause low resistance state (, logical one), follow the reset RM of the filiform of disconnection to cause high resistance state (for example, logical zero).RM memory card for example can comprise for platinum (Pt) or iridium (Ir) electrode and make sandwiched top electrode and the bottom electrode wherein of RM.In general be, contrary direction for setting and the resetting current of RM.For instance, RM uses bipolarity electric current for setting and resetting.Also can use the unipolarity electric current for setting and reset.
In another specific embodiment, memory cell can be magnetoresistive (MR) memory card to form mram cell.For MR memory card, it is included in is for example MTJ (MJT) storehouse between top electrode and the bottom electrode of platinum manganese (PtMn), iridium manganese (IrMn) or cobalt/palladium (Co/Pd).MJT storehouse comprises first and second magnetic or ferromagnetic (FM) layer of being separated by tunnel layer.For instance, FM layer be when the 2nd FM layer be while thering is the free layer of the changeable direction of magnetization, to be the fixing or pinning layer with fixed magnetisation direction.Fixed bed can be ferro-cobalt boron (CoFeB), and tunnel layer can be magnesium oxide (MgO) or alundum (Al2O3) (Al
2o
3), and free layer can be ferro-cobalt boron/rubidium/ferro-cobalt boron.Also can use other configuration of MJT storehouse.The direction of magnetization of fixed bed and free layer can be aimed at the direction parallel or vertical with MR storehouse.
When the direction of magnetization of layer in the opposite direction time MR memory module there is high resistance state, and when the direction of magnetization of layer during at equidirectional MR memory module there is low resistance state.The magnetic field of free layer is switched and can be reached by applying polarization current to MR storehouse.For instance, polarization current can as Fig. 1 b and Fig. 1 d represent to be applied to be configured in bit line below write lambda line (WrL) 165.For instance, a word line that is configured in another one top can comprise the first word line and the second word line.Can use the first word line and the second word line to set and reset mram cell.For instance, depend on sense of current, the direction of magnetization of free layer switches to other direction from a direction.For instance, two-way or bipolarity electric current is for the direction of magnetization of free layer being switched to the direction of wanting.So, setting (for example, low resistance phase) and reset (for example, high resistance phase) are contrary directions.
Memory array is to be configured on substrate (not shown).For instance, substrate can be the semiconductor substrate of for example Silicon Wafer.Also can use the substrate of other type.For instance, substrate can be the semiconductor substrate of monocrystalline (COI), SiGe or other type on the insulator of for example silicon-on-insulator.The use of non-semiconductor substrate may be also useful.For instance, at substrate, as intermediary layer in the situation that, substrate needs not be semiconductor substrate.For instance, substrate can be formed by glass or other non-semiconductor material.In general, parallel processing wafer is to form multiple devices.After finishing dealing with, wafer is cut into independent device.
For instance, substrate comprises the first first type surface and the second first type surface.Memory array is configured on one of them person of first type surface.For instance, the first type surface of array configurations on it can be described as array surface, and another surface can be described as non-array surface.In the configurable dielectric layer in array surface of array.Dielectric layer can be correspondence and has multiple dielectric layers of interlayer dielectric (ILD) layer of metal level (metal level).The various conductors of the corresponding array of metal level.For instance, metal level is available to bit line, word line and WrL in some cases.Memory module is configured between the bit line and word line in dielectric layer.
As described, array does not for example comprise, as the driving component of Memory control (, periphery or support) circuit.For instance, array can be described as passive array, and does not comprise as the control circuit of row decoder, column decoder, programmed circuit, reading circuit or other type circuit.
In one embodiment, array is connected to the non-array side of substrate by silicon guide hole (TSV) contact 180.For instance, TSV is the non-array side for the conductor of array being coupled to substrate.TSV contact is formed in silicon guide hole.The configurable periphery at substrate of TSV contact.TSV contact is positioned at and does not comprise that the other parts of assembly are also spendable.In one embodiment, TSV contact extends through substrate surface.For instance, TSV contact extends through array surface and the non-array surface of substrate.
In one embodiment, substrate act as the intermediary of Fig. 1 a and 1b.For instance, non-array surface comprises the contact or the contact tab that are connected to TSV contact, to be provided to the connection of memory array.Contact tab can be connected to TSV contact by for example heavy distribution layer (RDL).Also can use other technique for contact tab being coupled to TSV contact.
Other as the specific embodiment of Fig. 1 c and 1d in, provide TSV contact to be connected to the memory control circuit in the non-array side that is configured in substrate.For instance, as shown in the figure, array is connected to row decoder 190 and column decoder 192 by TSV contact 180.TSV contact 180 is also for being connected to array other control circuit.In this case, non-array side can be called the active side of substrate, and array side can be called non-effect.
The cutaway view of the exemplary specific embodiment of Fig. 2 display device 200.Device can be similar to person described in Fig. 1 c and 1d.And general assembly can not described or not be described in detail.As shown in Figure 2, can provide substrate 205.In one embodiment, substrate is semiconductor substrate.For instance, substrate is Silicon Wafer.Also can use the substrate of other type.For instance, substrate can be the semiconductor substrate of COI, SiGe or other type.
Substrate comprises the first first type surface 206 and the second first type surface 207.In one embodiment, when the not action face that the first first type surface is substrate at the second first type surface or basal surface, be action face or the top surface of substrate.Memory array 120 is to be configured on the not active surface of substrate.Memory array can be NVM memory array.NVM memory array can be resistance-type NVM memory array, as PCRAM, ReRAM or MRAM array.The memory array that other type is provided is also useful.In the configurable internal memory dielectric layer 225 in array surface of array.Dielectric layer can comprise that correspondence has multiple dielectric layers of the ILD layer of metal level.The various conductors of the corresponding array of metal level.Memory module is disposed between for example bit line and word line in dielectric layer.
In one embodiment, be the action face that is configured in substrate for controlling the driving component 277 of internal memory array access.For instance, driving component can comprise the control circuit of row decoder, column decoder, programmed circuit, reading circuit or other type circuit.Driving component can be formed as the part that FEOL (FEOL) is processed.If the dielectric layer 270 of front metal and dielectric (PMD) layer is be configured on substrate and cover driving component.Dielectric layer 270 is to be configured in pmd layer top.Dielectric layer 270 can comprise a plurality of ILD layers.ILD layer comprises the guide hole layer that has the metal level of metal wire 279 and have guide hole contact 278.Guide hole contact is used between the metal wire of two different metal levels connection is provided.In pmd layer, provide contact (CA) so that driving component is interconnected to M
1metal wire in layer.As shown in the figure, dielectric layer comprises metal level M
1to M
x.For instance, metal wire and contact are to use back-end process (BEOL) to process institute to form.For instance, can use the mosaic technology that comprises dual damascene process.Also can use other technique to form metal wire and contact.Also can comprise pad 295.Described pad provides the outside that arrives device to connect.Pad can couple M through pad contact
x.Can on pad, provide contact tab (not shown).
In one embodiment, TSV contact 180 is to provide by substrate surface.Between memory array in the not active side of the driving component of TSV contact in the active side of substrate and substrate, provide interconnection.As shown in the figure, device is included in memory array and control circuit integrated on the not homonymy of substrate, and substrate is the 3D application that uses TSV contact.
For the ease of storehouse device, the basal surface of internal memory dielectric layer that comprises memory array or the surface of exposure can comprise contact tab and RDL layer.Contact tab couples TSV contact, offers the interconnection of the active side of substrate.By this way, device can storehouse interconnection.
The cutaway view of the exemplary specific embodiment of Fig. 3 display device 300.As shown in the figure, device can be multichip system (MCS) device.As shown in the figure, device comprises intermediary's device 100.For instance, intermediary's device can be similar to person described in Fig. 1 a and 1b.And general assembly can not described or not be described in detail.Intermediary's device comprises intermediary substrate 305.In one embodiment, substrate is semiconductor substrate.Also can use the non-semiconductor substrate as glass.
Substrate comprises the first first type surface 306 and the second first type surface 307.In one embodiment, the first first type surface is that array surface and the second first type surface are non-array surface.The in the situation that of intermediate piece, two surfaces all can be not action face.Memory array 120 is configured in the array surface of substrate.Memory array can be NVM memory array.NVM memory array can be the memory array of any type.For instance, memory array can be as the NVM memory array of PCRAM, ReRAM or MRAM array.Also can use the memory array of other type.In the configurable internal memory dielectric layer 325 in array surface of array.Dielectric layer can comprise that correspondence has multiple dielectric layers of the ILD layer of metal level.The various conductors of the corresponding array of metal level.Memory module is disposed between for example bit line and word line in dielectric layer.
In one embodiment, TSV contact 180 provides by the surface of substrate.TSV contact provides the interconnection that arrives memory array from the non-array surface of substrate.Non-array surface comprises the intermediary's contact 312 configuring on it.For instance, intermediary's contact can be by dielectric layer 318 from non-array base palte surface separately.Dielectric layer can comprise RDL so that intermediary's contact and the interconnection of TSV contact.
At the top surface of internal memory dielectric layer, configurable if the pad of microtrabeculae is to connect the crystal grain of top.Pad provides for array and for the connection of the TSV contact on intermediary substrate.Can provide RDL to be beneficial to the connection for contact tab between TSV and memory array.
In one embodiment, intermediary's device is to couple base plate for packaging 330.For instance, base plate for packaging can be polyimide substrate.Also can use the base plate for packaging of other type.Base plate for packaging comprises the first main package surface 336 and the second main package surface 337.For instance, the first first type surface can be as top surface in the time that the second first type surface can be the basal surface of base plate for packaging.Top surface comprises encapsulation pad 342 in the time that basal surface comprises package land 346.Encapsulation pad couples package land by interior metal trace and contact in base plate for packaging.For instance, base plate for packaging can comprise multiple layers of metal trace and contact, to form the connection of wanting between encapsulation pad and package land.
In one embodiment, one or multi-controller 396 can storehouse on the top of intermediary's device.For instance, the first Memory Controller Hub 396
1, the second Memory Controller Hub 396
2and microcontroller (MCU) 396
3to be configured on the internal memory dielectric layer of intermediary's device.For instance, controller device is the intermediary's pad coordinating on (mated) internal memory dielectric layer.The controller device that other quantity or type are provided is also useful.As has been described, control circuit is in other device or in multiple individual other devices.MCS is as shown in Figure 3 the application of 2.5D.For instance, MCS system can be arranged on circuit board by package land.It will be appreciated that, Fig. 3 does not only mean and restricts for illustrative.For instance, intermediary layer can comprise any amount of chip or crystal grain.
Fig. 4 shows the specific embodiment of the flow process 400 that is used to form the device as described in Fig. 1 c to 1d and Fig. 2.General assembly can not described or not be described in detail.In step 410, carry out the processing procedure starting point (start) of wafer.For instance, process wafer in step 420 with FEOL.For instance, FEOL processes and form memory control circuit in the active side of wafer.After FEOL processes, carry out TSV module to form TSV contact in step 430.The processing of wafer is processed and is continued with BEOL, to form metal wire and guide hole in metal level and guide hole layer.Form like this connection of the control circuit to TSV contact.Then carry out passivation and the processing of pad opening.For instance, can above pad, form passivation layer and form therein opening to expose pad.Can complete like this processing of the active side of wafer.
Processing procedure continues rear side or the non-active side for the treatment of substrate.In one embodiment, processing procedure is undertaken by the rear side of thinning wafer, to expose the bottom of TSV contact in step 450.In step 460, form dorsal part RDL and memory array, and make array connect TSV.Forming after memory array, form contact tab.For instance, can apply and formation internal memory projection for thering is the crystal grain of storehouse.After finishing dealing with in the back side of wafer, processing procedure can carry out assembling, storehouse and the encapsulation of device and continue in step 470.
Fig. 5 shows the specific embodiment of the flow process 500 that is used to form the device as described in Fig. 1 a to 1b and Fig. 3.Processing procedure can comprise similar step as shown in Figure 4.General assembly can not described or not be described in detail.As shown in the figure, processing procedure comprises two independently sub-process 501 and sub-processes 505.For the first sub-process, use it to form through-silicon intermediary (TSI) device that is attended by integrated memory array.In one embodiment, in step 510, carry out the processing procedure starting point of intermediary's wafer.Processing procedure starts with the execution TSV module of step 520, to form TSV contact in TSI wafer.In step 530, can form RDL and memory array.RDL be provided for memory array to TSV from for example connection for the front side of TSI wafer.
Processing procedure continues to process the back side of TSI wafer.In one embodiment, carry out processing procedure to expose TSV contact in step 540.For instance, the back side that processing procedure comprises thinning/grinding crystal wafer is to expose the bottom of TSV contact.In step 550, can form dorsal part RDL and intermediary's contact tab.For instance, complete like this processing of TSI wafer.
As the second sub-process, it forms Memory Controller Hub device.In step 515, carry out the processing procedure starting point of top crystal grain/controller wafer.In step 525, wafer uses FEOL to process and processes.For instance, FEOL processes and forms Memory control circuit.After FEOL processes, BEOL processes and starts to form metal wire and guide hole in metal level and guide hole layer in step 535.Be formed for like this interconnection of control circuit.Can above metal level, form in step 545 passivation layer.In passivation layer, form opening, and then in opening, form contact tab.Contact tab offers the external path of control circuit.Complete like this processing of the active side of top crystal grain/controller wafer.Cutting crystal wafer is so that top crystal grain/controller device is separated into independent top crystal grain/controller device.
In step 560, described in Fig. 1 a and 1b and Fig. 3, install top crystal grain/controller device to TSI device to form device.The TSI device with top crystal grain/controller device can be arranged on base plate for packaging.In some cases, more than one top crystal grain/controller device can be arranged on TSI device.
The present invention can not depart from the specifically enforcement with other particular form under spirit of the present invention and essential characteristic thereof.Therefore, the specific embodiment in above stated specification is the purposes that is regarded as explanation completely, and unrestricted the present invention as herein described.Therefore, category of the present invention is by claims, but not by aforementioned specified, and to fall into all changes in equivalent intention and the scope of claim be to be intended to include in wherein.
Claims (20)
1. a device, comprising:
Substrate, has array surface and non-array surface;
Memory array, it has by the first conductor at first direction and at the second conductor of second direction and a plurality of internal storage locations that interconnect, and described memory array is configured in the described array surface of described substrate; And
Silicon guide hole (TSV) contact, it is configured in described substrate, and described TSV contact extends to described non-array surface from described array surface, and described TSV contact can be electrically connected to described array from described non-array surface.
2. device according to claim 1, wherein,
Described substrate act as intermediary substrate;
Configuration intermediary's contact is so that can be electrically connected by described TSV contact between described memory array; And
Configuration intermediary's pad is so that described memory array is electrically connected other circuit via silicon guide hole.
3. device according to claim 2, wherein, controller device is to be connected to described intermediary pad, for memory array described in control memory access.
4. device according to claim 1, comprises the control circuit in the described non-array surface that is configured in described substrate again,, the described non-array surface of wherein said substrate act as the action face of described substrate.
5. device according to claim 4, comprises the device projection on the exposed surface of the dielectric layer that is configured in described non-array surface top again,, described device projection couples described TSV contact.
6. device according to claim 5, comprises the lip-deep array contact point that is disposed at the array dielectric layer being configured in described array surface again, and described array contact point couples described TSV contact, is beneficial to the storehouse of described device and another device.
7. device according to claim 1, wherein, described memory array is Nonvolatile memory (NVM) array.
8. device according to claim 8, wherein, described nvm array is resistance-type nvm array.
9. device according to claim 8, wherein, described nvm array is phase-change random access internal memory (PCRAM) and MRAM internal memory (MRAM).
10. device according to claim 1, wherein, internal storage location comprises the memory card being configured between the first conductor and the second conductor.
11. 1 kinds are used to form the method for device, comprise:
The substrate with array surface and non-array surface is provided;
Form the TSV contact that extends to described non-array surface from the described array surface of described substrate; And
Formation has by the first conductor and the second conductor and the memory array of a plurality of internal storage locations that interconnect, and wherein, described memory array couples described TSV contact.
12. methods according to claim 11, comprise again:
Before forming described memory array, form described TSV contact; And
Form intermediary's pad, to be electrically connected with described memory array and other circuit via described TSV contact.
13. methods according to claim 12, are included in again in the described non-array surface of described substrate and form intermediary's contact, and described intermediary contact couples described TSV contact.
14. methods according to claim 13, wherein, the memory array side that described array surface is described substrate, and the non-memory array side that described non-array surface is described substrate.
15. methods according to claim 14, comprise again:
First process the described memory array side of described substrate; And
After the processing that completes described array side, process the described non-memory array side of described substrate.
16. methods according to claim 15, wherein, process described non-memory array side and comprise:
Described in thinning, the dorsal part of substrate is to expose described TSV contact; And
Formation couples the package land of described TSV contact.
17. methods according to claim 11, comprise again:
Use FEOL (FEOL) to process and form the control circuit in the described non-array surface that is configured in described substrate;
After the described control circuit of formation, form described TSV contact; And
Use back-end process (BEOL) to process and make described TSV contact and the interconnection of described control circuit.
18. methods according to claim 11, comprise again:
After processing the described non-array surface of described substrate, process the described array surface of described substrate;
Described in thinning, array surface is to expose described TSV contact; And
In described array surface, form described memory array, described memory array and described TSV connect multiple interconnection.
19. methods according to claim 18, wherein, described memory array comprises resistance-type nvm array.
20. 1 kinds are used to form the method for NVM memory devices, and it comprises:
The substrate with array surface and non-array surface is provided;
Form the TSV contact that extends to described non-array surface from the described array surface of described substrate; And
Formation has the resistance-type NVM by a plurality of internal storage locations of the first conductor and the second interconnection of conductors, and wherein said resistance-type NVM is coupled to described TSV contact.
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| US201361786624P | 2013-03-15 | 2013-03-15 | |
| US61/786,624 | 2013-03-15 | ||
| US13/906,289 US9111941B2 (en) | 2013-03-15 | 2013-05-30 | Non-volatile memory device with TSI/TSV application |
| US13/906,289 | 2013-05-30 |
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| CN107004667B (en) * | 2014-10-29 | 2020-05-29 | 高通股份有限公司 | Electrically reconfigurable interposer with built-in resistive memory |
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| CN104051491B (en) | 2017-06-06 |
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