CN104037160B - Copper interconnection structure and method for manufacturing same - Google Patents
Copper interconnection structure and method for manufacturing same Download PDFInfo
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- CN104037160B CN104037160B CN201310069905.XA CN201310069905A CN104037160B CN 104037160 B CN104037160 B CN 104037160B CN 201310069905 A CN201310069905 A CN 201310069905A CN 104037160 B CN104037160 B CN 104037160B
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Abstract
The invention provides a copper interconnection structure and a method for manufacturing the same. The copper interconnection structure comprises a semiconductor substrate, a first interlayer dielectric layer disposed on the semiconductor substrate, a copper plug running through the first interlayer dielectric layer, a second interlayer dielectric layer disposed on the first interlayer dielectric layer, and a copper interconnection wire running through the second interlayer dielectric layer. A first protective layer is arranged between the first interlayer dielectric layer and the copper interconnection wire, and a second protective layer is arranged between the second interlayer dielectric layer and the copper interconnection wire. According to the copper interconnection structure provided by the invention, as the first protective layer is arranged between the first interlayer dielectric layer and the copper interconnection wire and the second protective layer is arranged between the second interlayer dielectric layer and the copper interconnection wire, direct contact between the copper interconnection wire and the first interlayer dielectric layer and between the copper interconnection wire and the second interlayer dielectric layer is avoided, and the first interlayer dielectric layer and the second interlayer dielectric layer are prevented from being fractured by the copper interconnection wire.
Description
Technical field
The present invention relates to semiconductor applications, particularly to the manufacture method of a kind of copper interconnection structure and copper interconnection structure.
Background technology
With the development of semiconductor technology, the integrated level of VLSI chip has been up to several hundred million or even tens
The scale of hundred million devices, multiple layer metal interconnection technique more than two-layer widely uses.Metal interconnecting layer includes metal interconnection structure
（Metal interconnection structure includes metal interconnecting wires and metal plug）With interlayer dielectric layer (Inter-layer dielectric,
ILD).The manufacture method of metal interconnecting layer is typically included in interlayer dielectric layer manufacture groove (trench) and through hole（via）, then
Deposited metal in above-mentioned groove and through hole, the metal of deposition forms described metal interconnection structure.Because copper has preferable conduction
Property filling capacity, generally select copper as metal interconnecting wires material, from silicon oxide（Silicon dioxide）As interlayer dielectric layer
Material.
Metal interconnecting layer would generally be made on semiconductor device layer.The manufacture method of existing metal interconnecting layer refers to figure
Each schematic diagram of 1 to Fig. 4.With reference first to Fig. 1, in Semiconductor substrate（In figure is not shown）On sequentially form etching barrier layer 109,
Interlayer dielectric layer 101, Inorganic bottom antireflective layer 103 and organic bottom antireflective layer 105, and in organic bottom antireflective layer
Form the photoresist layer 107 of patterning on 105.Then referring to Fig. 2, with photoresist layer 107 described in Fig. 1 as mask, right successively
Described organic bottom antireflective layer 105, Inorganic bottom antireflective layer 103 and interlayer dielectric layer 101 carry out dry etching or wet
Method etches, to form two through holes in interlayer dielectric layer 101（Non- label）, then remove described photoresist layer 107 and organic
Bottom anti-reflection layer 105.Afterwards with reference to Fig. 3, then remove the partly described interlayer dielectric layer 101 between two through holes, form ditch
Groove 111.Wherein, during forming through hole and groove 111, the described etching barrier layer 109 manifesting also is etched.Finally
With reference to Fig. 4, fill groove 111 and the through hole in Fig. 3 with copper metal, form copper interconnecting line 113 and copper connector 115.
But, in the metal interconnection structure being formed by existing method, as shown in figure 4, interlayer dielectric layer 101 and copper interconnecting line
Contact area ratio between 113 is larger, and because the mechanical strength of interlayer dielectric layer 101 is less, and the density ratio of copper is larger, because
And copper interconnecting line 113 easily by interlayer dielectric layer 101 pressure break so that crack in interlayer dielectric layer 101（Crack）117.And one
Crack 117 in denier interlayer dielectric layer 101, then the reliability of whole semiconductor structure cannot ensure, this interlayer dielectric layer 101 exists
Very likely phenomenon of bursting apart occurs during following process, consequently, it is possible to leading to whole semiconductor structure to be scrapped.More need to emphasize
It is, thick due to the thickness of the corresponding interlayer dielectric layer of the interconnection structure of top layer interlayer dielectric layer more corresponding than other interconnection structures
Degree is much larger, and therefore the copper interconnecting line in the interconnection structure of top layer is thicker than the copper interconnecting line in other interconnection structures a lot, that is,
The volume of copper interconnecting line can be bigger, it is hereby understood that the copper interconnecting line of top layer is easier to make interlayer dielectric layer crack.
The forming method of more metal interconnection structures may be referred to the Chinese invention patent of Publication No. CN102543837A
Application.
Content of the invention
The problem that the present invention solves is the manufacture method providing a kind of copper interconnection structure and copper interconnection structure, to prevent interlayer
Crack by copper interconnecting line pressure break in dielectric layer.
For solving the above problems, the copper interconnection structure that the present invention provides includes：
Semiconductor substrate；
The first interlayer dielectric layer in described Semiconductor substrate；
Run through the copper connector of described first interlayer dielectric layer；
The second interlayer dielectric layer on described first interlayer dielectric layer；
Run through the copper interconnecting line of described second interlayer dielectric layer；
There is between described first interlayer dielectric layer and described copper interconnecting line the first protective layer, described second interlayer dielectric layer
There is and described copper interconnecting line between the second protective layer.
Optionally, the making material of described first interlayer dielectric layer and described second interlayer dielectric layer includes silicon oxide.
Optionally, include barrier layer between described first interlayer dielectric layer and described second interlayer dielectric layer, described copper is inserted
Plug runs through described barrier layer.
Optionally, the making material on described barrier layer includes one kind at least within of silicon nitride and carbonitride of silicium.
Optionally, the making material of described first protective layer includes one kind at least within of silicon nitride and carbonitride of silicium, its
Thickness range is 300 angstroms～1000 angstroms.
Optionally, the making material of described second protective layer includes one kind at least within of silicon nitride and carbonitride of silicium, its
Thickness range is 300 angstroms～1000 angstroms.
For solving the above problems, present invention also offers a kind of manufacture method of copper interconnection structure, including：
Semiconductor substrate is provided；
Form interlayer dielectric layer on the semiconductor substrate；
Form first groove in described interlayer dielectric layer；
Form protective layer in the side wall of described first groove and bottom, described first groove is reduced to second groove；
Form packed layer, the upper surface of the upper surface of described packed layer and described interlayer dielectric layer in described second groove
Flush；
Form the through hole sequentially passing through described packed layer, described protective layer and described interlayer dielectric layer from top to bottom；
Remove remaining described packed layer, form the 3rd groove；
Fill copper metal in described 3rd groove and described through hole.
Optionally, remove remaining described packed layer, form the 3rd groove, including：
Form organic bottom anti-reflecting layer and fill described through hole；
Remove remaining described packed layer and partly described organic bottom anti-reflective layer, form described 3rd groove, remaining
Described organic bottom anti-reflective layer is flushed with the 3rd channel bottom；
Remove and be located at remaining described organic bottom anti-reflective layer in described through hole.
Optionally, the making material of described interlayer dielectric layer includes silicon oxide.
Optionally, include barrier layer inside described interlayer dielectric layer；Described first groove is with described barrier layer as bottom；Institute
State through hole and run through described barrier layer.
Optionally, the making material on described barrier layer includes one kind at least within of silicon nitride and carbonitride of silicium.
Optionally, the making material of described protective layer includes a kind of at least within, its thickness of silicon nitride and carbonitride of silicium
Scope is 300 angstroms～1000 angstroms.
Optionally, the making material of described packed layer includes low temperature oxide material.
Compared with prior art, technical solution of the present invention has advantages below：
In the copper interconnection structure that the present invention provides, between copper interconnecting line and the first interlayer dielectric layer, include the first protective layer,
The second protective layer is included, the mechanical strength of the first protective layer and the second protective layer is more than layer between copper interconnecting line and second dielectric layer
Between dielectric layer mechanical strength, they can either protect interlayer dielectric layer,
Can contact so that whole semiconductor structure is relatively reliable well with copper interconnecting line, it is to avoid copper interconnecting line again
With interlayer dielectric layer directly contact, prevent interlayer dielectric layer by copper interconnecting line pressure break.
In the alternative of the present invention, described first protective layer and described second protective layer can be by silicon nitride making
Become, the high mechanical strength of silicon nitride, hardness, close to corundum, has self lubricity, and wear-resisting, and room temperature bending strength can be up to
More than 980MPa, its room temperature strength can be always maintained at 1200 DEG C and still not decline, and heat stability is good, and thermal coefficient of expansion is little, has
Good heat conductivility, good thermal shock, can play more preferable protective effect using silicon nitride as protective layer.
Brief description
Fig. 1 to Fig. 4 is the schematic diagram of existing copper interconnection structure manufacture method；
Fig. 5 is the embodiment of the present invention one copper interconnection structure schematic diagram；
Fig. 6 is the embodiment of the present invention two copper interconnection structure schematic diagram；
Fig. 7 to Figure 13 is each step structural representation of the embodiment of the present invention three copper interconnection structure manufacture method；
Figure 14 to Figure 20 is each step structural representation of the embodiment of the present invention four copper interconnection structure manufacture method.
Specific embodiment
As stated in the Background Art, in existing copper interconnection structure, copper interconnecting line and interlayer dielectric layer directly contact, because copper is close
Degree is big, and the volume of copper interconnecting line is big, thus easily interlayer dielectric layer pressure break is formed crack, thus the present invention provides new copper mutual
The manufacture method linking structure and copper interconnection structure, to solve the above problems.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
The present embodiment provides a kind of copper interconnection structure of top layer, in the copper interconnection structure of usual top layer, the thickness of copper interconnecting line
Degree can reach 16000 angstroms, and in the copper interconnection structure of usual interlayer, the thickness of copper interconnecting line is only the 3000 Izods right sides, thus top
The copper interconnection structure of layer is more easy to need to prevent the crack problem being previously mentioned in background technology.It should be noted that the present invention
Technical scheme in addition to can applying to the copper interconnection structure of top layer, be equally applicable to the copper interconnection structure of interlayer, thus
The structure that the present embodiment discloses below can correspond in the copper interconnection structure applying to interlayer, and similar, this specification is follow-up
Structure described by embodiment two to four and manufacture method are equally applicable to copper interconnection structure of interlayer and preparation method thereof.
Refer to Fig. 5, this copper interconnection structure includes Semiconductor substrate（Not shown）, in described Semiconductor substrate
One interlayer dielectric layer 511, runs through the copper connector 531 of described first interlayer dielectric layer 511, positioned at described first interlayer dielectric layer
The second interlayer dielectric layer 512 on 511, runs through the copper interconnecting line 532 of described second interlayer dielectric layer 512, described first interlayer
There is between dielectric layer 511 and described copper interconnecting line 532 first protective layer 521, described second interlayer dielectric layer 512 and described copper
There is between interconnection line 532 second protective layer 522.
In the present embodiment, the material of described Semiconductor substrate can be monocrystal silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon；Or
Person can also include other materials.Device architecture is may also be formed with, described device architecture can be in described Semiconductor substrate
The device architecture being formed in quasiconductor FEOL, such as MOS transistor etc..Interlayer is may also be formed with described Semiconductor substrate
Interconnection structure.In a word, the present invention is not limited to Semiconductor substrate.
As a kind of specific embodiment, the making material of this first interlayer dielectric layer 511 and this second interlayer dielectric layer 512
Expect for silicon oxide（Silicon dioxide）, and this first interlayer dielectric layer 511 can include one layer of etching stop layer 540 below,
This etching stop layer 540, in whole copper interconnection structure forming process, plays the effect stopping etching.
As shown in figure 5, copper interconnecting line 532 and copper connector 531 be collectively forming run through this first interlayer dielectric layer 511 and this
The copper interconnection structure of two interlayer dielectric layers 512.Have already mentioned above, between this first interlayer dielectric layer 511 and copper interconnecting line 532
There is the first protective layer 521, there is the second protective layer 522, wherein between this second interlayer dielectric layer 512 and copper interconnecting line 532
First protective layer 521 is located at the bottom of copper interconnecting line 532, and the second protective layer 522 is located at the side of copper interconnecting line 532.Due to
There is described first protective layer 521 and the second protective layer 522, the machinery of this first protective layer 521 and this second protective layer 522 is strong
Degree is bigger than the mechanical strength of the first interlayer dielectric layer 511 and the second interlayer dielectric layer 512, and they are it can be avoided that copper interconnecting line 532
With the first interlayer dielectric layer 511 and the second interlayer dielectric layer 512 directly contact, thus the first interlayer dielectric layer 511 can be prevented
With the second interlayer dielectric layer 512 by described copper interconnecting line 532 pressure break.
In the present embodiment, the making material of described first protective layer 521 can be silicon nitride and carbonitride of silicium at least its
Middle one kind.The making material of the first protective layer 521 described in the present embodiment is silicon nitride.The high mechanical strength of silicon nitride, hardness
Close to corundum, there is self lubricity, and wear-resisting.The room temperature bending strength of silicon nitride can be up to more than 980MPa, can be with conjunction
Jin Gang compares, and its room temperature strength can be maintained to 1200 DEG C does not decline, and its heat stability is good, and thermal coefficient of expansion is little,
There is good heat conductivility, so thermal shock resistance, will not ftracture from room temperature to 1000 DEG C of thermal shock very well.Thus with silicon nitride
It is difficult, by copper interconnecting line 532 pressure break, to play more preferable protective effect as protective layer.The thickness range of this first protective layer 521
300 angstroms～1000 angstroms can be preferably.In this thickness range, on the one hand this first protective layer 521 can reach to ground floor
Between dielectric layer 511 good protection, on the other hand this first protective layer 521 itself again will not too thick it is ensured that subsequent copper is golden
The filling belonging to.So, this first protective layer 521 just can preferably protect the first interlayer positioned at copper interconnecting line 532 bottom to be situated between
Matter layer 511.
Likewise, in the present embodiment, the making material of described second protective layer 522 can be silicon nitride and carbonitride of silicium
A kind of at least within.The making material of the second protective layer 522 described in the present embodiment is silicon nitride, and further, this second guarantor
The thickness range of sheath 522 can be preferably 300 angstroms～1000 angstroms, and the selection of this thickness range refers to the first protective layer 521
The selection of thickness range.It should be noted that the thickness of described first protective layer 521 and described second protective layer 522 can phase
With it is also possible to different.
Embodiment two
The present embodiment continues to provide a kind of copper interconnection structure of top layer.Copper interconnection structure and enforcement that the present embodiment is provided
Having points of resemblance copper interconnection structure described in example one, something in common refer to the corresponding contents in embodiment one, this enforcement more
Example is illustrated to the difference of the two emphatically.
Refer to Fig. 6, this copper interconnection structure includes Semiconductor substrate（Not shown）, in described Semiconductor substrate
One interlayer dielectric layer 611, runs through the copper connector 631 of described first interlayer dielectric layer, on described first interlayer dielectric layer 611
The second interlayer dielectric layer 612, run through the copper interconnecting line 632 of described second interlayer dielectric layer 612.In the present embodiment, described
Barrier layer 613 is also included, described copper connector 631 runs through institute between one interlayer dielectric layer 611 and described second interlayer dielectric layer 612
State barrier layer 613.There is between described first interlayer dielectric layer 611 and described copper interconnecting line 632 first protective layer 621, described
There is between second interlayer dielectric layer 612 and described copper interconnecting line 632 second protective layer 622.
Similar to embodiment one, one layer of etching stop layer 640 can be included below the first interlayer dielectric layer 611, should
Etching stop layer 640, in whole copper interconnection structure forming process, plays the effect stopping etching.First interlayer dielectric layer 611
Making material with the second interlayer dielectric layer 612 can be equally silicon oxide（Silicon dioxide）.
In the present embodiment, interlayer dielectric layer is divided into upper and lower two-layer by this barrier layer 613（I.e. described first interlayer dielectric layer
611 and described second interlayer dielectric layer 612）.As shown in fig. 6, the first interlayer dielectric layer 611, the second interlayer dielectric layer 612 and
The integrative-structure that barrier layer 613 between them is collectively forming by copper interconnecting line 632 and copper connector 631 runs through, wherein
Barrier layer 613 is run through by copper connector 631.
In the present embodiment, there is between the first interlayer dielectric layer 611 and copper interconnecting line 632 first protective layer 621,
There is between two interlayer dielectric layers 612 and copper interconnecting line 632 second protective layer 622.That is, the first protective layer 621 is located at
The bottom of copper interconnecting line 632, and the second protective layer 622 is located at the side of copper interconnecting line 632.The present embodiment is due to having described
One protective layer 621 and the second protective layer 622, the mechanical strength of this first protective layer 621 and this second protective layer 622 compares ground floor
Between dielectric layer 611 and the second interlayer dielectric layer 612 mechanical strength big, they are it can be avoided that copper interconnecting line 632 and the first interlayer
Dielectric layer 611 and the second interlayer dielectric layer 612 directly contact, thus described first interlayer dielectric layer 611 and second can be prevented
Interlayer dielectric layer 612 is formed the situation in crack by described copper interconnecting line 632 pressure break.
In the present embodiment optionally, the making material of described first protective layer 621 and the second protective layer 622 and thickness range
Refer to the content in embodiment one.The making material on this barrier layer 613 can for silicon nitride and carbonitride of silicium at least within
One kind, the making material on this barrier layer 613 can be identical with the making material of the first protective layer 621, so that being located at first
The partial barrier 613 of protective layer 621 lower section forms integrative-structure with this first protective layer 621.But, this this barrier layer 613
Making material can also be different from the making material of the first protective layer 621.The thickness range on this barrier layer 613 can be according to need
Set, such as：300 angstroms～1000 angstroms.Due to arranging barrier layer 613 between two interlayer dielectric layers, so that in etching
During the second interlayer dielectric layer 612, can be using this barrier layer 613 as etching stop layer（Refer to example IV）, so that
Copper interconnection structure to be made is more accurate.
The partial barrier 613 being located at the first protective layer 621 lower section in Fig. 6 is also pointed to the first protective layer 621 lower section
First interlayer dielectric layer 611 plays a protective role, and between this segments first layer dielectric layer 611 be just affected by copper interconnecting line 632 squeeze
The place of pressure most serious, thus in the present embodiment, the setting on barrier layer 613 can protect the first interlayer dielectric layer 611 further.
Embodiment three
The present embodiment provides a kind of manufacture method of the copper interconnection structure of top layer, including step S31 to step S38.Need
Illustrate, it is to distinguish and being easy to each step is described that the present embodiment names each step with S31 to step S38, but does not limit
The sequencing of fixed each step, in different embodiments, each sequence of steps can adjust.Hereinafter each step will be illustrated, please
With reference to Fig. 5 and Fig. 7 to Figure 13.
Step S31, provides Semiconductor substrate.
The Semiconductor substrate that the present embodiment is provided refers to may include partly leading of various types of semiconductor device structures
Body substrate, although in figure does not show, those skilled in the art can consider that this Semiconductor substrate may include this area can
Make arbitrary structures on a semiconductor substrate, the such as device architecture such as CMOS.
Execution step S32, refer to Fig. 7, forms interlayer dielectric layer 510 on a semiconductor substrate.
In the present embodiment, it is possible to use chemical vapor deposition (Chemical Vapor deposition, CVD) technique, thing
Physical vapor deposition technique（Physical Vapor Deposition, PVD）Or atom layer deposition process（atomic layer
Deposition, ALD）Form this interlayer dielectric layer 510 on the semiconductor substrate.The making material of this interlayer dielectric layer 510
Material is preferably silicon oxide.Silicon oxide generally applies to semiconductor fabrication process process, and its raw material is easy to get, and prepares accordingly
Technical maturity, is the first-selection making interlayer dielectric layer 510.
Execution step S33, please continue to refer to Fig. 7, forms first groove 560 in interlayer dielectric layer 510.
The photoresist layer of patterning can be formed first on interlayer dielectric layer 510（Do not show）, then perform etching, shape
Become this first groove 560.
The present embodiment is specific, before forming the described photoresist layer of patterning, arranges one layer of Inorganic bottom antireflective
, above this interlayer dielectric layer 510, specifically, this is inorganic for layer 550 (Bottom Antireflective Coating, BARC)
Bottom anti-reflection layer 550 can be enriched in the Si-BARC of Si or other inorganic material make, as SiON is formed
Inorganic bottom antireflective layer.After forming above-mentioned Inorganic bottom antireflective layer 550, then in this Inorganic bottom antireflective layer
550 surfaces form the photoresist layer of patterning.Then interlayer dielectric layer 510 is carried out with the photoresist layer of this patterning for mask
Etching, forms this first groove 560.
In the present embodiment, this interlayer dielectric layer 510 can be positioned below etching stop layer 540, and this etching stop layer 540 can
The semiconductor structure of interlayer dielectric layer 510 lower section is shielded, prevents overetch.
Execution step S34, refer to Fig. 8, and protective layer 520 is formed on the side wall of first groove 560 and bottom in the figure 7, the
One groove 560 is reduced to second groove 560 '.
In the present embodiment, the making material of protective layer 520 includes a kind of at least within, its thickness of silicon nitride and carbonitride of silicium
Degree scope is 300 angstroms～1000 angstroms.The setting of this thickness refer to embodiment one related content.From Fig. 8 it can further be seen that this
When still retain Inorganic bottom antireflective layer 550 between protective layer 520 and interlayer dielectric layer 510.
Execution step S35, refer to Fig. 9, forms packed layer 570 in fig. 8 in second groove 560 ', packed layer 570
Upper surface and the upper surface flush of interlayer dielectric layer 510.
After packed layer 570 filling second groove 560 ', generally exceed second groove 560 ' certain altitude, to packed layer
570 are planarized, to remove unnecessary packed layer 570（The packed layer 570 of this redundance is positioned at Inorganic bottom antireflective
The part on layer 550 surface）.The present embodiment, while packed layer 570 is planarized, removes Inorganic bottom antireflective layer 550, shape
Become the protective layer 520 ' with interlayer dielectric layer 510 upper surface flush and finally smooth packed layer 570, as shown in Figure 9.
In the present embodiment, the making material of packed layer 570 can be low temperature oxide（Such as silicon oxide, silicon oxide carbide or
Person's silicon oxynitride）Material, the filling capacity of low temperature oxide material is good, and easily removes, thus can be complete in subsequent step
Full removal.
Execution step S36, refer to Figure 10 and Figure 11, is formed and sequentially passes through packed layer 570, protective layer 520 ' from top to bottom
Through hole with interlayer dielectric layer 510.
In the present embodiment, referring first to Figure 10, Inorganic bottom anti-reflective is formed on the packed layer 570 after above-mentioned planarizing
Penetrate layer 581 and organic bottom antireflective layer 582.In the present embodiment, the material of this organic bottom antireflective layer 582 can be to pass through
Spin coating proceeding is formed.Then the photoresist layer 583 of patterning is formed on this organic bottom antireflective layer 582 again.
Refer to Figure 11, performed etching for mask with the photoresist layer 583 of patterning shown in Figure 10, define from top to bottom
Sequentially pass through the through hole of packed layer 570, protective layer 520 ' and interlayer dielectric layer 510（Do not mark）.After forming through hole, Tu10Zhong
The remainder of Inorganic bottom antireflective layer 581 forms new Inorganic bottom antireflective layer 581 ' in Figure 11, packed layer 570 surplus
Remaining part is divided, and forms new packed layer 570 ', and then corresponding area is divided into two parts to protective layer 520 ', and a part is positioned at residue
The first protective layer 521 below packed layer 570 ', another part is the second protective layer positioned at remaining packed layer 570 ' side
522.From Figure 11 it can also be seen that the through hole that this step is formed runs through etching stop layer 540 in the lump.
Photoresist layer 583 in Figure 10 can be eliminated by etching in the lump in etching process, and organic bottom antireflective layer
582 can be removed by solvent clean or cineration technics after through hole is formed.
Execution step S37, incorporated by reference to reference to Figure 12 and Figure 13, removes remaining packed layer 570 ', forms the 3rd groove
560”.
This step can specifically include following process：After forming structure as shown in figure 11, form new organic bottom
Anti-reflecting layer 591 fills above-mentioned through hole, the inorganic bottom that this organic bottom antireflective layer 591 remains in covering in Figure 11 simultaneously
Portion's anti-reflecting layer 581 '.Then the photoresist layer 592 of patterning is formed on organic bottom antireflective layer 591, with photoresist layer
592 is mask, is removed using dry etching, reactive ion etching (Reactive Ion Etching, RIE) or plasma etching
Part organic bottom antireflective layer 591 and remaining packed layer 570 ', form the 3rd groove 560 "（Void as shown in Figure 13
Frame portion, also can regard the space occupied by remaining packed layer 570 ' in original Figure 12 as）.
Removing in Figure 12 after packed layer 570 ', remaining described organic bottom anti-reflective layer and the 3rd groove 560 " bottom flushes
（Not shown）, available plasma etch process removes not this remaining organic bottom antireflective layer 591, until exposing whole
Through hole.It is of course also possible to using dry etching in the reactor chamber by photoresist layer 592 and remaining organic bottom antireflective layer
591 removals.Etching gas used can be oxygen (O2), oxygen organic bottom in through-holes with photoresist layer 592 and residual
There is chemical reaction in portion's anti-reflecting layer 591, while removing photoresist layer 592, remove described remaining part organic bottom
Anti-reflecting layer 591.
Execution step S38, refer to Fig. 5, in fig. 13 the 3rd groove 560 " and through hole filling copper metal.
The present embodiment can using galvanoplastic in the 3rd groove 560 " and through hole in deposited copper metal, the structure ultimately forming
As shown in Figure 5.It should be noted that the present embodiment by copper metal fill the 3rd groove 560 " and through hole after, this copper metal
Would generally be than the 3rd groove 560 " exceed a part, at this point it is possible to the copper metal so that being filled is removed by planarizing mode
With the upper surface flush of interlayer dielectric layer 510, form the copper connector 531 as described in embodiment one and copper interconnecting line 532.Specifically
, can be selected for CMP method and planarized, and can using this CMP method simultaneously
Remove the Inorganic bottom antireflective layer 581 ' that above steps left behind.
It should be noted that the first interlayer dielectric layer 511 in interlayer dielectric layer 510 in Fig. 5 and Figure 11 and the second layer
Between dielectric layer 512 corresponding, that is, the first interlayer dielectric layer 511 in Figure 11 and the second interlayer dielectric layer 512 can be regarded as altogether
It is the interlayer dielectric layer 510 in Fig. 5.
By above-mentioned steps, the present embodiment forms structure as shown in Figure 5, and this structure is due to having the first protective layer 521 He
Second protective layer 522, can avoid copper interconnecting line 532 and interlayer dielectric layer 510 directly contact, thus protecting interlayer dielectric layer
510 by copper interconnecting line 532 pressure break.
Example IV
The manufacture method that the present embodiment provides the copper interconnection structure of another top layer, including step S41 to step S48.
It should be noted that the manufacture method of the present embodiment copper interconnection structure has phase with the manufacture method of embodiment three copper interconnection structure more
Same part, something in common refer to the corresponding contents in embodiment three, and the present embodiment is said to the difference emphasis of the two emphatically
Bright.
Execution step S41, provides Semiconductor substrate.
The present embodiment step S41 is identical with embodiment three step S31, refer to embodiment three related content.
Execution step S42, refer to Figure 14, forms the first interlayer dielectric layer 611 and the second interlayer on a semiconductor substrate
Dielectric layer 612.
In the present embodiment, the place different from embodiment three is, the interlayer of the present embodiment non-immediate formation flood is situated between
Matter layer, and it is the increase in the step forming barrier layer 613, interlayer dielectric layer is separated into the first interlayer dielectric layer 611 and the
Two interlayer dielectric layers 612, as shown in figure 14.The making material on wherein this barrier layer 613 can be silicon nitride and carbonitride of silicium
A kind of at least within.The content of this step other parts refer to the corresponding contents in embodiment three.
Execution step S43, refer to Figure 14, forms first groove 660 in the second interlayer dielectric layer 612.
The present embodiment formed in the second interlayer dielectric layer 612 first groove 660 with shown in Fig. 7 in embodiment three in interlayer
First groove 560 is formed on dielectric layer 510 be similar to, difference is, the present embodiment is stopped with above-mentioned barrier layer 613 for etching
Only layer, and be that the second interlayer dielectric layer 612 of barrier layer 613 top is performed etching formation first groove 660, and it is located at resistance
First interlayer dielectric layer 611 of barrier 613 lower section is not then etched.This barrier layer 613 can be easy to accurately as etching end point
Control the depth of first groove 660.
Similar with embodiment three, the present embodiment is provided with Inorganic bottom antireflective above the second interlayer dielectric layer 612
Layer 650, its making material, technique and effect refer to related content in embodiment three.Likewise, the first interlayer dielectric layer
611 lower section setting etching stop layers 640, its making material, technique and effect also refer to related content in embodiment three.
Execution step S44, refer to Figure 15, forms protective layer in the bottom of first groove 660 shown in Figure 14 and side wall
620, first groove 660 is reduced to second groove 660 '.
The present embodiment, after completing the etching of first groove 660 as shown in figure 14, continues the side wall in first groove 660
Form protective layer 620 with bottom so that first groove 660 is reduced to second groove 660 '.It can further be seen that being similar to from Figure 15
In embodiment three, between protective layer 620 and the second interlayer dielectric layer 612, still retain this Inorganic bottom antireflective layer 650.
In the present embodiment, the making material of protective layer 620 includes a kind of at least within, its thickness of silicon nitride and carbonitride of silicium
Degree scope is 300 angstroms～1000 angstroms.The setting of this thickness refer to embodiment one related content.
Execution step S45, incorporated by reference to reference to Figure 16 and Figure 17, forms packed layer 670 in second groove 660 ' in fig .15,
The upper surface of packed layer 670 and the upper surface flush of the second interlayer dielectric layer 612.
Show in Figure 16, in the present embodiment, after defining second groove 660 ', form packed layer 670 filling second
Groove 660 ', refers to the related content in embodiment three.
Show in Figure 17, after the above step, packed layer 670 is planarized, to remove unnecessary packed layer
670 so as to packed layer 670 ' after becoming planarizing, and removes above-mentioned Inorganic bottom antireflective layer 650 simultaneously.This planarizing
The part that protective layer 620 is also located at the second interlayer dielectric layer 612 surface by step removes, and defines positioned at the first interlayer dielectric layer
First protective layer 621 of 611 tops and the second protective layer 622 being located at the second interlayer dielectric layer inwall.
Execution step S46, incorporated by reference to reference to Figure 17 and Figure 18, formed sequentially pass through from top to bottom packed layer 670 ', first
Protective layer 621 and the through hole of the first interlayer dielectric layer 611.
In the present embodiment, with reference first to Figure 17, the packed layer 670 ' after above-mentioned planarizing is upper to form Inorganic bottom anti-reflective
Penetrate layer 681 and organic bottom antireflective layer 682, and the photoresist layer of patterning is formed on organic bottom antireflective layer 682
683.Then with photoresist layer 683 as mask, etching forms and sequentially passes through packed layer 670 ', the first protective layer 621 from top to bottom
Through hole with the first interlayer dielectric layer 611（Do not mark）, in the present embodiment, this through hole runs through etching stop layer 640 simultaneously, such as schemes
Shown in 18.After the via is formed, removable photoresist layer 683 and organic bottom antireflective layer 682, and member-retaining portion inorganic bottom
Portion's anti-reflecting layer 681 forms remaining Inorganic bottom antireflective layer 681 ', and this process is most of with corresponding steps in embodiment three
Identical, refer to the related content of embodiment three.
This step is with embodiment three respective process difference, and in the present embodiment, the described through hole of formation passes through simultaneously
Wear barrier layer 613, thus in the via process forming the present embodiment, need to increase corresponding etch period, and to etching
Gas is also adjusted, for example, etching this barrier layer 613（Can be made by silicon nitride or carbonitride of silicium）When, Ke Yi
During the dry etching of plasma etching or reactive ion etching, with carbon dioxide and be aided with tetrafluoromethane gas conduct
Etching gas performs etching to this barrier layer 613.
Execution step S47, incorporated by reference to reference to Figure 19 and Figure 20, removes remaining packed layer 670 ', forms the 3rd groove
660”.
This step most contents are identical with embodiment three corresponding steps content, refer to the interior of embodiment three appropriate section
Hold, specifically, as shown in figure 19, form through hole shown in organic bottom anti-reflecting layer 691 filling Figure 18, this organic bottom antireflective
Layer 691 covers the Inorganic bottom antireflective layer 681 ' that left behind in above-mentioned steps simultaneously；Then in organic bottom antireflective layer
Form the photoresist layer 692 of patterning on 691, with photoresist layer 692 as mask, using dry etching, reactive ion etching or
Plasma etching removes part organic bottom antireflective layer 691, part Inorganic bottom antireflective layer 681 ' and remaining packed layer
670 ', form the 3rd groove 660 "（3rd groove 660 " dotted box portion as shown in Figure 20, the 3rd groove 660 " also may be used
Regard the space occupied by remaining packed layer 670 ' in original Figure 12 as）.
Form the 3rd groove 660 " after, also include remaining organic bottom antireflective layer 691 in the lower part of through hole
（Figure 20 is shown that to have eliminated the structure of this part organic bottom antireflective layer 691）, removable photoresist layer 692 and having
Motor spindle anti-reflecting layer 691, until exposing whole through hole, the contents of the section refers to embodiment three corresponding contents.
Execution step S48, refer to Fig. 6 and Figure 20, in the 3rd groove 660 " and through hole filling copper metal.
The present embodiment filling copper metal refers to embodiment three corresponding contents in the process of structure shown in Figure 20.Likewise,
The present embodiment by copper metal fill the 3rd groove 660 " and through hole after, this copper metal would generally be than the 3rd groove 660 " exceed
A part, this part copper metal can cover Inorganic bottom antireflective layer 681 ' surface, and again may be by planarizing mode makes
Obtain filled copper metal to flush with the second interlayer dielectric layer 612, and remove Inorganic bottom antireflective layer 681 ', form such as Fig. 6
Shown copper connector 631 and copper interconnecting line 632, concrete operations refer to corresponding contents in embodiment three.
By above-mentioned steps, the present embodiment forms structure as shown in Figure 6, and this structure is due to having the first protective layer 621 He
Second protective layer 622, can avoid copper interconnecting line 632 directly to connect with the first interlayer dielectric layer 611 and the second interlayer dielectric layer 612
Touch, protection the first interlayer dielectric layer 611 and the second interlayer dielectric layer 612 be not by copper interconnecting line 632 pressure break.
It should be noted that in the structure as shown in Figure 6 that ultimately forms of the present embodiment, below copper interconnecting line 632
Barrier layer 613 equally plays a protective role to the first interlayer dielectric layer 611, and is located at the first interlayer of copper interconnecting line 632 lower section
Dielectric layer 611 is just being affected by the place that copper interconnecting line 632 extrudes most serious, thus the present embodiment is in the first interlayer dielectric layer 611
And second the mode forming barrier layer 613 between interlayer dielectric layer 612 can protect the first interlayer dielectric layer 611 further.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope limiting is defined.
Claims (7)
1. a kind of manufacture method of copper interconnection structure is it is characterised in that include：
Semiconductor substrate is provided；
Form interlayer dielectric layer on the semiconductor substrate；
Form first groove in described interlayer dielectric layer；
Form protective layer in the side wall of described first groove and bottom, described first groove is reduced to second groove；
Form packed layer in described second groove, the upper surface of described packed layer is neat with the upper surface of described interlayer dielectric layer
Flat；
Form the through hole sequentially passing through described packed layer, described protective layer and described interlayer dielectric layer from top to bottom；
Remove remaining described packed layer, form the 3rd groove；
Fill copper metal in described 3rd groove and described through hole.
2. manufacture method as claimed in claim 1, it is characterised in that removing remaining described packed layer, forms the 3rd groove,
Including：
Form organic bottom anti-reflecting layer and fill described through hole；
Remove remaining described packed layer and partly described organic bottom anti-reflective layer, form described 3rd groove, remaining described
Organic bottom anti-reflective layer is flushed with the 3rd channel bottom；
Remove and be located at remaining described organic bottom anti-reflective layer in described through hole.
3. manufacture method as claimed in claim 1 is it is characterised in that the making material of described interlayer dielectric layer includes aoxidizing
Silicon.
4. manufacture method as claimed in claim 1 is it is characterised in that include barrier layer inside described interlayer dielectric layer；Described
First groove is with described barrier layer as bottom；Described through hole runs through described barrier layer.
5. manufacture method as claimed in claim 4 is it is characterised in that the making material on described barrier layer includes silicon nitride and carbon
One kind at least within of silicon nitride.
6. manufacture method as claimed in claim 1 is it is characterised in that the making material of described protective layer includes silicon nitride and carbon
One kind at least within of silicon nitride, its thickness range is 300 angstroms～1000 angstroms.
7. manufacture method as claimed in claim 1 is it is characterised in that the making material of described packed layer includes low temperature oxide
Material.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6472721B2 (en) * | 2000-07-24 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect structures that include radio frequency capacitors and inductors |
| CN1212653C (en) * | 2002-08-08 | 2005-07-27 | 联华电子股份有限公司 | Method for reducing cracking and deformation of copper wire |
| CN101043028A (en) * | 2006-03-23 | 2007-09-26 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6472721B2 (en) * | 2000-07-24 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect structures that include radio frequency capacitors and inductors |
| CN1212653C (en) * | 2002-08-08 | 2005-07-27 | 联华电子股份有限公司 | Method for reducing cracking and deformation of copper wire |
| CN101043028A (en) * | 2006-03-23 | 2007-09-26 | 恩益禧电子股份有限公司 | Semiconductor device and method of manufacturing the same |
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