CN104037124B - Form the semiconductor devices and method for the insertion conductive layer of power ground plane in FO-EWLB - Google Patents

Form the semiconductor devices and method for the insertion conductive layer of power ground plane in FO-EWLB Download PDF

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Publication number
CN104037124B
CN104037124B CN201410085270.7A CN201410085270A CN104037124B CN 104037124 B CN104037124 B CN 104037124B CN 201410085270 A CN201410085270 A CN 201410085270A CN 104037124 B CN104037124 B CN 104037124B
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conductive layer
semiconductor element
conductive
ground plane
layer
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CN104037124A (en
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林耀剑
包旭升
陈康
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Priority claimed from US14/193,267 external-priority patent/US9685350B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24175—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

A kind of semiconductor element that semiconductor devices has the first conductive layer and is adjacently positioned with first conductive layer.Sealant is deposited on first conductive layer and semiconductor element.Insulating layer is formed on the sealant, semiconductor element and the first conductive layer.It is formed on the insulating layer the second conductive layer.The first part of first conductive layer is electrically connected to VSSAnd form ground plane.The second part of first conductive layer is electrically connected to VDDAnd form power plane.First conductive layer, insulating layer and the second conductive layer constitute decoupling capacitors.The microstrip line of the trace including the second conductive layer is formed on the insulating layer and the first conductive layer.The first conductive layer is provided on being embedded in empty tube core, interconnecting unit or modularization PCB unit.

Description

Form the semiconductor device for the insertion conductive layer of power ground plane in FO-EWLB Part and method
It is required that domestic priority
This application claims the equity for the U.S. Provisional Application No. 61/774,692 that on March 8th, 2013 submits, this application passes through Reference is incorporated herein in.
Technical field
And, more specifically, it is related to being formed insertion conducting surface to be fanned out to formula the present invention relates generally to semiconductor devices It is embedded in wafer scale ball grid array (Fo-eWLB) and the semiconductor devices and method of power ground plane is provided.
Background technique
Semiconductor devices is often found in modern electronic product.Semiconductor devices is in terms of the number of electronic component and density It is different.Discrete-semiconductor device typically contains a type of electronic component, for example, light emitting diode (LED), small signal crystal Pipe, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor (MOSFET).Integrated semiconductor Device usually contains hundreds of to hundreds of thousands of electronic components.The example of integrated-semiconductor device include microcontroller, microprocessor, Charge-coupled device (CCD), solar battery and Digital Micromirror Device (DMD).
Semiconductor devices executes extensive function, such as signal processing, supercomputing, transmitting and reception electromagnetic signal, control Electronic device processed converts sunlight to electric power, and creates visual projection for television indicator.Turn in amusement, communication, power It changes, find semiconductor devices in the field of network, computer and consumer products.Also in Military Application, aviation, automobile, industry control Semiconductor devices is found in device and office equipment processed.
Semiconductor devices utilizes the electrical properties of semiconductor material.The structure of semiconductor material allows through electric field or base stage The application of electric current manipulates its electric conductivity by the process of doping.Doping adds impurities in semiconductor material, with manipulation With the electric conductivity of the semiconductor devices of control.
Semiconductor devices includes active and passive electrical structure.Active structure, including nesistor, control electricity The flowing of stream.By changing the application of doped level and electric field or base current, transistor promotes or the flowing of limitation electric current. Passive structures, including resistor, capacitor and inductor, creation execute between voltage and current necessary to various electrical functions Relationship.Passive and active structure is electrically connected to form circuit, this makes semiconductor devices be able to carry out high speed operation and other Useful function.
Generally come manufacturing semiconductor devices, i.e. front end manufacture and back-end manufacturing using two complicated manufacturing processes, it is each It is a to be all potentially related to hundreds of steps.Front end manufacture is related to the formation of multiple tube cores on the surface of semiconductor wafer.Each half Conductor tube core is usually identical, and includes to be formed by circuit by being electrically connected active and passive component.Back-end manufacturing relates to And (singulate) each semiconductor element is cut from the chip list of completion, and by die package to provide structural support and environment Isolation.As used herein term " semiconductor element " refers to two kinds of forms of odd number and plural number of the word, and therefore both may be used It may refer to multiple semiconductor devices to refer to single semiconductor devices also.
One target of semiconductors manufacture is the smaller semiconductor devices of production.Smaller device usually consumes less function Rate has higher performance, and can more effectively be produced.In addition, smaller semiconductor devices has smaller covering Area (footprint), this be for smaller end product it is desired.Smaller semi-conductor die size can be by generating tool There is the improvement during the front end of the semiconductor element of smaller, more highdensity active and passive component to realize.By electric mutual Even and the improvement in encapsulating material, back-end process can produce the semiconductor packages with the smaller area of coverage.
It is technical to realize that a method of smaller, thinner semiconductor devices concentrates on eWLB.One re-distribution layer is embedding The wafer scale BGA Package (1L eWLB) entered provides small, thin semiconductor devices, with high input/output (I/O) It counts and the semiconductor element with high routing density can be combined.In 1L eWLB, formed around semiconductor element close Agent is sealed, and forms a re-distribution layer (RDL) for being electrically interconnected on sealant and semiconductor element.During RDL is used as Interbed is with for the electrical interconnection in semiconductor devices, mutually including the electricity between the semiconductor element in device and the point of device exterior Even.The I/O counting that single RDL increases semiconductor devices is formed, thin encapsulation profile is maintained.However, in 1L eWLB In, power supply, signal and ground connection trace are all designed in single RDL, this is opposite with throughout multiple RDL.It is formed in single RDL Power supply, signal and ground networks eliminate and are dedicated to entire layer to provide the option of power supply and ground plane.In no Special electric In the case where source and ground plane, routing Design option is limited, because power supply and ground connection trace are needed across entire device quilt Routing is to form effective ground networks and power distribution network (PDN).Ground connection and electric power network consumption are formed in single RDL Valuable motionless resource (real estate) in RDL, and limit the space that can be used for signal traces.In addition, not having In the case where having Special grounding plane layer, reduce the Electrostatic Discharge protection in device.Finally, due to which 1L eWLB only has There are a conductive layer, i.e. RDL, therefore microstripline and decoupling capacitance cannot be formed in device.
Summary of the invention
In the presence of for forming the demand of ground connection and power plane without increasing package thickness in semiconductor devices.Therefore, In one embodiment, the present invention is a kind of method for making semiconductor devices, comprising the following steps: the first conductive layer is provided, It is disposed adjacently semiconductor element with first conductive layer, sealing is deposited on first conductive layer and semiconductor element Agent, and the second conductive layer is formed on first conductive layer and semiconductor element.
In another embodiment, the present invention is a kind of method for making semiconductor devices, comprising the following steps: provides the One conductive layer is disposed adjacently semiconductor element with first conductive layer, on first conductive layer and semiconductor element Form the second conductive layer.
In another embodiment, the present invention is a kind of semiconductor devices, including ground plane and with the ground plane phase The semiconductor element of neighbour's arrangement.Conductive layer is formed on the ground plane and semiconductor element.
In another embodiment, the present invention is a kind of semiconductor devices, including the first conductive layer and with it is described first conductive The semiconductor element that layer is adjacently positioned.Sealant is deposited on first conductive layer and semiconductor element.
Detailed description of the invention
Fig. 1 illustrates printed circuit board (PCB), have mounted to the different types of encapsulation of PCB surface；
Fig. 2 a-2d is illustrated with the semiconductor die by the separated multiple semiconductor elements of saw street (saw street) Piece；
Fig. 3 a-3k, which is illustrated, is adjacent to insertion conductive layer with semiconductor element to provide ground connection and power supply in Fo-eWLB The process of plane；
Fig. 4 illustrates the Fo-eWLB of the insertion conductive layer including providing ground connection and power plane in Fo-eWLB；
Fig. 5 illustrates the Fo-eWLB including being embedded in conductive layer and semiconductor element, wherein on the surface of semiconductor element Form ground plane；
Fig. 6 a-6 b illustrates the process to form the empty tube core including conductive layer (dummy die)；
Fig. 7 a-7d illustrates the process to form Fo-eWLB, which includes the insertion conduction being formed on empty tube core Layer；
Fig. 8 illustrates the Fo-eWLB including the insertion conductive layer being formed on empty tube core；
Fig. 9 illustrates the Fo-eWLB of the insertion 3D conductive layer including providing ground connection and power plane in Fo-eWLB；
Figure 10 a-10c illustrates the process to form modularization PCB unit；
Figure 11 a-11h, which is illustrated, is embedded in modularization PCB unit in Fo-eWLB to provide perpendicular interconnection and insertion conductive layer Process；And
Figure 12 illustrates the Fo-eWLB including being embedded in PCB unit.
Specific embodiment
In the following description referring to attached drawing, the present invention is described in one or more embodiments, wherein identical number Indicate the same or similar component.Although describing the present invention, ability according to the optimal mode for realizing the object of the invention Field technique personnel will be understood that the description is intended to cover as that can be included in the appended power supported by following disclosure and attached drawing Benefit require and the equivalent way of claim defined by alternative in the spirit and scope of the present invention, modification mode and wait Same mode.
Generally carry out manufacturing semiconductor devices using two complicated manufacturing processes: front end manufacture and back-end manufacturing.Front end system Make the formation of multiple tube cores on the surface for be related to semiconductor wafer.Each tube core on chip includes the active and passive electrical department of the Chinese Academy of Sciences Part is electrically connected to form functional circuitry.Active electric component, such as transistor and diode have control electric current The ability of flowing.Passive electrical component, such as capacitor, inductor and resistor create electricity necessary to execution circuit function Relationship between pressure and electric current.
Passive and active component is formed to be formed on the surface of semiconductor wafer by a series of process steps, including Doping, deposition, photoetching, etching and planarization.By the technology of such as ion implanting or thermal diffusion, doping, which adds impurities to, partly to be led In body material.Semiconductor material electric conductivity is dynamically changed and in response to electric field or base current, the modification of doping process has The electric conductivity of semiconductor material in the device of source.Transistor include different type and doping level region, be arranged to be When applying electric field or base current, transistor is enable to promote or limit necessary to the flowing of electric current.
Active and passive component is formed by the material layer with different electrical properties.The material type by being deposited can be passed through The various deposition techniques that part determines form these layers.For example, film deposition can be related to chemical vapor deposition (CVD), object Physical vapor deposition (PVD), electrolysis plating and electroless process.Generally by every pattern layers to form active parts, passive component Or each section of the electrical connection between component.
Back-end manufacturing refers to by the chip cutting of completion or being singly cut into each semiconductor element, and partly leads with post package Body tube core, to be used for structural support and be environmentally isolated.In order to singly cut semiconductor element, claimed by wafer notch and along chip It is disconnected for saw street or the non-functional area of scratch.Carry out wafer singulation using laser cutting tool or saw blade.It is each after singly cutting Semiconductor element is mounted to package substrate comprising for the pin or engagement pad with other systems component connection.Partly leading The engagement pad that engagement pad is subsequently attached in encapsulation is formed by body tube core.Can carry out with solder bump, stud bump, lead The electrical connection of electric cream or wire bonding.Sealant or other molding materials are deposited in encapsulation, it is exhausted to provide physical support and electricity Edge.Then, the encapsulation of completion is inserted into electricity system, and enables the function of semiconductor devices that other systems component is used.
Fig. 1 illustrates electronic devices 50, and with chip carrier substrate or PCB 52, plurality of semiconductor packages is pacified On the surface of PCB 52.Figure electronic device 50 can have a type of semiconductor packages or a plurality of types of partly lead Body encapsulation, this depends on application.For illustrative purposes, different types of semiconductor packages is shown in Fig. 1.
Electronic device 50 can be using semiconductor packages the autonomous system for executing one or more electrical functions.Substitution Ground, electronic device 50 can be the subassembly of bigger system.For example, electronic device 50 can be cellular phone, individual digital helps Manage a part of (PDA), digital camera (DVC) or other electronic communication devices.Alternatively, can be can quilt for electronic device 50 Graphics card, network interface card or other signal processing cards being inserted into computer.Semiconductor packages may include micro process Device, memory, specific integrated circuit (ASIC), logic circuit, analog circuit, rf circuitry, discrete device or other half Conductor tube core or electronic component.Miniaturization and weight reduction are essential for by the product received by market. The distance between semiconductor devices be can reduce to realize higher density.
In Fig. 1, PCB 52 provides common substrate by the structural support and electrical interconnection of the semiconductor packages installed on PCB. By using evaporation, electrolysis plating, electroless plating, silk-screen printing or other suitable metal deposition processes, on the surface of PCB 52 Conductive signal trace 54 is formed in upper or layer.Signal traces 54 provide the component and other external systems of semiconductor packages, installation Telecommunication between each of component.Trace 54 also provides power supply and grounding connection to each semiconductor packages.
In some embodiments, there are two package levels for semiconductor devices tool.First order encapsulation is for by semiconductor element Mechanically and electrically it is attached to the technology of intermediate vector.Second level encapsulation is related to intermediate vector being mechanically and electrically attached to PCB.? In other embodiments, semiconductor devices can only have first order encapsulation, and wherein tube core is directly mechanically and electrically installed to PCB。
For illustrative purposes, the first order encapsulation of several types, including bonding wire encapsulation 56 are shown on PCB 52 With flip-chip 58.In addition, the second of several types is grade packaged, including ball grid array (BGA) 60, bump chip carrier (BCC) 62, contact grid array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70, quad flat envelope It fills 72, embedded wafer scale ball grid array (eWLB) 74 and wafer level chip scale encapsulation (WLCSP) 76 is shown as installing On PCB 52.EWLB 74 is to be fanned out to formula wafer-class encapsulation (Fo-WLP), and WLCSP 76 is fan-in formula wafer-class encapsulation (Fi- WLP).According to system requirements, any combination of semiconductor packages and other electricity configured with first and second grades of encapsulation styles Any combination of subassembly may be connected to PCB 52.In some embodiments, electronic device 50 includes half individually adhered to Conductor encapsulation, and other embodiments then require the encapsulation of multiple interconnection.It is partly led by combining one or more on a single substrate The component of pre-production can be integrated in electronic device and system by body encapsulation, manufacturer.Because semiconductor packages includes multiple Miscellaneous function can manufacture electronic device by using less expensive component and fairshaped manufacturing process.It is obtained Device is unlikely to occur failure and manufactures less valuableness, and which results in for the more inexpensive of consumer.
Fig. 2 a shows semiconductor wafer 120, have for structural support base portion substrate material 122, such as silicon, Germanium, GaAs, indium phosphide or silicon carbide.As described above, separated by wafer area between non-effective, tube core or saw street 126 Chip 120 on form multiple semiconductor elements or component 124.Saw street 126 provides cutting region for semiconductor wafer 120 Singly it is cut into each semiconductor element 124.In one embodiment, semiconductor wafer 120 has the width of 200-300 millimeters (mm) Or diameter.In another embodiment, semiconductor wafer 120 has the width or diameter of 100-450mm.
Fig. 2 b shows the sectional view of a part of semiconductor wafer 120.Scheme each semiconductor element 124 with the back side or Non-effective surface 128 and active surface 130, it includes be implemented as being formed by active device, passive device, conduction in tube core Layer and dielectric layer, and according to the analog or digital circuit of the electrical design of tube core and function and electricity interlinkage.For example, the circuit It may include that one or more transistors, diode and other circuit elements are formed by active surface 130, to realize mould Quasi- circuit or digital circuit, such as digital signal processor (DSP), ASIC, memory or other signal processing circuits.Semiconductor Tube core 124 can also include the integrated passive devices (IPD) for RF signal processing, such as inductor, capacitor and resistor. In one embodiment, semiconductor element 124 is flip-chip semiconductor tube core.
Using PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes, in effective table Conductive layer 132 is formed on face 130.Conductive layer 132 can be aluminium (Al), copper (Cu), tin (Sn), nickel (Ni), golden (Au), silver-colored (Ag) Or one or more layers of other suitable conductive materials.The operation of conductive layer 132 is the circuit being electrically connected on active surface 130 Engagement pad.Conductive layer 132 can be formed to be arranged side by side in the engagement pad of the edge first distance from semiconductor element 124, As shown in figure 2b.Alternatively, conductive layer 132 can be formed the engagement pad deviated in multiple rows, so that the first row engagement pad It is disposed in the first distance from die edge, and is disposed in the alternate second row engagement pad of the first row from die edge Second distance.
Semiconductor wafer 120 is subjected to the electrical testing and inspection of a part as quality control process.Artificial vision's inspection It looks into and is used to execute inspection to semiconductor wafer 120 with automated optical system.Software can be used in oneself of semiconductor wafer 120 In dynamic optical analysis.Vision inspection method can be using such as scanning electron microscope, high intensity or ultraviolet (UV) light or metallographic Microscopical equipment.For special including warpage, thickness change, surface particles, scrambling, crackle, layering and the structure of discoloration Property checks semiconductor wafer 120.
Active and passive component in semiconductor element 124 is subjected to the survey for electric property and circuit function in wafer scale Examination.As illustrated in fig. 2 c, using probe 136 or other test devices, for function and electrical parameter, to each semiconductor element 124 are tested.Test probe 136 includes multiple probes 138.Probe 138 is used to and the section on each semiconductor element 124 Point or engagement pad 132 are electrically connected, and electro photoluminescence is supplied to engagement pad.Semiconductor element 124 responds electro photoluminescence, The electro photoluminescence is compared as measured by computer testing system 140 and with the expected response of the test function to semiconductor element Compared with.Electrical testing may include circuit function, lead integrality, resistive, continuity, reliability, junction depth, ESD, RF performance, Driving current, threshold current, leakage current and the operating parameter specific to unit type.The inspection and electricity of semiconductor wafer 120 Test enables qualified semiconductor element 124 to be designated for known good tube core (KGD) used in semiconductor packages.
In figure 2d, semiconductor wafer 120 is singly cut into via saw street 126 using saw blade or laser cutting tool 142 Each semiconductor element 124.Inspection and electrical testing can be carried out to each semiconductor element 124, for the KGD after singly cutting Identification.
Related with Fig. 1, Fig. 3 a-3k, which is illustrated, is adjacent to insertion conductive layer with semiconductor element to provide in Fo-eWLB The process of ground connection and power plane.Fig. 3 a show comprising for such as silicon of structural support, polymer, beryllium oxide, glass or The sectional view of other suitable low costs, a part of the carrier of the sacrifice base material of rigid material or temporary substrates 160.? In one embodiment, carrier 160 is carrier band.Boundary layer or double-sided tape 162 is formed on carrier 160 to engage as temporary adhesive Film, etching stopping layer or hot releasing layer.
Carrier 160 can be round or rectangular panel (being greater than 300mm), have the appearance for multiple semiconductor elements 124 Amount.Carrier 160 can have the surface area bigger than the surface area of semiconductor wafer 120.Bigger carrier reduces semiconductor package The manufacturing cost of dress, because more semiconductor elements can be handled on bigger carrier, to reduce the cost of per unit.Half Conductor encapsulation and processing equipment are to be directed to the size of chip or carrier being processed and design and configure.
In order to further decrease manufacturing cost, the size of carrier 160 is independently of the size of semiconductor element 124 or partly leads The size of body chip 120 carrys out selection.That is, carrier 160 has fixed or standardized size, can accommodate from one or more The semiconductor element 124 for the various sizes that a semiconductor wafer 120 is singly cut.In one embodiment, carrier 160 is that have The circle of the diameter of 330mm.In another embodiment, carrier 160 is the square with the length of width and 600mm of 560mm Shape.Semiconductor element 124 can have the scale that 10mm multiplies 10mm, be placed on standardized carrier 160.Alternatively, The scale that semiconductor element 124 can have 20mm to multiply 20mm is placed on identical standard carriers 160.Therefore, standard The semiconductor element 124 of any size can be handled by changing carrier 160, this allows subsequent semiconductor processing equipment to be standardized as altogether Carrier, that is, independently of die-size or introduce wafer size.By using a set of shared handling implement, equipment and material Inventory is expected to handle from any any semi-conductor die size for introducing wafer size, and semiconductor packaging device can be for mark Quasi- carrier and be designed and configured.By reducing or eliminating at the dedicated semiconductor based on die-size or introducing wafer size The needs of lineation, share or standardized carrier 160 reduces manufacturing cost and capital risk.By selecting predetermined carrier dimensions So that the semiconductor element of any size from all semiconductor wafers uses, flexible manufacturing line may be implemented.
In fig 3b, conductive layer 164 is formed on carrier 160 and boundary layer 162.Conductive layer 164 include Al, Cu, Sn, Ni, Au, Ag, Ti, W or other suitable conductive materials.Conductive layer 164 is formed the lamination on carrier 160 and boundary layer 162 Plate or band.Conductive layer 164 may include patterned lead frame, patterned copper foil, the resin painting with patterned copper (RCC) band covered or the prepreg (prepeg) with patterned copper.Alternatively, using PVD, CVD, electrolysis plating, without electricity Plating process or other suitable metal deposition processes to form conductive layer 164 on carrier 160 and boundary layer 162.
In figure 3 c, the semiconductor element 124 from Fig. 2 d is installed to carrier using such as pickup and placement operation 160 and boundary layer 162, wherein active surface 130 is positioned towards carrier 160.Conductive layer 164 is placed in semiconductor element 124 In neighboring area.Alternatively, conductive layer can be formed after semiconductor element 124 is installed to carrier 160 and boundary layer 162 164.Fig. 3 d, which is shown, is installed to carrier 160 as reconstruct or the semiconductor element 124 and conductive layer of the chip 166 reconfigured 164。
Fig. 3 e shows the plan view of the semiconductor element 124 and conductive layer 164 that are installed to boundary layer 162 and carrier 160. Conductive layer includes three parts 164a, 64b and 164c.Part is disposed adjacently with three side surfaces of semiconductor element 124 164a-164c.Alternatively, conductive layer 164 may include two portions being disposed adjacently with two side surfaces of semiconductor element 124 Four parts divide, arranged around four side surfaces of semiconductor element 124 or a side table with semiconductor element 124 Two parts that face is disposed adjacently.It, can be adjacent with semiconductor element 124 according to the routing Design and function of semiconductor packages The conductive layer 164 of any quantity and/or configuration is arranged on ground.
In Fig. 3 f, using paste printing, it is compression molded, transfer molding, hydraulic seal molding, vacuum lamination, spin coating or Other suitable applicators to deposit sealant or molding on semiconductor element 124, conductive layer 164a-164c and carrier 160 Compound 168.Sealant 168 can be polymer composites, the epoxy resin such as with filler, the epoxy with filler Acrylates or polymer with appropriate filler.Sealant 168 is non-conductive and protects semiconductor devices in the environment From external elements and pollutant effects.Sealant 168 also protects semiconductor element 124 from causing by exposure to light Deterioration.In one embodiment, sealant 168 is removed from the surface of sealant 168 170 into grinding steps after subsequent A part.Backward grinding operation makes the surface plane of sealant 168 and reduces the overall thickness of reconstructed wafer 166.With table The surface 172 of the opposite sealant 168 in face 170 is placed on carrier 160 and boundary layer 162, so that the surface of sealant 168 172 is substantially coplanar with the active surface 130 of semiconductor element 124.
In Fig. 3 g, is dried by chemical etching, mechanical stripping, chemical-mechanical planarization (CMP), mechanical lapping, heat, is ultraviolet Light, laser scanning or wet type strip (wet stripping) to remove carrier 160 and boundary layer 162.Remove carrier 160 and boundary Surface layer 162 exposes the active surface 130 and conductive layer 164a-164c on the surface 172 of sealant 168, semiconductor element 124.
In Fig. 3 h, using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come in sealant 168 Surface 172, the active surface 130 of semiconductor element 124 form insulating layer or passivation layer 180 on conductive layer 164a-164c.Absolutely Edge layer 180 includes silica (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), oxidation One or more layers of aluminium (Al2O3) or the other materials with similar insulation and structural property.It is directly cut off by laser (LDA), etching or other suitable processes remove a part of insulating layer 180 to expose conductive layer 132 and conductive layer 164a- The part of 164c.
In Fig. 3 i, insulated using such as spraying plating, electrolysis plating or electroless patterning and metal deposition process Conductive layer or RDL 182 are formed on layer 180.Conductive layer 182 can be Al, Cu, Sn, Ni, Au, Ag or other suitable conduction materials One or more layers of material.A part of conductive layer 182 is electrically connected to conductive layer 132.The other parts of conductive layer 182 are electric It shares or is electrically isolating on, this depends on the Design and Features of semiconductor element 124.Conductive layer 182 is by transistor Core 124 is electrically connected to insertion conductive layer 164a-164c.Conductive layer 182 provides signal routing and power supply in semiconductor packages And grounding connection.
In Fig. 3 j, using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come in 180 and of insulating layer Insulating layer or passivation layer 184 are formed on conductive layer 182.Insulating layer 184 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or tool There are one or more layers of the other materials of similar insulation and structural property.It is made a return journey by LDA, etching or other suitable processes Except a part of insulating layer 184 is to expose conductive layer 182.
In Fig. 3 k, it is electroplated using evaporation, electrolysis, electroless plating, ball are fallen or screen printing process comes on conductive layer 182 Deposit conductive salient point material.Convex point material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, and having can Choosing helps weldering solution.For example, convex point material can be eutectic tin/lead, high kupper solder or lead-free solder.Using suitable attachment or Engaging process engages convex point material to conductive layer 182.In one embodiment, by heating the material to the fusing point of material On so that convex point material is flowed back to form ball or salient point 186.In some applications, make second of salient point 186 reflux to improve With the electrical contact of conductive layer 182.In one embodiment, salient point 186 is formed under salient point and metallizes on (UBM) layer.Salient point 186 also can be compressed engagement or hot compression engagement to conductive layer 182.Salient point 186 indicates the one kind that may be formed on conductive layer 182 The interconnection structure of type.Bonding wire, conductive paste, stud bump, miniature salient point or other electrical interconnections can also be used in interconnection structure.
Conductive layer 164a-164c is electrically connected to salient point 186 to be used for and exterior positive electrode pressure side via conductive layer 182 (VDD) or negative voltage terminal (VSS) connection.Conductive layer 164a may be connected to VDDOr VSS.Conductive layer 164b can be connected To VDDOr VSS.Conductive layer 164c may be connected to VDDOr VSS.In one embodiment, conductive layer 164a is connected to VDD, Conductive layer 164b is connected to VSSAnd conductive layer 164c is connected to VSS。VDDIt may be connected to conductive layer 164a, conduction Layer 164b and/or conductive layer 164c.Vss may be connected to conductive layer 164a, conductive layer 164b and/or conductive layer 164c.
It is connected to VSSConductive layer 164a-164c part formed ground plane.It is connected to VDDConductive layer 164a- The part of 164c forms power plane.It is disposed under insulating layer 180 by the ground plane that conductive layer 164a-164c is provided, And it is electrically isolated with the signal traces of conductive layer 182.In semiconductor element 124 and the power supply provided by conductive layer 164a-164c The power trace of conductive layer 182 is formed between plane.Power trace is by being connected to any part of power plane come to partly leading Body tube core 124 provides power.The position of the position (i.e. conductive layer 164a-164c) and power trace that select power plane is come most Smallization trace length.
Reconstructed wafer 166 is singly cut into each Fo-eWLB via sealant 168 using saw blade or laser cutting tool 188 200.Fig. 4 shows the Fo-eWLB after singly cutting 200.Semiconductor element 124 is electrically connected to salient point 186 via conductive layer 182 For the connection with external device (ED) (for example, PCB).Conductive layer 164a-164c is embedded in the peripheral region of semiconductor element 124 In sealant 168 in domain.Conductive layer 164a-164c is electrically connected to salient point 186 to be used for and outside V via conductive layer 182DD Or VSSConnection.It is embedded in conductive layer 164a-164c and forms the ground connection and power plane adjacent with semiconductor element 124.Insertion is led Electric layer 164a-164c provides ground connection and power plane without forming additional RDL on conductive layer 182.Less RDL is formed to increase Add package reliability and reduces the overall thickness of Fo-eWLB 200.
It is adjacent to semiconductor element 124 and forms power plane and increase flexibility in routing Design.It can be by power supply Trace is connected to any part of power plane, and conductive layer 164a-164c can be placed in and need VDDConnection anyly Side.Increased flexibility allows most short possible trace length in routing Design.The trace length of reduction produces more effectively PDN and the speed and function for increasing Fo-eWLB 200.
Be disposed under insulating layer 180 by the ground plane that conductive layer 164a-164c is provided, and with conductive layer 182 Signal traces be electrically isolated.The signal traces of insulating layer 180 and conductive layer 182 are placed on ground plane and are promoted across Fo- The formation of the microstrip line of eWLB 200.Microstrip line transmitting microwave frequency signal and allow microwave component (for example, antenna, coupler, Filter, power divider etc.) it is incorporated into Fo-eWLB 200.Ground plane is formed to also add in Fo-eWLB 200 ESD protection.
Insertion conductive layer 164a-164c provides the additional conductive layer in Fo-eWLB 200.Additional conductive layer is used for shape At decoupling capacitors.Power supply is designed in a part by conductive layer 182 and conductive layer 164a-164c on insulating layer 180 Network forms decoupling capacitors.In one embodiment, supply power to the electric power network of semiconductor element 124, i.e., it is conductive The trace of layer 182, is designed to throughout conductive layer 164c, so that electric power network, insulating layer 180 and conductive layer 164c form decoupling Capacitor.Decoupling capacitors are integrated to the electricity for reducing voltage fluctuation in Fo-eWLB 200 and increasing Fo-eWLB 200 Performance.
Conductive layer 164a-164c is formed laminate or band on carrier 160.Compared to needing complicated, height control, high The formation of expensive and time-consuming manufacturing step adds RDL, formed on carrier 160 conductive layer 164a-164c be faster, it is less expensive And more low-risk.It to form conductive layer 164a-164c by being adjacent to semiconductor element 124 power supply and ground plane is provided And additional conductive layer, manufacturing time is reduced, handling capacity is increased, and reduces the totle drilling cost of Fo-eWLB 200.Insertion is led Electric layer 164a-164c increases the electric property and function of Fo-eWLB 200, without increasing package thickness.
Fig. 5 shows the Fo-eWLB 220 similar with the Fo-eWLB 200 in Fig. 4.Fo-eWLB 220 includes from similar In the semiconductor element 224 that the chip of chip 120 is singly cut.Semiconductor element 224 has the back side or non-effective surface 228 and has Surface 230 is imitated, it includes being implemented as being formed by active device, passive device, conductive layer and dielectric layer in tube core, and root According to the electrical design of tube core and the analog or digital circuit of function and electricity interlinkage.For example, the circuit may include active surface 230 One or more transistors, diode and other circuit elements are inside formed by, to realize analog circuit or digital circuit, Such as DSP, ASIC, memory or other signal processing circuits.Semiconductor element 224 can also be comprising for RF signal processing IPD, such as inductor, capacitor and resistor.
Using PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes, in effective table Conductive layer 232 is formed on face 230.Conductive layer 232 can be the one of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials A or multiple layers.The operation of conductive layer 232 is the engagement pad for the circuit being electrically connected on active surface 230.Conductive layer 232 can be by shape As the engagement pad for being arranged side by side in the edge first distance from semiconductor element 224.Alternatively, conductive layer 32 can be formed The engagement pad deviated in multiple rows, so that the first row engagement pad is disposed in the first distance from die edge, and and the first row Alternate second row engagement pad is disposed in the second distance from die edge.
It is exhausted to be formed on semiconductor element 224 using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide Edge layer or passivation layer 234.Insulating layer 234 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or has similar to insulation and structure One or more layers of the other materials of property.A part of insulating layer is removed by LDA, etching or other suitable processes 234 to expose conductive layer 232.
Using PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes, in insulating layer Conductive layer 236 is formed on 234.Conductive layer 236 can be Al, Cu, Sn, Ni, Au, Ag or one of other suitable conductive materials Or multiple layers.Conductive layer 236 is formed on semiconductor element 224 with wafer scale (i.e. before singly cutting).Via 182 He of conductive layer Conductive layer 236 is electrically connected to external V by salient point 186SS.Conductive layer 236 forms the additional ground plane in Fo-eWLB 220.
Fig. 6 a-6b illustrates the process to form the empty tube core including conductive layer.Fig. 6 a shows the one of semiconductor wafer 240 Partial sectional view has the base portion substrate material 242 for structural support, such as silicon, germanium, GaAs, indium phosphide or carbon SiClx.Multiple empty tube cores 250 are formed on chip 240.Void is separated by wafer area between non-effective, tube core or saw street 248 Tube core 250.Saw street 248 provides cutting region and semiconductor wafer 240 is singly cut into each empty tube core 250.Implement at one In example, semiconductor wafer 240 has the width or diameter of 200-300mm.In another embodiment, semiconductor wafer 240240 Width or diameter with 100-450mm.
Each void tube core has opposite surface 244 and 246.Using PVD, CVD, electrolysis plating, electroless process or Other suitable metal deposition processes form conductive layer 252 on active surface 244.Conductive layer 252 can be Al, Cu, One or more layers of Sn, Ni, Au, Ag or other suitable conductive materials.In one embodiment, conductive layer 252 is plating Cu.
In figure 6b, semiconductor wafer 240 is singly cut into via saw street 248 using saw blade or laser cutting tool 254 Each empty tube core 250 including conductive layer 252.Empty tube core 250 can be cut to arbitrary dimension or shape with coverlet, this depends on combining The routing Design and function of the semiconductor packages of empty tube core 250.
Related with Fig. 1, Fig. 7 a-7d illustrates the process to form Fo-eWLB, which includes being formed on empty tube core Insertion conductive layer.Fig. 7 a is shown comprising for such as silicon of structural support, polymer, beryllium oxide, glass or other are suitable Low cost, the sacrifice base material of rigid material be similar to Fig. 3 a in carrier 160 carrier or temporary substrates 260 one Partial sectional view.In one embodiment, carrier 260 is carrier band.Boundary layer or double-sided tape 262 are formed on carrier 260 As temporary adhesive junction film, etching stopping layer or hot releasing layer.
By the semiconductor element 124 from Fig. 2 d and Fig. 6 b void tube core 250a- is come from using such as pickup and placement operation 250c is installed to boundary layer 262 and carrier 260, wherein the active surface 130 of semiconductor element 124 and empty tube core 250a-250c Conductive layer 252a-252c towards carrier 260 position.In one embodiment, it similar to the conductive layer 236 in Fig. 5, is partly leading Ground plane layer is formed on the surface 130 of body tube core 124.
Fig. 7 b, which is shown, to be arranged on carrier 260 as reconstruct or 124 He of semiconductor element of the chip 266 reconfigured Empty tube core 250a-250c.Half is disposed in similar to conductive layer 164a, 164b and 164c in Fig. 3 e, empty tube core 250a-250c Around the side surface of conductor tube core 124.It alternatively, can be with a side surface of semiconductor element 124, semiconductor element 124 Two side surfaces are disposed adjacently or arrange around all side surfaces of semiconductor element 124 empty tube core 250a-150c.Root According to the routing Design and function of semiconductor packages, any quantity and/or configuration can be disposed adjacently with semiconductor element 124 Empty tube core 250.
Using paste printing, it is compression molded, transfer molding, hydraulic seal molding, vacuum lamination, spin coating or other suitably Applicator to deposit sealant or mold compound 268 on semiconductor element 124, void tube core 250a-250c and carrier 260. Sealant 268 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler, Or the polymer with appropriate filler.Sealant 268 is non-conductive and protects semiconductor devices from outside in the environment Element and pollutant effects.Sealant 268 also protects semiconductor element 124 from by exposure to deterioration caused by light. In one embodiment, one of sealant 268 is removed from the surface of sealant 268 270 into grinding steps after subsequent Point.Backward grinding operation makes the surface plane of sealant 268 and reduces the overall thickness of reconstructed wafer 266.With 270 phase of surface Pair the surface 272 of sealant 268 be placed on carrier 260 and boundary layer 262 so that the surface 272 of sealant 268 with partly lead The conductive layer 252 of the active surface 130 of body tube core 124 and empty tube core 250 is substantially coplanar.
In figure 7 c, pass through chemical etching, mechanical stripping, CMP, mechanical lapping, hot baking, ultraviolet light, laser scanning or wet Formula strips to remove carrier 260 and boundary layer 262.Removal carrier 260 and boundary layer 262 expose the surface of sealant 268 272, the conductive layer 252a-252c of the active surface 130 of semiconductor element 124 and empty tube core 250a-250c.
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come on the surface of sealant 268 272, half Insulating layer or passivation layer are formed on the active surface 130 of conductor tube core 124, the conductive layer 252a-252c of void tube core 250a-252c 280.Insulating layer 280 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or other materials with similar insulation and structural property One or more layers of material.A part of insulating layer 280 is removed by LDA, etching or other suitable processes to expose conduction 132 and conductive layer 252a-252c of layer.
Using such as spraying plating, electrolysis plating or electroless patterning and metal deposition process come the shape on insulating layer 280 At conductive layer or RDL 282.Conductive layer 282 can be Al, Cu, Sn, Ni, Au, Ag or one of other suitable conductive materials Or multiple layers.A part of conductive layer 282 is electrically connected to conductive layer 132.The other parts of conductive layer 282 are electrically shared Or be electrically isolating, this depends on the Design and Features of semiconductor element 124.Semiconductor element 124 is electrically connected by conductive layer 282 It is connected to conductive layer 252a-252c.Conductive layer 282 provides signal routing and power supply and grounding connection in semiconductor packages.
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come in insulating layer 280 and conductive layer 282 Upper formation insulating layer or passivation layer 284.Insulating layer 284 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or has similar exhausted One or more layers of the other materials of edge and structural property.A part is removed by LDA, etching or other suitable processes Insulating layer 284 is to expose conductive layer 282.
In figure 7d, it is electroplated using evaporation, electrolysis, electroless plating, ball are fallen or screen printing process comes on conductive layer 282 Deposit conductive salient point material.Convex point material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, and having can Choosing helps weldering solution.For example, convex point material can be eutectic tin/lead, high kupper solder or lead-free solder.Using suitable attachment or Engaging process engages convex point material to conductive layer 282.In one embodiment, by heating the material to the fusing point of material On so that convex point material is flowed back to form ball or salient point 286.In some applications, make second of salient point 286 reflux to improve With the electrical contact of conductive layer 282.In one embodiment, salient point 286 is formed on UBM layer.Salient point 286, which also can be compressed, to be connect It closes or hot compression engagement is to conductive layer 282.Salient point 286 indicates a type of interconnection structure that may be formed on conductive layer 282. Bonding wire, conductive paste, stud bump, miniature salient point or other electrical interconnections can also be used in interconnection structure.
Conductive layer 252a-252c is electrically connected to salient point 286 to be used for and outside V via conductive layer 282SSOr VDDCompany It connects.Conductive layer 252a may be connected to VSSOr VDD.Conductive layer 252c may be connected to VSSOr VDD.In one embodiment, Conductive layer 252a is connected to VDD, and conductive layer 252c is connected to VSS。VDDMay be connected to conductive layer 252a and/or Conductive layer 252c.Vss may be connected to conductive layer 252a and/or conductive layer 252c.
It is connected to VSSConductive layer 252a-252c formed ground plane.It is connected to VDDConductive layer 252a-252c formed Power plane.Be disposed under insulating layer 280 by the ground plane that conductive layer 252a-252c is provided, and with conductive layer 282 Signal traces be electrically isolated.Conduction is provided between semiconductor element 124 and the power plane provided by conductive layer 252a-252c The power trace of layer 282.Power trace provides function to semiconductor element 124 by being connected to any part of power plane Rate.The position of selection power plane (is attached to VDDConductive layer 252a-252c) and the position of power trace minimize Trace length.
Reconstructed wafer 266 is singly cut into each Fo-eWLB via sealant 268 using saw blade or laser cutting tool 288 300.Fig. 8 shows the Fo-eWLB after singly cutting 300.Semiconductor element 124 is electrically connected to salient point 286 via conductive layer 282 For the connection with external device (ED) (for example, PCB).Empty tube core 250a-250c is embedded in the peripheral region of semiconductor element 124 In sealant 268 in domain.Conductive layer 252a-252c is electrically connected to salient point 286 to be used for and outside V via conductive layer 282SS Or VDDConnection.Conductive layer 252a-252c forms the ground connection and power plane adjacent with semiconductor element 124.It is embedded in empty tube core 250a-250c and conductive layer 252a-252c provides ground connection and power plane without forming additional RDL on conductive layer 282. Form the overall thickness that less RDL increases package reliability and reduces Fo-eWLB 300.
Power plane is formed by being disposed adjacently empty tube core with semiconductor element 124 increases spirit in routing Design Activity.Empty tube core 250a-250c can be arranged in from anywhere in needing power supply to connect, and power trace can be connected To any part of conductive layer 252a-252c.Increased flexibility allows most short possible trace length in routing Design.It reduces Trace length produce more effective PDN and increase the speed and function of Fo-eWLB 300.
Be disposed under insulating layer 280 by the ground plane that conductive layer 252a-252c is provided, and with conductive layer 282 Signal traces be electrically isolated.The signal traces of insulating layer 280 and conductive layer 282 are placed on ground plane and are promoted across Fo- The formation of the microstrip line of eWLB 300.Microstrip line transmitting microwave frequency signal and allow microwave component (for example, antenna, coupler, Filter, power divider etc.) it is incorporated into Fo-eWLB 300.Ground plane is formed to also add in Fo-eWLB 300 ESD protection.
Insertion void tube core 250a-250c provides the additional conductive layer in Fo-eWLB 300.Additional conductive layer is used for shape At decoupling capacitors.Power supply is designed in a part by conductive layer 282 and conductive layer 252a-252c on insulating layer 280 Network forms decoupling capacitors.In one embodiment, supply power to the electric power network of semiconductor element 124, i.e., it is conductive The trace of layer 282, is designed to throughout conductive layer 252c, so that electric power network, insulating layer 280 and conductive layer 252c form decoupling Capacitor.Decoupling capacitors are integrated to the electricity for reducing voltage fluctuation in Fo-eWLB 300 and increasing Fo-eWLB 300 Performance.
Conductive layer 252a-252c is formed in empty tube core 250a- (i.e. before singly the cutting of chip 240) on a wafer level On 250c.It can form conductive layer 252a-252c, and arbitrary shape and size can be cut by empty tube core 250a-250c is mono-, This depends on the design and route request of semiconductor element 124 and Fo-eWLB 300.Void is managed using picking up with laying method Core 250a-250c is installed to carrier 260.Compared to needing, complicated, height is controlled, the formation of costly and time-consuming manufacturing step adds RDL, by preformed void tube core 250a-252c and conductive layer 252a-252c be installed to carrier 260 be faster, it is less expensive And more low-risk.Additional conductive layer and ground connection and power plane are provided by insertion void tube core 250a-250c to reduce Manufacturing time, the totle drilling cost for increasing handling capacity and reducing Fo-eWLB 300.Insertion void tube core 250a-250c is increased The electric property and function of Fo-eWLB 300, without increasing package thickness.
Fig. 9 shows including semiconductor element 124 and is embedded in the Fo- of three-dimensional (3D) interconnecting unit or interposer 312 310 interconnecting unit 312 of eWLB includes insulating layer 314,318 and 322 and conductive layer 316,320 and 324.In one embodiment In, interconnecting unit 312 includes with phenolic aldehyde cotton paper, epoxides, resin, establishment glass, obscured glass, polyester or other enhancings One or more layers of the prepreg (prepreg) of fiber or fabric, FR-4, FR-1, CEM-1 or CEM-3.Interconnecting unit 312 Can also be layer flexible laminate, ceramics, copper foil, glass or the semiconductor wafer including active surface, it includes one or Multiple transistors, diode or other circuit elements are to realize analog circuit or digital circuit.
The insulating layer of interconnecting unit 312 is formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide 314,318 and 322.Insulating layer 314,318 and 322 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or insulate with similar With one or more layers of the other materials of structural property.Use such as spraying plating, electrolysis plating or electroless patterning and gold Belong to deposition process to form the conductive layer 316,320 and 324 of interconnecting unit 312.Conductive layer 316,320 and 324 can be Al, One or more layers of Cu, Sn, Ni, Au, Ag, Ti, W or other suitable conductive materials.Conductive layer 316,320 and 324 includes Lateral RDL and vertical conduction through-hole, and the electrical interconnection by Fo-eWLB 310 is provided.The part 316a and conduction of conductive layer 316 The part 324a of layer 324 is electrically connected via the part 320a of conductive layer 329.The part 316a and conductive layer 324 of conductive layer 316 Part 324a be electrically connected via the part 320b of conductive layer 320.One part 316a is electrically connected to external VSSAnd it is formed Ground plane in Fo-eWLB 310.Another part 316a is electrically connected to external VDDAnd form the electricity in Fo-eWLB 310 Source plane.The other parts of conductive layer 316,320 and 324 are electrically shared or are electrically isolating, this depends on Fo-eWLB 310 routing Design and function.
Similar to conductive layer 164a, 164b and 164c in Fig. 3 e, interconnecting unit 312 is disposed in semiconductor element 124 Three side surfaces around.It alternatively, can be with two side tables of a side surface of semiconductor element 124, semiconductor element 124 Face is disposed adjacently or arranges around all four side surfaces of semiconductor element 124 interconnecting unit 312.According to Fo-eWLB 310 routing Design and function can be disposed adjacently the interconnecting unit of any quantity and/or configuration with semiconductor element 124 312.In one embodiment, similar to the conductive layer 236 in Fig. 5, ground connection is formed on the surface of semiconductor element 124 130 Plane layer.
Using paste printing, it is compression molded, transfer molding, hydraulic seal molding, vacuum lamination, spin coating or other suitably Applicator to deposit sealant or mold compound 328 on semiconductor element 124 and interconnecting unit 312.Sealant 328 can be with Polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have appropriate filler Polymer.Sealant 328 is non-conductive and protects semiconductor devices from external elements and pollutant in the environment It influences.Sealant 328 also protects semiconductor element 124 from by exposure to deterioration caused by light.In one embodiment, Remove a part of sealant 328 from the surface of sealant 328 330 into grinding steps after subsequent.Backward grinding operation Make the surface plane of sealant 328 and reduces the overall thickness of Fo-eWLB 310.The sealant 328 opposite with surface 330 Surface 332 and the active surface 130 of semiconductor element 124 are substantially coplanar.
Multiple openings 333 are formed in the surface of sealant 328 330.By LDA, etching or other suitable processes come Form opening 333.Opening 333 exposes the part of conductive layer 324, serves as engagement pad and promotes Fo-eWLB 310 and partly lead The electrical interconnection between component stacked on body tube core or Fo-eWLB 310.Opening 333a exposes ground mat and power source pad.Ground connection Pad is the part of conductive layer 324, is coupled to the ground plane portion 316a of conductive layer 316.Power source pad is conductive layer 324 Part is coupled to the power plane part 316a of conductive layer 316.Opening 333b exposes signal pad.Signal pad is conductive The part of layer 324 promotes the routing between the component arranged on Fo-eWLB 310 and semiconductor element or Fo-eWLB 310 And communication.
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come on the surface of sealant 328 332, half Insulating layer or passivation layer 334 are formed on the active surface 130 of conductor tube core 124, the conductive layer 316 of interconnecting unit 312.Insulating layer One of 334 other materials comprising SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar insulation and structural property or Multiple layers.A part of insulating layer 334 is removed by LDA, etching or other suitable processes to expose conductive layer 132 and conduction Layer 316.
Using such as spraying plating, electrolysis plating or electroless patterning and metal deposition process come the shape on insulating layer 334 At conductive layer or RDL 336.Conductive layer 336 can be Al, Cu, Sn, Ni, Au, Ag or one of other suitable conductive materials Or multiple layers.A part of conductive layer 336 is electrically connected to conductive layer 132.A part of conductive layer 336 is electrically connected to interconnection The part 316a of unit 312.A part of conductive layer 336 is electrically connected to the part 316b of conductive layer 316.Conductive layer 336 Other parts are electrically shared or are electrically isolating, this depends on the Design and Features of semiconductor element 124.Conductive layer 336 provide signal routing and power supply and grounding connection in Fo-eWLB 310.
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come in insulating layer 334 and conductive layer 336 Upper formation insulating layer or passivation layer 338.Insulating layer 338 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or has similar exhausted One or more layers of the other materials of edge and structural property.A part is removed by LDA, etching or other suitable processes Insulating layer 338 is to expose conductive layer 336.
Using evaporation, electrolysis plating, electroless plating, ball are fallen or screen printing process on conductive layer 336 deposits conductive stud Point material.Convex point material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, has and optionally helps weldering molten Liquid.For example, convex point material can be eutectic tin/lead, high kupper solder or lead-free solder.Come using suitable attachment or engaging process By convex point material engagement to conductive layer 336.In one embodiment, convex to make on the fusing point by heating the material to material Point material reflow is to form ball or salient point 340.In some applications, make second of salient point 340 reflux to improve and conductive layer 336 Electrical contact.In one embodiment, salient point 340 is formed on UBM layer.Salient point 340 also can be compressed engagement or hot compression It is joined to conductive layer 336.Salient point 340 indicates a type of interconnection structure that may be formed on conductive layer 336.Interconnection structure Bonding wire, conductive paste, stud bump, miniature salient point or other electrical interconnections can be used.
The conductive layer 316a of interconnecting unit 312 is electrically connected to salient point 340 to be used for and outside V via conductive layer 336SSOr VDDConnection.Each conductive layer 316a may be connected to VSSOr VDD。VSSIt may be connected to arbitrary conductive layer 316a.VDD It may be connected to arbitrary conductive layer 316a.It is connected to VSSThe ground connection that is formed in Fo-eWLB 310 of conductive layer 316a it is flat Face.It is connected to VDDConductive layer 316a formed Fo-eWLB 310 in power plane.By ground plane 316a and power plane 316a is electrically isolated.
It is disposed under insulating layer 334 by the ground plane that interconnecting unit 312 provides, and the letter with conductive layer 336 Number trace is electrically isolated.The electricity of conductive layer 336 is provided between semiconductor element 124 and the power plane provided by conductive layer 326a Source trace.(V can be attached in any part of semiconductor element 124 and power planeDDAny conductive layer 316a) it Between form power trace.The position of the position of discretionary interconnections unit 312, the position of power plane and power trace minimizes Trace length.
Semiconductor element 124 is electrically connected to salient point 340 to be used for and external device (ED) (for example, PCB) via conductive layer 336 Connection.Interconnecting unit 312 is embedded in the sealant 268 in the neighboring area of semiconductor element 124.Interconnecting unit 312 It is electrically connected to conductive layer 336 and provides signal, power supply and grounding connection to semiconductor element or be placed on Fo-eWLB 310 Component.Conductive layer 316a is electrically connected to salient point 340 to be used for and outside V via conductive layer 336SSOr VDDConnection.Conductive layer 316a forms the ground connection and power plane adjacent with semiconductor element 124.It is embedded in interconnecting unit 312 and ground connection and power plane is provided Without forming additional RDL on conductive layer 336.Less RDL is formed to increase package reliability and reduce Fo-eWLB 310 overall thickness.
Routing Design is increased by being disposed adjacently interconnecting unit 312 with semiconductor element 124 to form power plane In flexibility.Interconnecting unit 312 can be placed in from anywhere in needing power plane, and the power supply mark of conductive layer 336 Line may be coupled to any part of power plane, be attached to VDDAny conductive layer 316a.Increased spirit in routing Design Activity allows most short possible trace length.The trace length of reduction produces more effective PDN and increases Fo-eWLB 310 Speed and function.
It is disposed under insulating layer 334 by the ground plane that conductive layer 316a is provided, and the signal with conductive layer 336 Trace is electrically isolated.The signal traces of insulating layer 334 and conductive layer 336 are placed on ground plane and are promoted across Fo-eWLB The formation of 310 microstrip line.Microstrip line transmitting microwave frequency signal simultaneously allows microwave component (for example, antenna, coupler, filtering Device, power divider etc.) it is incorporated into Fo-eWLB 310.It forms ground plane and also adds the ESD in Fo-eWLB 310 Protection.
Insertion interconnecting unit 312 provides the additional conductive layer in Fo-eWLB 310.Additional conductive layer is used to form solution Coupling capacitor.It is formed by designing power supply network in a part of conductive layer 336 and conductive layer 316a on insulating layer 334 Decoupling capacitors.In one embodiment, the electric power network of semiconductor element 124, the i.e. portion of conductive layer 336 are supplied power to Point, it is designed to throughout ground plane portion 316a, so that electric power network, insulating layer 334 and ground plane 316a form decoupling Capacitor.Decoupling capacitors are integrated to the electricity for reducing voltage fluctuation in Fo-eWLB 310 and increasing Fo-eWLB 310 Performance.
Interconnecting unit 312 promotes Fo-eWLB 310 and semiconductor element or is placed between the component on Fo-eWLB 310 Telecommunication and signal routing.Opening 333b exposes the signal pad part 324b of conductive layer 324.Part 324b is electrically connected to The part 320b of the conductive layer 320 and part 316b of conductive layer 316.324b, 320b and 316b are designed in conductive layer for part 336 and semiconductor element or it is placed in route signal between the component on Fo-eWLB 310.Interconnecting unit 312 is also transistor Core or the component for being electrically coupled to Fo-eWLB 310 provide ground plane and connect with power plane.
Similar to the carrier 260 in Fig. 7 a, interconnecting unit 312 is to be mounted to the pre- of carrier using pickup and laying method The unit being initially formed.Before depositing sealant 328, interconnecting unit is disposed adjacently on carrier and with semiconductor element 124 312.Compared to needing complicated, height control, the formation of costly and time-consuming manufacturing step to add RDL, insertion is preformed mutually Even unit 312 be faster, less expensive and more low-risk.Ground connection and power plane are provided by insertion interconnecting unit 312 And the totle drilling cost that additional conductive layer reduces manufacturing time, increases handling capacity and reduce Fo-eWLB 310.Insertion is mutual Even element 312 increases the electric property and function of Fo-eWLB 310, without increasing package thickness.
Figure 10 a-10c illustrates the process to form modularization PCB unit.Figure 10 a shows a part of core substrate 350 Sectional view.Core substrate 350 includes with phenolic aldehyde cotton paper, epoxides, resin, establishment glass, obscured glass, polyester or other increasings The one or more of the polytetrafluoroethylene (PTFE) of strong fiber or fabric, prepreg (prepreg), FR-4, FR-1, CEM-1 or CEM-3 Layer.Alternatively, core substrate 350 includes one or more insulating layers or passivation layer.Core substrate 350 has opposite 352 He of surface 354。
It is served as a contrast using laser drill, machine drilling, deep reaction ion etching (DRIE) or other suitable procedures across core Bottom 350 forms multiple reach through holes.Reach through hole extends to surface 354 completely through core substrate 350 from surface 352.Using PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes come use Al, Cu, Sn, Ni, Au, Ag, Ti, W or its He fills reach through hole by suitable conductive material, to form the direction z vertical interconnecting structure or conductive through hole 356.Alternatively, it uses PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes to be formed on the side wall of reach through hole conductive Layer, and fill with the insulating packing material of the conductive material of such as Cu cream, or such as polymer pin the central part of reach through hole.
Using PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes come in core substrate 350 and vertical interconnecting structure 356 on formed conductive layer 358.Conductive layer 358 includes Al, Cu, Sn, Ni, Au, Ag or other are suitable Conductive material one or more layers.The part 358a operation of conductive layer 358 is engagement pad and is electrically connected to perpendicular interconnection Structure 356.Conductive layer 358 further includes part 358b.Part 358a and 358b can be shared electrically or be electrically isolating, This depends on the routing Design and function of semiconductor packages.
Using PVD, CVD, printing, spin coating, sprays, cuts painting, coil coating, lamination, sintering or thermal oxide come in core substrate 350 Insulating layer or passivation layer 360 are formed on surface 352 and conductive layer 358a-358b.Insulating layer 360 include SiO2, Si3N4, SiON, One or more layers of Ta2O5, Al2O3 or the other materials with similar insulation and structural property.In one embodiment, absolutely Edge layer 360 is solder mask.A part of insulating layer 360 is removed by LDA, etching or other suitable processes to form opening 366.Opening 366 exposes conductive layer 358.Opening 366a exposes the part 358a of conductive layer 358.Opening 366b, which is exposed, to be led The part 358b of electric layer 358.
Use PVD, CVD, electrolysis plating, electroless process or other suitable metal deposition processes, Lai Xin substrate Conductive layer 362 is formed on 350 surface 354.Conductive layer 362 includes Al, Cu, Sn, Ni, Au, Ag or other suitable conduction materials One or more layers of material.One part operation of conductive layer 362 is engagement pad and is electrically connected to vertical interconnecting structure 356. The other parts of conductive layer 362 are electrically shared or are electrically isolating, this depends on the Design and Features of semiconductor packages. Alternatively, core substrate 350 is passed through after forming conductive layer 358 and/or conductive layer 362 form vertical interconnecting structure 356.
Using PVD, CVD, printing, spin coating, sprays, cuts painting, coil coating, lamination, sintering or thermal oxide come in core substrate 350 Insulating layer or passivation layer 364 are formed on surface 354 and conductive layer 362.Insulating layer 364 include SiO2, Si3N4, SiON, Ta2O5, One or more layers of Al2O3 or the other materials with similar insulation and structural property.In one embodiment, insulating layer 364 be solder mask.A part of insulating layer 364 is removed by LDA, etching or other suitable processes to form opening 367 And exposure conductive layer 362.
Core substrate 350 constitutes one or more PCB unit with vertical interconnecting structure 356 and conductive layer 358 and 362 together. Figure 10 b shows tissue to the plan view of the core substrate 350 in PCB unit or column 368 and 370.PCB unit 368 and 370 includes Multirow vertical interconnecting structure 356 extends between the apparent surface of PCB unit.PCB unit 368 and 370 is configured for collecting At into stacking or stacked package (package-on-package, PoP) semiconductor devices.PCB unit 368 and 370 promotes heap Electrical interconnection between folded semiconductor devices.PCB unit 368 and 370 can be dimensionally different, this matches depending on resulting devices It sets.Although PCB unit 368 and 370 is illustrated as including rectangular or rectangular foot-print in figure 10b, alternatively, PCB unit 368 May include criss-cross (+) with 370, angled or " L-shaped ", it is circular, oval, hexagon, octagonal, The area of coverage of star-shaped or any geometric form.Figure 10 c, which is shown, is singly cut into each PCB using saw blade or laser cutting tool 372 The core substrate 350 of unit 368 and 370.
Related with Fig. 1, Figure 11 a-11h illustrates the process to form the Fo-eWLB including being embedded in PCB unit.Figure 11 a is shown Comprising for such as silicon of structural support, polymer, beryllium oxide, glass or other suitable low costs, rigid material it is sacrificial The sectional view of a part of the carrier or temporary substrates 380 of domestic animal base material.In one embodiment, carrier 380 is carrier band. Boundary layer or double-sided tape 382 are formed on carrier 380 as temporary adhesive junction film, etching stopping layer or hot releasing layer.
The PCB unit 368 and 370 from Figure 10 c is installed to boundary layer 382 with placement operation using picking up, wherein Conductive layer 358a-358b is positioned towards carrier 380.In one embodiment, conductive layer 358 and/or conductive layer 362 include electricity every From imaginary component.Imaginary component promotes the alignment of PCB unit 368 and 370, and reduces total pickup and standing time.Imaginary component is also Increase the planarization of insulating layer 360 and 364.Increased planarization improves PCB unit 368 and 370 at carrier 380 and interface Adhesiveness on layer 382.Imaginary component prevents PCB unit from shifting or fleeing from carrier 380.PCB unit 368 and 370 can compare It is pressed into boundary layer 382, so that insulating layer 360 is arranged in boundary layer.
The semiconductor element 124 from Fig. 2 d is installed to boundary layer 382 with placement operation using picking up, wherein effectively Surface 130 is positioned towards carrier.PCB unit 368 and 370 is placed in the neighboring area of semiconductor element 124.Alternatively, exist After installing semiconductor element 124, PCB unit 368 and 370 is placed on carrier 380.Figure 11 b, which is shown, to be arranged on carrier 380 Semiconductor element 124 and PCB unit 368 and 370 as the chip 384 for reconstructing or reconfiguring.In one embodiment, class The conductive layer 236 being similar in Fig. 5, forms ground plane layer on the surface of semiconductor element 124 130.
Figure 11 c shows the plan view of a part of reconstructed wafer 384.PCB unit 368 and 370 and semiconductor element 124 are installed on boundary layer 382.PCB unit 368 and 370 is placed in around semiconductor element 124 with interlocking pattern.Opening 367 expose multirow engagement pad 362.Engagement pad 362 is electrically connected to vertical interconnecting structure 356.Vertical interconnecting structure 356 exists Electrical interconnection is provided between the apparent surface 352 and 354 of PCB unit 368 and 370.Multiple saw streets 386 are relative to semiconductor element 124 and be aligned.Saw street 386 extends across PCB unit 368 and 370.When singly cutting reconstructed wafer 384 along saw street 386, Each semiconductor element 124 have be placed in around the neighboring area of semiconductor element 124 or among multiple vertical interconnecting structures 356 and multiple conductive layer 358b.Although PCB unit 368 and 370, which is illustrated to have, interlocks rectangular and rectangular foot-print, it is placed in PCB unit around semiconductor element 124 may include the PCB unit with such area of coverage, which has cross (+), angled or " L shape ", round or ellipse, hexagon, octagon, star or any other geometry.Alternatively, may be used PCB unit 368 and/or PCB unit 370 are disposed adjacently with the one, two or three side surface with semiconductor element 124. In one embodiment, PCB unit is individual unit or plate, and is arranged in the opening for passing through the formation of PCB unit or punching press Semiconductor element 124.According to the routing Design and function of semiconductor packages, it can be disposed adjacently and appoint with semiconductor element 124 What quantity and/or the PCB unit of configuration.
In Figure 11 d, using paste printing, it is compression molded, transfer molding, hydraulic seal molding, vacuum lamination, spin coating or Other suitable applicators to deposit sealant or mould on semiconductor element 124, PCB unit 368 and 370 and carrier 380 Produced compounds 388.Sealant 388 can be polymer composites, the epoxy resin such as with filler, the ring with filler Oxypropylene hydrochlorate or polymer with appropriate filler.Sealant 388 is non-conductive and protects semiconductor device in the environment Part is from external elements and pollutant effects.Sealant 388 also protects semiconductor element 124 from drawing by exposure to light The deterioration risen.Sealant 388 has opposite surface 390 and 392.The surface 392 of sealant 388 and semiconductor element 124 Active surface 130 is substantially coplanar.
In Figure 11 e, using dismembyator 394 in rear one for removing sealant 388 from surface 390 into grinding operation Point.Backward grinding operation removes sealant 388 from the surface of semiconductor element 124 128, and reduces reconstructed wafer 384 Thickness.Sealant 388 is retained on PCB unit 368 and 370.The surface 396 of sealant 388 and the surface of semiconductor element 124 128 is coplanar.In some embodiments, one of semiconductor element 124 is removed from rear surface 128 to during grinding operation rear Point, reconstructed wafer 384 is further thinned.
In Figure 11 f, multiple openings 398 are formed in the surface of sealant 388 396.Opening 398 includes vertical or inclination Side wall, and extend to from the surface of sealant 388 396 engagement pad 362 of perpendicular interconnection unit 368 and 370.Use laser 400 form opening 398 by LDA.Alternatively, opening 398 is formed by etching or other suitable processes.Be open 398 quilts It is configured to the memory device in semiconductor element 124 and being for example stacked on semiconductor element 124, passive device, sawtooth filtering 3D is provided between the semiconductor element or device of device, inductor, antenna etc. to be electrically interconnected.In one embodiment, will such as Cu have The surface coating (finish) that machine can weld preservative (OSP) is applied to exposed conductive layer to prevent Cu from aoxidizing.
In Figure 11 g, pass through chemical etching, mechanical stripping, CMP, mechanical lapping, hot baking, ultraviolet light, laser scanning or wet Formula strips to remove carrier 380 and boundary layer 382.Removal carrier 380 and boundary layer 382 expose the surface of sealant 388 392, the conductive layer 358a- of the active surface 130 of semiconductor element 124 and insulating layer 360 and PCB unit 368 and 370 358b。
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come on the surface of sealant 388 392, half Insulating layer or passivation layer 402 are formed on the active surface 130 and PCB unit 368 and 370 of conductor tube core 124.Insulating layer 402 wraps The one or more of other materials containing SiO2, Si3N4, SiON, Ta2O5, Al2O3 or with similar insulation and structural property Layer.A part of insulating layer 402 is removed by LDA, etching or other suitable processes to expose conductive layer 132 and conductive layer 358a-358b。
Using such as spraying plating, electrolysis plating or electroless patterning and metal deposition process come the shape on insulating layer 402 At conductive layer or RDL 404.Conductive layer 404 can be Al, Cu, Sn, Ni, Au, Ag or one of other suitable conductive materials Or multiple layers.A part of conductive layer 404 is electrically connected to conductive layer 132.A part of conductive layer 404 is electrically connected to PCB The conductive layer 358b of unit 368 and 370.A part of conductive layer 404 is electrically connected to the conductive layer of PCB unit 368 and 370 358a.The other parts of conductive layer 404 are electrically shared or are electrically isolating, this depends on setting for semiconductor element 124 Meter and function.Conductive layer 404 provides signal routing and power supply and grounding connection in semiconductor packages.
Using PVD, CVD, printing, lamination, spin coating, spraying, sintering or thermal oxide come in insulating layer 402 and conductive layer 404 Upper formation insulating layer or passivation layer 406.Insulating layer 406 includes SiO2, Si3N4, SiON, Ta2O5, Al2O3 or has similar exhausted One or more layers of the other materials of edge and structural property.In one embodiment, insulating layer 406 is solder mask.Pass through LDA, etching or other suitable processes remove a part of insulating layer 406 to expose conductive layer 404.
In Figure 11 h, it is electroplated using evaporation, electrolysis, electroless plating, ball are fallen or screen printing process comes on conductive layer 404 Deposit conductive salient point material.Convex point material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and a combination thereof, and having can Choosing helps weldering solution.For example, convex point material can be eutectic tin/lead, high kupper solder or lead-free solder.Using suitable attachment or Engaging process engages convex point material to conductive layer 404.In one embodiment, by heating the material to the fusing point of material On so that convex point material is flowed back to form ball or salient point 408.In some applications, make second of salient point 408 reflux to improve With the electrical contact of conductive layer 404.In one embodiment, salient point 408 is formed on UBM layer.Salient point 408, which also can be compressed, to be connect It closes or hot compression engagement is to conductive layer 404.Salient point 408 indicates a type of interconnection structure that may be formed on conductive layer 404. Bonding wire, conductive paste, stud bump, miniature salient point or other electrical interconnections can also be used in interconnection structure.
The conductive layer 358a of PCB unit 368 and 370 is electrically connected to salient point 408 to be used for and outside via conductive layer 404 VSSOr VDDConnection.Each conductive layer 358b may be connected to VSSOr VDD。VSSIt may be connected to arbitrary conductive layer 358b。VDDIt may be connected to arbitrary conductive layer 358b.It is connected to VSSConductive layer 358b formed ground plane.It is connected to VDDConductive layer 358b formed power plane.Ground plane 358b and power plane 358b is electrically isolated.
By PCB unit 368 and 370 provide ground plane be disposed under insulating layer 402, and with conductive layer 404 Signal traces be electrically isolated.The power trace of conductive layer 404 supplies function to semiconductor element 124 by connection power plane Rate.(V can be attached in any part of semiconductor element 124 and power planeDDAny conductive layer 358b) between shape At power trace.The position of the position of PCB unit 368 and 370, the position of power plane and power trace is selected to minimize Trace length.
It will via the saw street 386 of sealant 388 and PCB unit 368 and 370 using saw blade or laser cutting tool 409 Reconstructed wafer 384 is singly cut into each Fo-eWLB 410.Figure 12 shows the Fo-eWLB after singly cutting 410.Via conductive layer 404 Semiconductor element 124 is electrically connected to salient point 408 to be used for and the connection of external device (ED) (for example, PCB).368 He of PCB unit 370 are embedded into the sealant 388 in the neighboring area of semiconductor element 124.Via conductive layer 404 by semiconductor element 124 It is electrically connected to the conductive layer 358a-358b of PCB unit 368 and 370.Via conductive layer 404 by the conduction of PCB unit 368 and 370 Layer 358b is electrically connected to salient point 408 to be used for and external VSSOr VDDConnection.Conductive layer 358b is provided and semiconductor element 124 Adjacent ground connection and power plane.It is embedded in PCB unit 368 and 370 and forms ground connection and power plane without on conductive layer 404 Form additional RDL.Form the overall thickness that less RDL increases package reliability and reduces Fo-eWLB 410.
Routing is increased by being disposed adjacently PCB unit 368 and 370 with semiconductor element 124 to form power plane Flexibility in design.PCB unit 368 and 370 can be placed in from anywhere in needing power plane, and conductive layer 404 Power trace may be coupled to any part of power plane, be attached to VDDConductive layer 358b.Increase in routing Design Flexibility allow most short possible trace length.The trace length of reduction produces more effective PDN and increases Fo-eWLB 410 speed and function.
It is disposed under insulating layer 402 by the ground plane that conductive layer 358b is provided, and the signal with conductive layer 404 Trace is electrically isolated.The signal traces of insulating layer 402 and conductive layer 404 are placed on ground plane and are promoted across Fo-eWLB The formation of 410 microstrip line.Microstrip line transmitting microwave frequency signal simultaneously allows microwave component (for example, antenna, coupler, filtering Device, power divider etc.) it is incorporated into Fo-eWLB 410.It forms ground plane and also adds the ESD in Fo-eWLB 410 Protection.
The conductive layer 358b of PCB unit 368 and 370 provides the additional conductive layer in Fo-eWLB 410.Additional conductive layer It is used to form decoupling capacitors.By designing electricity in a part of conductive layer 404 and conductive layer 358b on insulating layer 402 Source network forms decoupling capacitors.In one embodiment, the electric power network for supplying power to semiconductor element 124, that is, lead The part of electric layer 404 is designed to throughout ground plane portion 358b, so that electric power network, insulating layer 402 and ground plane 358b forms decoupling capacitors.Decoupling capacitors, which are integrated to, to be reduced voltage fluctuation in Fo-eWLB 410 and increases Fo- The electric property of eWLB 410.
The electrical interconnection of component that PCB unit 368 and 370 promotes semiconductor element or is mounted on Fo-eWLB 410.It opens 398 exposure conductive layers 362 of mouth are to provide signal, ground connection and power supply for semiconductor element or the component being placed on Fo-eWLB 410 Interconnection.PCB unit 368 and 370 is modular prefabricated unit, be can be incorporated into various semiconductor packages.Using picking up It takes and PCB unit 368 and 370 is installed to carrier 380 with laying method.Compared to needing complicated, height control, costly and time-consuming Manufacturing step formation add RDL, form additional conductive layer and power supply and ground connection using prefabricated PCB unit 368 and 370 Plane be faster, less expensive and more low-risk.Insertion PCB unit 368 and 370 reduces manufacturing time, increases and handle up Measure and reduce the totle drilling cost of Fo-eWLB 410.Insertion PCB unit 368 and 370 increases the electric property of Fo-eWLB 410 And function, without increasing package thickness.
Although one or more embodiments of the invention is described in detail, those skilled in the art will be managed Solution, in the case where not departing from the scope of the present invention as illustrated in following following claims, can make those embodiments Modification and adjustment.

Claims (14)

1. a kind of method for making semiconductor devices, comprising:
Semiconductor element is provided；
The first ground plane is disposed adjacently with the semiconductor element；
Sealant is deposited on first ground plane and semiconductor element；And
Conductive layer is formed above first ground plane, semiconductor element and sealant, wherein the conductive layer includes, from First ground plane is electrically coupled to the conductive trace of reference circuits node, and directly in first ground plane The signal traces of upper formation.
2. method of claim 1 further comprises forming power net in the conductive layer on first ground plane Network.
3. method of claim 1 further comprises:
Insulating layer is formed on first ground plane and semiconductor element；And
Form the decoupling capacitors including first ground plane, insulating layer and conductive layer.
4. method of claim 1 further comprises:
Empty tube core is provided；And
First ground plane is formed on the empty tube core.
5. method of claim 1 further comprises forming the second ground plane on the surface of the semiconductor element.
6. a kind of method for making semiconductor devices, comprising:
Conductive plane is provided；
The conductive plane is arranged on carrier；
Semiconductor element is disposed adjacently with the conductive plane on the carrier；
Sealant is deposited on the first surface of semiconductor element and conductive plane；
It moves back in deposition sealant except the carrier；And
Conductive layer is formed on the conductive plane, semiconductor element and sealant, wherein the conductive layer includes: directly to exist Extend above the second surface of the conductive plane opposite with the first surface of the conductive plane and is electrically connected to institute The first conductive trace of semiconductor element is stated, and is separated with first conductive trace and is coupled to the conductive plane Second conductive trace of reference circuits node.
7. method for claim 6 further comprises: providing the substrate including the conductive plane and formed across the substrate Multiple vertical interconnecting structures.
8. method for claim 6 further comprises:
Insulating layer is formed on the conductive plane and the semiconductor element；And
It is formed on the insulating layer microstrip line.
9. method for claim 6, wherein providing the conductive plane as patterned lead frame, patterned copper foil, packet Include the band of the resin coating of patterned copper or a part of the prepreg including patterned copper.
10. a kind of semiconductor devices, comprising:
Semiconductor element；
The ground plane being adjacently positioned with the semiconductor element；
The sealant being deposited on the first surface of the ground plane；And
The conductive layer being formed in above the second surface of the ground plane opposite with the first surface of the ground plane, and And the conductive layer includes: the first conductive mark for being electrically connected to the semiconductor element and extending above the ground plane Line；And it is formed in the second conductive trace above the ground plane.
11. the semiconductor devices of claim 10 further comprises substrate, the substrate includes adjacent with the semiconductor element The multiple vertical interconnecting structures for passing through the substrate and being formed of arrangement.
12. the semiconductor devices of claim 11, wherein the ground plane is formed over the substrate.
13. the semiconductor devices of claim 10 further comprises the empty tube core being adjacently positioned with the semiconductor element, wherein The ground plane is formed on the empty tube core.
14. the semiconductor devices of claim 10, further comprises:
The insulating layer arranged between the ground plane and conductive layer；And
Decoupling capacitors including the ground plane, insulating layer and the part conductive layer.
CN201410085270.7A 2013-03-08 2014-03-10 Form the semiconductor devices and method for the insertion conductive layer of power ground plane in FO-EWLB Active CN104037124B (en)

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