CN104037122A - Multi-layer Metal Contacts - Google Patents
Multi-layer Metal Contacts Download PDFInfo
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- CN104037122A CN104037122A CN201310451248.5A CN201310451248A CN104037122A CN 104037122 A CN104037122 A CN 104037122A CN 201310451248 A CN201310451248 A CN 201310451248A CN 104037122 A CN104037122 A CN 104037122A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method for forming metal contacts within a semiconductor device is provided. The method includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, wherein the first-layer contact extends to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.
Description
The cross reference of related application
The application requires the U.S. Patent application the 61/775th of submitting on March 10th, 2013, the priority of No. 642, and its content is hereby expressly incorporated by reference.
Technical field
The application relates generally to semiconductor applications, more specifically, relates to multiple layer metal contact.
Background technology
Semiconductor integrated circuit can comprise containing transistorized various parts.Metal wire and the contact of the mode link that this class circuit also can comprise expecting, to form functionalization, interconnection and integrated circuit.The manufacture of this class circuit for example, realizes by form lamination (starting from semiconductor crystal wafer) in Semiconductor substrate conventionally.
For example, can be in Semiconductor substrate and middle formation transistor to comprise doped source and the drain electrode structure in grid structure and the substrate on substrate.Then, cover by interlayer dielectric layer and around structure.Form hole through interlayer dielectric layer and extend downward grid structure and impure source and drain electrode structure.Then, use electric conducting material to fill these holes to form the required cross tie part (also referred to as contact or through hole) connecting for one or more other circuit blocks.
The hole that the use electric conducting material forming is filled does not generate straight cylindrical hole.Contrary, darker along with its extension, it is narrower that hole becomes.Because grid and doped region are positioned at different height, can be of different sizes for the hole of doped region with for the hole of grid.Particularly, owing to extending to the Kong Yueshen of doped region, it can be wider on top compared with extending to the hole of gate electrode.
On patterning, design has impact to the difference of hole dimension.Particularly, the critical dimension (relevant with the amount of space of allowing between hole) that extends to the hole of doped region is different from the critical dimension in the hole that extends to grid.Expect that thereby reducing this difference allows better alignment budget (overlay budget) and critical dimension control.
Summary of the invention
For addressing the above problem, the present invention relates to a kind of for form the method for metal contact element in semiconductor device, the method comprises: in the first dielectric layer around gate electrode, form ground floor contact, ground floor contact extends to the impure source/drain region of base substrate; Above the first dielectric layer, form the second dielectric layer; Form the second layer contact that extends to ground floor contact through the second dielectric layer.
The method further comprises: form the second layer contact that extends to the gate electrode in the first dielectric layer through the second dielectric layer.
The method further comprises: form the contact that extends to gate electrode and first layer metal contact through the second dielectric layer.
Wherein, form second layer contact, between ground floor contact and second layer contact, form step.
Wherein, the critical dimension of ground floor contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode comprises high-k/metal gate electrode.
The method further comprises: form second layer contact, second layer contact extends through the second dielectric layer and hard mask layer, hard mask layer around gate electrode to be connected with gate electrode.
Wherein, hard mask layer has selectivity with respect to the first dielectric layer and comes for etching object.
In addition, also provide a kind of semiconductor device, having comprised: substrate, has comprised doped region; The first dielectric layer, around at least one gate electrode being formed on substrate, the first dielectric layer comprises the ground floor contact that extends to doped region; The second dielectric layer, is formed on the first dielectric layer top, and the second dielectric layer comprises the second layer contact that extends to ground floor contact through the second dielectric layer.
This device further comprises the second layer contact that extends to the gate electrode in the first dielectric layer through the second dielectric layer.
This device further comprises: step, and between ground floor contact and second layer contact.
Wherein, the critical dimension of ground floor contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode comprises high-k/metal gate electrode.
Wherein, use hard mask layer covering grid electrode.
This device further comprises the second layer contact that extends to the gate electrode in the first dielectric layer through the second dielectric layer and hard mask layer.
Wherein, hard mask layer has selectivity with respect to the first dielectric layer and comes for etching object.
In addition, also provide a kind of for form the method for metal contact element in semiconductor device, the method comprises: on substrate, deposit gate electrode; Doped region is adulterated to form in region to contiguous gate electrode in substrate; Above gate electrode, deposit the first dielectric layer; In the first dielectric layer, form ground floor contact; Above the first dielectric layer, form the second dielectric layer; Form the second layer contact that extends to ground floor contact through the second dielectric layer, make to there is step between ground floor contact and second layer contact.
The method further comprises: form the second layer contact that extends to the gate electrode in the first dielectric layer through the second dielectric layer.
Wherein, the critical dimension of ground floor contact is substantially similar to the critical dimension of second layer contact.
Wherein, gate electrode comprises high-k/metal gate electrode.
Brief description of the drawings
According to specific descriptions below in conjunction with the each side that the present invention may be better understood with reference to accompanying drawing.Should emphasize, according to the standard practices in industry, all parts is not drawn to scale.In fact,, in order clearly to discuss, the size of all parts can at random increase or reduce.
Figure 1A to Fig. 1 E be according to shown in principle described herein example for form the diagram of illustrative processes of metal contact element in semiconductor device.
Fig. 2 A to Fig. 2 B is according to the diagram of the example semiconductor device with multilayer contact shown in principle described herein example.
Fig. 3 be according to shown in principle described herein example for form the flow chart of illustrative methods of multiple layer metal contact in semiconductor device.
Embodiment
Should be appreciated that, it is many for implementing different embodiment or the example of disclosed different characteristic that following discloses content provides.The instantiation of parts and configuration is below described to simplify the present invention.Certainly, this is only example, is not limited to the present invention.And, in the following description, implement to implement before the second technique the first technique can be included in the first technique after the direct embodiment of enforcement the second technique, also can comprise the embodiment that can implement extra technique between the first technique and the second technique.In order to simplify and object clearly, all parts can be drawn arbitrarily in varing proportions.In addition, in the following description, first component be formed on second component top or on can comprise the embodiment that the first component of formation directly contacts with second component, and also can be included between first component and second component and can form extra parts, thereby the embodiment that first component can directly not contacted with second component.
And, for convenience of description, such as " in ... below ", " ... under ", " bottom ", " ... on ", the relative space position term such as " top " can be for describing the relation of element as shown in the figure or parts and another (or other) element or parts.Should be appreciated that, the orientation of describing in figure, these relative space position terms are intended to comprise the different azimuth of device in using or operating.For example, if the device of upset in accompanying drawing, be described as other elements or parts " under " or the element of " below " will be oriented in other elements or parts " on ".Therefore, exemplary term " ... under " can be included in top and below two kinds of orientation.Device can be orientated other directions (90-degree rotation or in other orientation), and correspondingly in herein interpreted for the descriptor of relative space position.
Figure 1A to Fig. 1 E shows the diagram of the illustrative processes for form metal contact element in semiconductor device.The every width of Figure 1A to Fig. 1 E shows three different views of the identity unit of instantiation in technique.In every width diagram, left-hand line 102 shows along the first (x) sectional view of direction, and middle column 104 shows vertical view, and right-hand column 106 shows along the sectional view of second (y) direction.
Figure 1A shows the formation around the first dielectric layer 108 of multiple gate electrodes 112.Gate electrode 112 is formed on the top of substrate 101.In addition, hard mask layer 110 is formed on gate electrode 112 tops.Substrate 101 comprises the doped region of contiguous gate electrode 112, for simplified characterization, and not shown this type of region herein.
According to some illustrative examples, substrate 101 can also comprise Silicon Wafer.Alternatively or additionally, substrate 101 can comprise another elemental semiconductor such as germanium; Comprise the compound semiconductor of carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; Or comprise the alloy semiconductor of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP.In another optional embodiment, substrate 101 also can comprise dielectric layer, conductive layer or their combination.
According to some illustrative examples, the first dielectric layer 108 can be greater than 3.9 non-low k dielectric by k value and form, for example silica (SiO2), silicon nitride (SiN) or silicon oxynitride (SiON).In an embodiment, the first dielectric layer 108 is formed by the oxide of such as non-doped silicate glasses (USG), boron-doping silicon silicate glass (BSG), phosphorous doped silicon silicate glass (PSG), boron Doping Phosphorus silicate glass (BPSG) etc.The first dielectric layer 108 also can be formed by the silicon nitride layer on silicon oxide layer and silicon oxide layer.Alternatively, the first dielectric layer 108 can be less than 3.9 low k dielectric by k value and form, for example carbon doped silicon oxide of fluorine doped silicon oxide, carbon doped silicon oxide, porous silica, porous, organic polymer or silicon resin base polymer.In these embodiments, can use chemical vapor deposition (CVD) or physical vapor deposition (PVD) technique to form the first dielectric layer 108.
According to some illustrative examples, gate electrode 112 can be high-k/metal gate.Some grids are made up of the material such as polysilicon, and other grids can be made of metal.This type of metal gates comprises the high-k dielectric material between grid and substrate.For forming this type of grid, need on substrate, form dummy grid.Forming after hard mask layer around dummy grid, can remove dummy grid, and high-k dielectric material and metal material can be filled in the space staying by removal dummy grid.
Figure 1A also shows the first dielectric layer after the flatening process 111 such as chemico-mechanical polishing (CMP) technique uses.Flatening process 111 can be removed unnecessary dielectric material to expose the top of the hard mask material 110 forming above grid 112.
According to this example, gate electrode 112 is fin-shapeds.Concrete, it is formed as the shape of extending.Can find out by overlooking Figure 104, the hard mask material 110 around gate electrode 112 exposing extends in two parallel lines modes, and each is corresponding to a gate electrode 112.In y direction diagram 106, in this concrete sectional view, only show dielectric layer 108.In x direction diagram 102, show two gate electrodes 112 and around hard mask material 110.
Figure 1B shows on the first dielectric layer 108 tops and forms etching stopping layer 114, forms interim dielectric layer 116 on etching stopping layer 114 tops, and forms photoresist material 118 on interim dielectric layer 116 tops.Etching stopping layer 114 is connected to gate electrode 112 in substrate 101 or the metal contact element of doped region for helping to form at etch process.According to some illustrative examples, etching stopping layer 114 can comprise silicon nitride or silicon oxynitride.
According to some illustrative examples, photoresist material 118 can be positive shaped material or minus material.Photoresist material 118 for by ground floor contact patterning in the first dielectric layer 108.By photoetching process patterning the first dielectric layer 108.The treatment step of exemplary light carving technology can comprise coating photoresist 118, soft baking, mask alignment, exposure, postexposure bake, development photoresist and baking firmly.Photoetching process can be applied KrF (KrF) excimer laser, argon fluoride (ArF) excimer laser, ArF liquid immersion lithography, extreme ultraviolet line (EUV) or electron beam and write (e-beam).Photolithographic exposure technique also can be implemented or substitute by writing such as maskless lithography, ion beam with other suitable methods of molecule impression.In the time that the photoresist layer 118 of exposure is applied to developing solution, the photoresist region (for eurymeric photoresist) of exposure sacrifice layer below is also partly or entirely removed.
In this example, ground floor contact is perpendicular to fin-shaped gate electrode 112.
Fig. 1 C shows etch process and removes the device after photoresist material 118.Etch process affects the region that photoresist material 118 exposes.Particularly, hole 113 is etched down to hard mask layer 110.Therefore, the material of formation hard mask layer 110 has with respect to the etched selectivity of material that forms dielectric layer 108,116.
Because hole 113 is perpendicular to gate electrode 112, therefore can not in the diagram of x direction 102, observe hole 113.But, in vertical view, can observe hole 113 and expose hard mask layer 110.Particularly, etch process is etched down to the hard mask material 110 around gate electrode 112, and the hard mask material 110 depositing along substrate 101.Y direction diagram 106 shows and extends downward the hole 113 of gate electrode 112 and the hard mask layer 110 along substrate 101.Due to the etch process of standard, hole 113 can be not vertically downward.On the contrary, the extension of hole 113Yue Xiang depths becomes narrower.
Fig. 1 D shows and is using metal material filler opening to form the CMP technique 122 after metal contact element 120.Metal contact element can comprise the various materials that comprise barrier layer and crystal seed layer.For example, metal contact element 120 can comprise titanium nitride (TiN), tantalum nitride (TaN) or platinum (Pt).In addition, metal contact element can comprise the various packing materials such as tungsten, copper, aluminium or their combination.Can pass through ald (ALD), physical vapor deposition (PVD or sputter) or optionally other suitable techniques form metal contact elements 120.
According to this example, CMP technique 122 is ground device downwards until expose the hard mask layer 110 on gate electrode 112 tops.This grinding has been removed interim dielectric layer 116, etching stopping layer 114 and has been positioned at any metal material of gate electrode 112 tops.The desired region of this grinding in semiconductor device retains first layer metal contact 120.
Can not observe metal contact element 120 from x direction diagram 102.From overlooking Figure 104, can observe the metal contact element between gate electrode 112.Also can from y direction diagram 106, observe metal contact element 120.
Fig. 1 E shows at the interior formation second layer of the second dielectric layer 124 contact 126,128,130 being formed at above the first dielectric layer 108.Second layer metal contact can comprise the similar or different material of first layer metal contact above discussed from those.According to this example, second layer metal contact 126 is only formed on first layer metal contact top.Therefore, first layer metal contact 120 and second layer metal contact be combined to form the complete contact that extends downward substrate doped region.This metalloid contact 126 can be for being connected to transistorized source electrode or drain terminal.
According to this example, form and be passed down through the second layer metal contact 128 of the second dielectric layer 124 to gate electrode 112.Contact extends through hard mask layer 110 to contact actual grid 112.Placing this contact can not contact with any first layer metal contact 120 it.This can cause the short circuit between grid and doped region.
In addition, second layer metal contact 130 is formed on gate electrode 112 and first layer metal contact 120 tops.In some circuit, expect to form the cross tie part between transistorized source terminal or drain electrode end and transistorized grid.As shown here, can use second layer metal contact 130 effectively to form this cross tie part.
X direction diagram 120 shows each in second layer metal contact 126,128,130.Darker due to what in sectional view, they arranged, so contact is shown in broken lines.Vertical view also shows each in second layer metal contact 126,128,130.Y direction diagram shows and only extends to the second layer metal contact 128 of gate electrode 112 and extend to the second layer metal contact 130 of gate electrode 112 and first layer metal contact 120.
Can form each in second layer metal contact 126,128,130 by standard photolithography process.For example, photoresist material can be for patterning the second dielectric layer 124.At photoresist layer by exposing through the light source of photomask and after photoresist layer develops, can forming hole in the location of removing photoresist layer.Then, can use metal material to fill these holes to form second layer metal contact 126,128,130.
Fig. 2 A and Fig. 2 B show the diagram of the example semiconductor device with multilayer contact.Fig. 2 A shows the multiple layer metal contact of implementing principle described herein.On the contrary, Fig. 2 B shows the conventional method that forms the metal contact element of differing heights in identical technique.
Fig. 2 A shows the doped region 204 being formed in substrate 202.The contiguous gate electrode 208 of doped region 204 is to form complete transistor.With the structural similarity shown in Figure 1A to Fig. 1 E, hard mask material 210 is around grid 208.In addition, the first dielectric layer 212 is around gate electrode.First layer metal contact 204 is formed in the first dielectric layer 212.First layer metal contact extends downward doped region 204.
The second dielectric layer 214 is formed on the top of the first dielectric layer 212.Second layer metal contact 216,218 is formed in the second dielectric layer 214.A second layer contact 216 extends downward gate electrode 208.Another second layer contact 218 extends downward first layer metal contact 206.
In this example, use identical Patternized technique to form second layer metal contact 216,218.In addition,, because the second layer metal contact 218 that is connected to doped region 204 needn't extend downward doped region 204 always, therefore can being fabricated to, it retains small size at top.Can allow so better alignment budget.Particularly, because the hole that extends downward doped region 204 needn't be wider at top, can form parts closely so implement the patterning of the device of principle herein.
Extend downward the complete contact of doped region 204 owing to using two techniques of separating to form, so form step 224 between ground floor contact 206 and second layer contact 218.But this step does not have substantial effect on the electrical interconnection between ground floor contact 206 and second layer contact 218.
Fig. 2 B shows with the contact that is connected to gate electrode 208 and uses the formation of same process to be connected to the conventional method of the contact of doped region.Owing to there is no first layer metal contact above doped region, and because the extension of Kong Yuexiang depths becomes narrower, so the second layer contact 220 of single technique has wider hole on top.Due to contact 220 than and the contact 216 that is connected to gate electrode 208 extend darker, so hole is wider on top.If contact 216,220 place each other enough closely; can form electrical connection, this may cause short circuit 222.
In other words,, due to the degree of depth of contact 220, the critical dimension at contact 220 tops is different from the critical dimension of contact 220 bottoms substantially.But in Fig. 2 A, the critical dimension at metal contact element 218 tops is substantially similar to the critical dimension at ground floor contact top.
Fig. 3 shows the flow chart of the illustrative methods for form multiple layer metal contact in semiconductor device.According to this example, the method comprising the steps of 302, in the first dielectric layer around at least one gate electrode, forms ground floor contact, and ground floor contact extends to the doped region at the bottom of back lining.The method further comprises step 304, forms the second dielectric layer above the first dielectric layer.The method further comprises step 306, forms the second layer contact that extends to ground floor contact through the second dielectric layer.
According to some illustrative examples, a kind of method that forms metal contact element in semiconductor device is included in the first dielectric layer of at least one gate electrode and forms ground floor contact, ground floor contact extends to the doped region at the bottom of back lining, above the first dielectric layer, form the second dielectric layer, and form the second layer contact that extends to ground floor contact through the second dielectric layer.
According to some illustrative examples, semiconductor device comprises the substrate with doped region, the first dielectric layer of the gate electrode forming on substrate around at least one, the first dielectric layer comprises the ground floor contact that extends to doped region, and above the first dielectric layer, form the second dielectric layer, the second dielectric layer comprises the second layer contact that extends to ground floor contact through the second dielectric layer.
A kind of method that forms metal contact element in semiconductor device is included in and on substrate, forms gate electrode, in substrate, the position of contiguous gate electrode forms doped region, above gate electrode, form the first dielectric layer, in the first dielectric layer, form ground floor contact, above the first dielectric layer, form the second dielectric layer, and form extend through the second layer contact of the second dielectric layer to ground floor contact, make to there is step between ground floor contact and second layer contact.
Should be appreciated that, the various combination of listed embodiment and step herein can be with different using in order or parallel use, and there is no special step be crucial or necessary.In addition,, although use term " electrode " herein, should be realized that this term comprises the concept of " electrode contact part ".In addition, the parts of describing and discussing in conjunction with some embodiment herein can be combined the parts that other embodiment described and discussed herein and combine.Therefore, all these type of embodiment include within the scope of the invention.
The parts of multiple embodiment are discussed above, it will be understood by those skilled in the art that can design or revise as basis with the present invention easily other for carry out with herein the identical object of the embodiment that introduces and/or realize processing and the structure of same advantage.Those of ordinary skill in the art should also be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and in the situation that not deviating from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.
Claims (10)
1. for form a method for metal contact element in semiconductor device, described method comprises:
In the first dielectric layer around gate electrode, form ground floor contact, described ground floor contact extends to the impure source/drain region of base substrate;
Above described the first dielectric layer, form the second dielectric layer;
Form the second layer contact that extends to described ground floor contact through described the second dielectric layer.
2. method according to claim 1, further comprises: form the second layer contact that extends to the described gate electrode in described the first dielectric layer through described the second dielectric layer.
3. method according to claim 1, further comprises: form the contact that extends to described gate electrode and described first layer metal contact through described the second dielectric layer.
4. method according to claim 1, wherein, forms described second layer contact, between described ground floor contact and described second layer contact, forms step.
5. method according to claim 1, wherein, the critical dimension of described ground floor contact is substantially similar to the critical dimension of described second layer contact.
6. method according to claim 1, wherein, described gate electrode comprises high-k/metal gate electrode.
7. method according to claim 1, further comprises: form second layer contact, described second layer contact extends through described the second dielectric layer and hard mask layer, described hard mask layer around described gate electrode to be connected with described gate electrode.
8. method according to claim 6, wherein, described hard mask layer has selectivity with respect to described the first dielectric layer to be come for etching object.
9. a semiconductor device, comprising:
Substrate, comprises doped region;
The first dielectric layer, around at least one gate electrode being formed on described substrate, described the first dielectric layer comprises the ground floor contact that extends to described doped region;
The second dielectric layer, is formed on described the first dielectric layer top, and described the second dielectric layer comprises the second layer contact that extends to described ground floor contact through described the second dielectric layer.
10. for form a method for metal contact element in semiconductor device, described method comprises:
On substrate, deposit gate electrode;
Doped region is adulterated to form in region to contiguous described gate electrode in described substrate;
Above described gate electrode, deposit the first dielectric layer;
In described the first dielectric layer, form ground floor contact;
Above described the first dielectric layer, form the second dielectric layer;
Form the second layer contact that extends to described ground floor contact through described the second dielectric layer, make to there is step between described ground floor contact and described second layer contact.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361775642P | 2013-03-10 | 2013-03-10 | |
| US61/775,642 | 2013-03-10 | ||
| US13/911,183 US9337083B2 (en) | 2013-03-10 | 2013-06-06 | Multi-layer metal contacts |
| US13/911,183 | 2013-06-06 |
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| CN104037122A true CN104037122A (en) | 2014-09-10 |
| CN104037122B CN104037122B (en) | 2017-08-15 |
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| CN104037122B (en) | 2017-08-15 |
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