CN104037121A - 通过镶嵌工艺形成气隙 - Google Patents
通过镶嵌工艺形成气隙 Download PDFInfo
- Publication number
- CN104037121A CN104037121A CN201310224578.0A CN201310224578A CN104037121A CN 104037121 A CN104037121 A CN 104037121A CN 201310224578 A CN201310224578 A CN 201310224578A CN 104037121 A CN104037121 A CN 104037121A
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- Prior art keywords
- layer
- energy
- dielectric layer
- film
- conductive coating
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- 238000005516 engineering process Methods 0.000 description 15
- 238000000151 deposition Methods 0.000 description 13
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
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- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
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Classifications
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Abstract
本发明提供了一种形成半导体器件的方法,其中通过镶嵌工艺形成气隙。该方法包括:在衬底上的第一介电层中形成第一导电层结构;形成具有多个部分的图案化光刻胶层,每一部分都位于对应的一个第一导电层结构上方;在每一部分的侧壁上形成能量可去除膜(ERF);在ERF、图案化光刻胶层的部分和第一介电层的上方形成第二介电层;去除多个部分以留下多个开口;将导电材料填充在开口中,导电材料限定第二导电层结构;在第二导电层结构、ERF和第二介电层的上方形成顶面层;以及将能量施加于ERF,以部分地去除部分侧壁上的ERF,从而形成气隙。
Description
技术领域
本发明总的来说涉及半导体器件,更具体地,涉及通过镶嵌工艺形成气隙。
背景技术
在半导体技术中,根据通常表示最小部件尺寸的特定技术节点可在半导体衬底上形成集成电路。当最小部件尺寸变至约100nm或以下时,通常使用镶嵌工艺来形成包括垂直互连通孔以及水平互连金属线的多层铜互连。在这种镶嵌工艺中,通常期望使用低介电常数(低k)材料来形成层间介电层。形成这种低k介电材料的一种方法是在材料中提供气隙。然而,一种担心是气隙可能在大间距区域中坍塌,从而引起集成电路的性能和质量问题。因此,需要气隙坍塌减少且性能提高的结构其及制造方法。
发明内容
根据本发明的一个方面,提供了一种制造半导体器件的方法,包括:提供衬底;在衬底上形成图案化第一介电层,图案化第一介电层具有多个第一开口;将第一导电材料填充在多个第一开口中,第一导电材料限定第一导电层结构;在第一介电层和第一导电层结构的上方形成掩模层,掩模层包括多个部分,每一部分均位于对应的一个第一导电层结构的上方,并且掩模层的每一部分的宽度均大于对应的一个第一导电层结构的宽度;在掩模层的每一部分的对应侧壁上形成能量可去除膜(ERF);在能量可去除膜、掩模层的多个部分和第一介电层的上方形成第二介电层;去除掩模层的多个部分以留下多个第二开口;将第二导电材料填充在多个第二开口中,第二导电材料限定第二导电层结构;在第二导电层结构、能量可去除膜和第二介电层上形成顶面层;以及将能量施加于衬底,以至少部分地去除能量可去除膜并形成气隙。
优选地,该方法还包括:在将第一导电材料填充在多个第一开口中之前,在图案化第一介电层上和第一开口内形成阻挡层。
优选地,该方法还包括:在将第一导电材料填充在多个第一开口中的步骤之后,平坦化第一导电材料,使得第一导电材料的顶部与第一介电层的顶部共面。
优选地,掩模层是图案化光刻胶层。
优选地,图案化光刻胶层包括底部抗反射涂覆(BARC)层。
优选地,形成能量可去除膜包括:形成选自由光子分解材料、热分解材料、电子束分解材料和它们的组合所组成的组中的材料。
优选地,形成顶面层包括:形成选自由蚀刻终止层、低k介电材料层和它们的组合所组成的组中的材料层。
优选地,形成顶面层包括形成多孔材料层。
优选地,形成顶面层包括:形成介电常数范围在约2.5至约4之间的多孔氮化硅层或碳化硅层。
优选地,对衬底施加能量包括:使用从基本由热能、X射线、紫外(UV)线、红外线和它们的组合所组成的组中选择的一种能量。
优选地,施加于衬底的能量是温度范围在约100摄氏度至约600摄氏度之间且持续时间从约1分钟至约20分钟的热能。
优选地,在将能量施加于衬底之后,第二介电层包括孔隙率范围在约0.5%至约80%之间的多孔结构。
根据本发明的另一方面,提供了一种形成镶嵌层的方法,包括:在半导体衬底上的第一介电层中形成多个第一导电层结构;形成图案化光刻胶层,图案化光刻胶层具有多个部分,每一部分都位于对应的一个第一导电层结构的上方,并且图案化光刻胶层的每一部分的宽度均大于对应的一个第一导电层结构的宽度;在第一介电层上以及图案化光刻胶层的多个部分的顶部和侧壁上形成能量可去除膜(ERF);蚀刻能量可去除膜,仅保留图案化光刻胶层的每一部分的侧壁上的能量可去除膜;在能量可去除膜、图案化光刻胶层的多个部分和第一介电层的上方形成第二介电层;去除图案化光刻胶层的部分,以留下多个开口;将导电材料填充在多个开口中,导电材料限定第二导电层结构;在第二导电层结构、能量可去除膜和第二介电层的上方形成顶面层;以及将能量施加于衬底,以至少部分地去除光刻胶层的部分的侧壁上的能量可去除膜,从而形成气隙。
优选地,该方法还包括:在第一导电层结构和第一介电层之间形成阻挡层。
优选地,形成能量可去除膜包括形成选自由光子分解材料、热分解材料、电子束分解材料和它们的组合所组成的组中的材料。
优选地,将能量施加于衬底包括使用从由热能、X射线、紫外(UV)线、红外线和它们的组合所组成的组中选择的一种能量。
优选地,在将能量施加于衬底之后,第二介电层包括孔隙率范围在约0.5%至约80%之间的多孔结构。
根据本发明的又一方面,提供了一种半导体器件,包括:多个第一金属层结构,位于半导体衬底上的第一介电层中;多个第二金属层结构,位于第二介电层中,多个第二金属层结构的每一个结构都位于多个第一金属层结构中的对应一个结构的上方,并且第二金属层结构中的每一个结构的宽度均大于对应的一个第一金属层结构的宽度;能量可去除膜,设置在第二金属层结构各自的侧壁上;气隙,设置在第二金属层结构的侧壁上的能量可去除膜和第二介电层之间;以及顶面层,形成在第二金属层结构、能量可去除膜和第二介电层的上方。
优选地,顶面层包括多孔结构。
优选地,第二介电层包括孔隙率范围在约0.5%至80%之间的多孔结构。
附图说明
阅读以下详细描述时结合附图来理解本发明的实施例。需要强调的是,根据工业标准实践,各个部件没有按比例绘制。事实上,为了清楚地讨论,可以任意地增大或减小各个部件的尺寸。
图1是根据本发明各个实施例的制造半导体器件的方法的流程图;以及
图2至图12是根据本发明各个实施例的处于各个制造阶段的部分半导体器件的示意性截面图。
具体实施方式
在以下描述中,描述了具体细节以对本发明的实施例提供全面的理解。然而,掌握本领域常规技术的技术人员应该理解,在没有这些具体细节的情况下可实施本发明的实施例。在一些情况下,没有详细描述已知的结构和工艺从而避免本发明的实施例产生不必要的模糊。
在本说明书中涉及的“一个实施例”或“实施例”意味着与实施例相关的所述特定部件、结构或特性至少被包括在本发明的一个实施例中。因此,本说明书中各处出现的短语“在一个实施例中”或“在实施例中”不一定都指相同的实施例。此外,在一个或多个实施例中可按照任何适合的方式组合特定部件、结构或特性。应该理解,以下附图没有按比例绘制;相反,这些附图意在说明。
图1是根据本发明各个方面的制造半导体器件的方法2的流程图。参照图1,方法2包括框4,其中提供衬底。方法2包括框6,其中,在衬底上形成图案化的第一介电层。图案化的第一介电层具有多个第一开口。方法2包括框8,其中,将第一导电材料填充在多个第一开口中,第一导电材料限定第一导电层结构。方法2包括框10,其中,在第一介电层和第一导电层结构的上方形成掩模层。掩模层包括多个部分,每一部分均位于第一导电层结构中对应结构的上方。每一部分的宽度均大于对应一个第一导电层结构的宽度。方法2包括框12,其中,在掩模层每一部分的侧壁上形成能量可去除膜(ERF)。方法2包括框14,其中,在能量可去除膜、部分掩模、和第一介电层的上方形成第二介电层。方法2包括框16,其中,去除部分掩模层以留下多个第二开口。方法2包括框18,其中,将第二导电材料填充在多个第二开口中,第二导电材料限定第二导电层结构。方法2继续至框20,其中,在第二导电层结构、能量可去除膜和第二介电层上形成顶面层。方法2包括框22,其中,将能量施加于衬底以部分去除能量可去除膜,从而形成气隙。
应该理解,可在图1所示的框4至框22之前、期间或之后执行附加工艺以完成半导体器件的制造,但为了简化,本发明没有详细讨论这些附加工艺。
图2至图12是根据图1中的方法2的实施例的处于各个制造阶段的半导体器件的局部截面示意图。应该理解,为了更好地理解本发明的发明概念,已简化了图2至图12。应该理解,本发明所描述的材料、几何形状、尺寸、结构以及工艺参数仅是示例性的,但不是旨在且不应被解释为限制本发明所要求保护的发明。本领域技术人员一旦得知本发明,则许多替换和修改对本领域技术人员都是显而易见的。
参照图2,提供半导体器件100。半导体器件100可以是集成电路(IC)芯片、***级芯片(SOC)或它们的一部分,其可包括各种无源和有源微电子器件,诸如电阻器、电容器、电感器、二极管、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极结型晶体管(BJT)、横向扩散MOS(LDMOS)晶体管、高功率MOS晶体管或其他类型的晶体管。半导体器件100包括衬底110。衬底110可以是半导体晶圆的一部分。例如,衬底可包括硅。衬底110可以可选地由其他一些诸如金刚石或锗的适合的元素半导体、诸如碳化硅、砷化铟或磷化铟的适合的化合物半导体或者诸如碳化硅锗、磷化镓砷或磷化镓铟的适合的合金半导体制成。在一个实施例中,衬底110包括用于各种微电子元件的各种掺杂部件,诸如互补金属氧化物半导体场效应晶体管(CMOSFET)、图像传感器、存储器单元和/或电容元件。
在一些实施例中,在衬底110上形成层间介电(ILD)层115。ILD层115包括介电材料,例如非掺杂硅酸盐玻璃(USG)或磷硅酸盐玻璃(PSG)。ILD层115可包括其他适合的材料。
在ILD层115的上方形成导电层(未示出)。导电层还可称为金属层且包括导电材料。在一个实施例中,导电材料是铜。
在ILD层115和/或导电层的上方形成材料层120。材料层120可以是蚀刻终止层,因此可选地在下文称为蚀刻终止层120。蚀刻终止层120可具有合适的厚度,使得以下用于形成通孔的蚀刻工艺能够留有足够的蚀刻裕度而适当地停止于蚀刻终止层120。蚀刻终止层120可包括氮化硅、氮氧化硅、碳化硅、氮碳化硅、其他合适材料或它们的组合。
如图2所示,在蚀刻终止层120上形成第一介电层130。第一介电层130包括氧化硅、氮化硅、低介电常数(低k)材料或它们的组合。例如,低k材料可包括氟化硅玻璃(FSG)、掺碳氧化硅、干凝胶、气凝胶、氟化非晶碳、聚对二甲苯、BCB(苯并环丁烯)、聚酰亚胺和/或其他材料。形成第一介电层130的工艺可使用CVD或旋涂工艺。第一介电层130的厚度可在约50埃至约2000埃的范围之间。应该理解,所提到的尺寸仅仅是实例,且随着集成电路按比例缩小而改变。
现在参照图3,根据一个实施例,对半导体器件100执行图案化工艺142,以在第一介电层130中形成终止于蚀刻终止层120的多个第一开口(或通孔)140。图案化工艺142可包括使用诸如光刻、浸没式光刻、离子束写入的工艺或其他合适的工艺形成图案化的光刻胶层(未示出)。例如,光刻工艺可包括旋涂、软烘、曝光、后烘、显影、冲洗、烘干以及其他合适工艺。图案化工艺142还可包括蚀刻工艺,其中,图案化的光刻胶层可用作掩模以在第一介电层130中蚀刻开口。
尽管能理解可形成许多其他开口,但为了简化,这里仅示出第一开口140。每一个第一开口140均与下面衬底中的对应一个导电层(垂直)对齐。
现在参照图4,执行沉积工艺以在第一介电层130的上方形成扩散阻挡层150。在第一介电层130的顶部上以及第一介电层130的开口中形成扩散阻挡层150。如图4所示,在以下进一步讨论的随后步骤中去除扩散阻挡层150沉积在第一介电层130顶面上的部分。扩散阻挡层150阻止金属层结构扩散至相邻的介电材料。在示例性实施例中,沉积工艺包括化学汽相沉积(CVD)工艺。在另一个实施例中,沉积包括原子层沉积(ALD)工艺。扩散阻挡层150包括导电材料。在一个实施例中,导电材料选自由钽(Ta)、氮化钽(TaNx)、钛(Ti)、氮化钛(TiNx)、氧化锰(MnOx)和它们的组合所组成的组。在一个实施例中,扩散阻挡层150的厚度小于约50埃。在一些实施例中,在第一介电层130的开口中形成粘附层和/或铜晶种层。
仍参照图4,对半导体器件100执行镶嵌沉积工艺155。镶嵌沉积工艺155将导电材料沉积在第一介电层130的第一开口140中。导电材料可另外位于第一介电层130上方或第一介电层130上。在一个实施例中,导电材料是铜。在其他实施例中,导电材料可包括铜、铜合金、钨、钛、氮化钛或它们的组合。在一个实施例中,镶嵌工艺155包括化学沉积(ELD)工艺。在另一个实施例中,镶嵌沉积工艺155包括电镀工艺(ECP)。在镶嵌沉积工艺155之后,随后执行包括化学机械抛光(CMP)工艺的平坦化工艺,使得导电材料的顶部与第一介电层130的顶部共面。该工艺还去除了形成在第一介电层130顶面上的扩散阻挡层部分。平坦化工艺可以可选或同时包括回蚀工艺或其他适合工艺。作为镶嵌工艺和后续CMP工艺的结果,在第一开口140中形成多个第一导电层结构160。
现在参照图5,对半导体器件100执行图案化工艺165,以在第一介电层130和第一导电层结构160的上方形成掩模层。在一个实施例中,掩模层包括光刻胶材料,其使用与以上参照图3所讨论的光刻工艺类似的光刻工艺进行图案化。掩模层或图案化的光刻胶材料层包括每一个均位于对应的一个第一导电层结构160上方的部分180。在一些实施例中,部分180均包括底部抗反射涂覆(BARC)层170。在一些实施例中,每一个掩模层部分180的宽度均大于对应的第一导电层结构160的宽度。虽然在截面图中仅示出二维(例如,x-y平面),但是本领域技术人员应该理解,在未示出的方向上(即,延伸入页面或延伸到页面外的x-z平面)掩模层部分180也可比第一导电层结构160的对应宽度宽。在另一个实施例中,掩模层包括介电材料,例如氧化硅、氮化硅等,其可通过图案化的光刻胶层进行图案化以形成部分180。在随后的工艺中,去除部分180以在半导体器件100中形成开口或沟槽。
现在参照图6,对半导体器件100执行热分解材料沉积工艺185以在第一介电层130上以及掩模层部分180的顶部和侧壁上形成能量去除膜(ERF)190。能量去除膜190使用能量去除材料。能量去除材料是暴露于诸如紫外线(UV)、X射线、红外线、可见光、热能、电子束(e-beam)的合适能量和/或其他适合能量源时可分解的材料。例如,一种能量去除材料对于电子能量范围在约100eV至约500KeV之间的电子束而言是可分解的。能量去除材料包括光子分解材料、热分解材料以及电子束分解材料。在一个实施例中,ERF190包括有机化合物。在另一个实施例中,ERF190包括硅基CxHy化合物。在又一个实施例中,ERF190包括诸如P(新戊基甲基丙烯酸乙二醇二甲基丙烯酸酯)共聚物,简写为P(npMAco-EGDA)的热分解聚合物。ERF190的厚度可在约50埃至约1000埃的范围之间。可通过诸如化学汽相沉积(CVD)的适合工艺形成ERF190。
如图7所示,回蚀工艺或其他适合工艺去除位于掩模层部分180的顶部和第一介电层130的顶部上的ERF190,保留掩模层的每一部分180的侧壁上的ERF190。
如图8所示,在能量可去除膜190、硬掩模层的部分180和第一介电层130的上方形成第二介电层200。第二介电层200包括氧化硅、氮化硅、低介电常数(低k)材料或它们的组合。例如,低k材料可包括氟化硅玻璃(FSG)、掺碳氧化硅、干凝胶、气凝胶、氟化非晶碳、聚对二甲苯、BCB(苯并环丁烯)、聚酰亚胺和/或其他材料。形成第二介电层200的工艺可使用CVD或旋涂工艺。第二介电层200的厚度可在约50埃至约2000埃的范围之间。应该理解,提到的尺寸仅仅是实例,并且随着集成电路按比例缩小而改变。在一个实施例中,第二介电层200具有多孔结构,可以使得在随后的步骤中适当地形成气隙。在一个实施例中,第二介电层200具有孔隙率范围在约0.5%至约80%之间的多孔结构。根据一个实施例,第二介电层200使用具有合适的多孔结构且介电常数范围在约3至约4之间的氮化硅。通过CVD工艺形成多孔氮化硅的前体可包括更多的有机材料以提高气孔的形成。
在图9所示的下一步骤中,去除部分第二介电层200以及硬掩模层的部分180,以在第二介电层200中留下多个第二开口205。在一些实施例中,在部分180均包括底部抗反射涂覆(BARC)层170的情况下,也去除BARC层170。在一个实施例中,如本领域所公知的,使用低k回蚀工艺来去除部分第二介电层200。在掩模层的部分180是图案化光刻胶层的实施例中,通过剥离来去除图案化的光刻胶层。在示例性实施例中,如本领域所公知的,使用等离子体蚀刻工艺剥离图案化的光刻胶层。在可选实施例中,使用湿蚀刻工艺剥离图案化的光刻胶层。
现在参照图10,对半导体器件100执行镶嵌沉积工艺220。镶嵌沉积工艺220将导电材料沉积在第二介电层200的第二开口205中。在一个实施例中,导电材料是铜。在其他实施例中,导电材料可包括铜、铜合金、钨、钛、氮化钛或它们的组合。在一个实施例中,镶嵌工艺220包括化学沉积(ELD)工艺。在另一个实施例中,镶嵌沉积工艺220包括电镀工艺(ECP)。在镶嵌沉积工艺220之后,执行包括化学机械抛光(CMP)工艺的平坦化工艺,使得导电材料的顶部与第二介电层200的顶部共面。平坦化工艺可以可选地或同时包括回蚀工艺或其他合适工艺。如本领域技术人员所理解的,镶嵌工艺可包括在沉积导电材料之前,在第二开口205中形成一层或多层阻挡层和/或晶种层。作为镶嵌工艺以及随后的CMP工艺的结果,在第二开口205中形成多个第二导电层结构210。
在图11中,对半导体器件100执行顶面层沉积工艺230以在第二导电层结构210、能量可去除膜190和第二介电层200上形成顶面层220。顶面层220具有多孔结构,使得在随后的步骤中,可以适当地去除能量去除膜190中的能量去除材料。在一个实施例中,顶面层220具有介电常数范围在约2.5至约4之间的多孔结构。在一个实施例中,顶面层220包括诸如氮化硅、氮氧化硅、碳化硅、氮碳化硅、其他适合材料或它们的组合的蚀刻终止层(ESL)。在成分和结构方面,顶面层220可与蚀刻终止层120基本类似。在另一个实施例中,顶面层220包括诸如FSG、掺碳氧化硅、干凝胶、气凝胶、氟化非晶碳、聚对二甲苯、BCB、SiLK、聚酰亚胺和/或其他适合材料的低k介电材料层。顶面层220的厚度可在约10埃至约500埃的范围之间。应该理解,所提到的尺寸仅仅是实例,并且随着集成电路的按比例缩小而改变。
参照图12,对半导体器件100执行能量工艺235以形成气隙240。能量工艺235至少部分地去除能量可去除膜190,从而得到气隙240。施加于能量可去除膜190的能量包括紫外线(UV)、X射线、红外线、可见光、热能、电子束(e-beam)和/或其他合适的能量。一种施加于能量可去除膜190的示例性能量源包括电子能量范围在约100eV至约500KeV之间的电子束源。施加于能量可去除膜190的能量可与某一类型的能量结合持续一定时间,使得可至少部分地去除能量可去除膜190来形成气隙240。在一个实施例中,以范围在约100摄氏度至约600摄氏度之间的温度和/或约1分钟至约20分钟的持续时间来施加热能。在另一个实施例中,以范围在约100摄氏度至约600摄氏度之间的温度和/或约1分钟至约10分钟的持续时间来施加紫外线能量。在暴露于所施加的能量时,能量可去除膜190被部分去除,从而得到如图12所示的气隙240。在图12所示的实施例中,气隙240具有狭缝式形状。气隙240基本形成在之前由能量可去除膜190占据的区域内,该区域位于由具有小间距的第二导电层结构210限定的区域内。因此,防止了气隙坍塌。在一些实施例中,如图12示意性示出的,能量工艺235可增加第二介电层200的孔隙率。
本发明提供了气隙基本上分布在具有小间距的相邻的导电层结构或部件之间所限定的能量可去除膜区域内的结构及其制造方法。因此,基本上减少或消除了气隙坍塌。
本发明可包括其他变形、扩展和实施例而不背离本发明的精神。例如,上述光刻工艺可仅呈现了与光刻图案化技术相关的工艺步骤的一个子集。光刻工艺还可包括合适顺序的诸如清洗和烘焙的其他步骤。光刻工艺可具有其他变形。例如,抗反射涂覆(ARC)层可位于光刻胶层的上方,称为顶部ARC(TARC)。根据本发明的方面,能量去除材料和顶面层可使用其他镶嵌技术,以形成在能量去除材料中引入气隙的多层互连结构,同时减小介电常数以及减小气隙坍塌效应。
本发明描述了各个示例性实施例。根据一个实施例,一种制造半导体器件的方法包括提供衬底。在衬底上形成图案化第一介电层,图案化第一介电层具有多个第一开口。将第一导电材料填充在多个第一开口中,第一导电材料限定第一导电层结构。在第一介电层和第一导电层结构的上方形成掩模层。掩模层包括多个部分,每一部分都位于对应的一个第一导电层结构上方。掩模层的每一部分的宽度均大于对应的一个第一导电层结构的宽度。在掩模层的每一部分的侧壁上形成能量可去除膜(ERF)。在能量可去除膜、掩模层的部分和第一介电层的上方形成第二介电层。去除掩模层部分以留下多个第二开口。将第二导电材料填充在多个第二开口中,第二导电材料限定第二导电层结构。在第二导电层结构、能量可去除膜和第二介电层上形成顶面层。将能量施加于衬底,以部分去除能量可去除膜并且形成气隙。
根据另一个实施例,一种形成镶嵌层的方法包括在半导体衬底上的第一介电层中形成多个第一导电层结构。形成图案化光刻胶层,其中,图案化光刻胶层具有多个部分,每一部分均位于对应的一个第一导电层结构的上方,并且图案化光刻胶层的每一部分的宽度均大于对应的一个第一导电层结构的宽度。在第一介电层以及图案化光刻胶层的部分的顶部和侧壁上形成能量可去除膜(ERF)。蚀刻能量可去除膜,从而仅保留图案化光刻胶层的每一部分的侧壁上的能量可去除膜。在能量可去除膜、图案化光刻胶层的部分和第一介电层的上方形成第二介电层。去除图案化光刻胶层的部分以留下多个开口。将导电材料填充在多个开口中,导电材料限定第二导电层结构。在第二导电层结构、能量可去除膜和第二介电层的上方形成顶面层。将能量施加于衬底,以部分地去除光刻胶层的部分的侧壁上的能量可去除膜,从而形成气隙。
根据又一个实施例,一种半导体器件包括设置在半导体衬底上的第一介电层中的多个第一金属层结构。多个第二金属层结构设置在第二介电层中,其中,多个第二金属层结构的每一个均位于多个第一金属层结构中的对应第一金属层结构的上方,并且第二金属层结构中的每一个的宽度均大于第一金属层结构中的对应第一金属层结构的宽度。能量可去除膜设置在第二金属层结构的侧壁上。气隙设置在第二金属层结构的侧壁上的能量可去除膜和第二介电层之间。在第二金属层结构、能量可去除膜和第二介电层的上方形成顶面层。
在以上详细的描述中,已描述了具体示例性的实施例。然而,对于本领域的技术人员很明显的是,可以另外进行各种修改、结构、工艺以及改变而不背离本发明更广泛的精神和范围。因此,说明书和附图被认为是说明性的但不是限制性的。应该理解,本发明的实施例能够在各种其他组合和环境使用并且能够在权利要求的范围内进行改变或修改。
Claims (10)
1.一种制造半导体器件的方法,包括:
提供衬底;
在所述衬底上形成图案化第一介电层,所述图案化第一介电层具有多个第一开口;
将第一导电材料填充在所述多个第一开口中,所述第一导电材料限定第一导电层结构;
在所述第一介电层和所述第一导电层结构的上方形成掩模层,所述掩模层包括多个部分,每一部分均位于对应的一个所述第一导电层结构的上方,并且所述掩模层的每一部分的宽度均大于对应的一个所述第一导电层结构的宽度;
在所述掩模层的每一部分的对应侧壁上形成能量可去除膜(ERF);
在所述能量可去除膜、所述掩模层的多个部分和所述第一介电层的上方形成第二介电层;
去除所述掩模层的多个部分以留下多个第二开口;
将第二导电材料填充在所述多个第二开口中,所述第二导电材料限定第二导电层结构;
在所述第二导电层结构、所述能量可去除膜和所述第二介电层上形成顶面层;以及
将能量施加于所述衬底,以至少部分地去除所述能量可去除膜并形成气隙。
2.根据权利要求1所述的方法,还包括:
在将所述第一导电材料填充在所述多个第一开口中之前,在所述图案化第一介电层上和所述第一开口内形成阻挡层。
3.根据权利要求1所述的方法,还包括:
在将所述第一导电材料填充在所述多个第一开口中的步骤之后,平坦化所述第一导电材料,使得所述第一导电材料的顶部与所述第一介电层的顶部共面。
4.根据权利要求1所述的方法,其中,所述掩模层是图案化光刻胶层。
5.根据权利要求4所述的方法,其中,所述图案化光刻胶层包括底部抗反射涂覆(BARC)层。
6.根据权利要求1所述的方法,其中,形成所述能量可去除膜包括:形成选自由光子分解材料、热分解材料、电子束分解材料和它们的组合所组成的组中的材料。
7.根据权利要求1所述的方法,其中,形成所述顶面层包括:形成选自由蚀刻终止层、低k介电材料层和它们的组合所组成的组中的材料层。
8.根据权利要求1所述的方法,其中,形成所述顶面层包括形成多孔材料层。
9.一种形成镶嵌层的方法,包括:
在半导体衬底上的第一介电层中形成多个第一导电层结构;
形成图案化光刻胶层,所述图案化光刻胶层具有多个部分,每一部分都位于对应的一个所述第一导电层结构的上方,并且所述图案化光刻胶层的每一部分的宽度均大于对应的一个所述第一导电层结构的宽度;
在所述第一介电层上以及所述图案化光刻胶层的多个部分的顶部和侧壁上形成能量可去除膜(ERF);
蚀刻所述能量可去除膜,仅保留所述图案化光刻胶层的每一部分的侧壁上的所述能量可去除膜;
在所述能量可去除膜、所述图案化光刻胶层的多个部分和所述第一介电层的上方形成第二介电层;
去除所述图案化光刻胶层的部分,以留下多个开口;
将导电材料填充在所述多个开口中,所述导电材料限定第二导电层结构;
在所述第二导电层结构、所述能量可去除膜和所述第二介电层的上方形成顶面层;以及
将能量施加于所述衬底,以至少部分地去除所述光刻胶层的部分的侧壁上的所述能量可去除膜,从而形成气隙。
10.一种半导体器件,包括:
多个第一金属层结构,位于半导体衬底上的第一介电层中;
多个第二金属层结构,位于第二介电层中,所述多个第二金属层结构的每一个结构都位于所述多个第一金属层结构中的对应一个结构的上方,并且所述第二金属层结构中的每一个结构的宽度均大于对应的一个第一金属层结构的宽度;
能量可去除膜,设置在所述第二金属层结构各自的侧壁上;
气隙,设置在所述第二金属层结构的侧壁上的能量可去除膜和所述第二介电层之间;以及
顶面层,形成在所述第二金属层结构、所述能量可去除膜和所述第二介电层的上方。
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US8900989B2 (en) | 2014-12-02 |
CN104037121B (zh) | 2017-07-21 |
US20150132952A1 (en) | 2015-05-14 |
US20140252633A1 (en) | 2014-09-11 |
US9299603B2 (en) | 2016-03-29 |
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