CN104022672A - Self-adaptive adjustable delay circuit for soft-switch ZVT (zero voltage transformation) converter - Google Patents

Abstract

The invention discloses a self-adaptive adjustable delay circuit for a soft-switch ZVT (zero voltage transformation) converter. The soft-switch ZVT converter is characterized in that an auxiliary switch is introduced in a main circuit, the auxiliary switch is conducted before the conduction of the corresponding main switch, and the starting time of the resonance oscillation is controlled through the auxiliary switch. The self-adaptive adjustable delay circuit comprises a main switch zero-pass detection circuit which is used for detecting a voltage zero-pass point of a main switch of the converter and a main-auxiliary switch logic control circuit which is used for automatically adjusting the delay time between the auxiliary switch and the main switch of the converter; the main-auxiliary switch logic control circuit is used for enabling the main switch to be switched on according to the zero-pass point of the main switch detected by the main switch zero-pass detection circuit at the moment when voltage of the main switch is reduced to zero. The delay time between the auxiliary switch and the main switch is automatically adjusted, so that the main switch is switched on just at the moment when the voltage of the main switch is reduced to zero, the self-adaptive control of the zero voltage switch is realized, and the high-efficiency operation of the soft switch in the full-load variation range of the converter can be realized.

Description

For the self adaptation adjustable delay circuit of soft switch ZVT converter

Technical field

The present invention relates to a kind of self adaptation adjustable delay circuit for soft switch ZVT converter, relate in particular to the self adaptation adjustable delay circuit of the soft switch ZVT of a kind of bridge-type inverter.

Background technology

High power density and miniaturization and are one of development trends of converters, and high frequency is the inevitable choice of realizing this goal.High switching loss, high voltage and current stress that traditional hard switching causes with the raising of switching frequency, make transducer effciency reduction, reliability decrease, thereby limited miniaturization and the lightweight of converter.Soft switch technique, by introducing resonant circuit, the switching process of switching device being controlled, makes its switch under no-voltage or zero current condition, thereby obviously reduces even to eliminate switching loss.Therefore, soft switch technique is converters miniaturization and light-weighted inevitable requirement.Soft switch ZVT converter is the Typical Representative of current soft switch circuit.

In the time of soft switch ZVT converter work, auxiliary switch is open-minded prior to corresponding main switch, and the time of opening is in advance realized by the delay circuit of fixing conventionally.In the time that the excursion of load current size is wider, this method is difficult to ensure the ZVS performance of main switch.Taking the at present popular soft switch ZVT of coupling inductance inverter as example, one bridge topology as shown in Figure 1.If adopt fixing delay time, when load current hour, in delay time, main switch reaches zero-voltage state very soon, but will wait until that delay time is to opening, and may cause effective duty cycle loss; And load current is when larger, because coupling inductance Current rise is to the overlong time of load current and beginning resonance, cause main switch to reach the time lengthening of no-voltage, be greater than fixing delay time, in the time that opening to, main switch, delay time because of also resonance to zero not of the voltage at its two ends, therefore cannot realize ZVS.In order to address the above problem, people propose to change fixing time delay into adjustable time delay control, basic ideas are to regulate delay time according to the size and Orientation of load current, but load current size and Orientation is difficult to judgement in the time of zero crossing, and there is the biasing problem of noise jamming and current regulating circuit.

Summary of the invention

The deficiency existing for solving prior art, the invention discloses the self adaptation adjustable delay circuit for soft switch ZVT converter, this circuit regulates the delay time between auxiliary switch and main switch automatically, main switch is opened just occur in main switch voltage to be down to moment of zero, realize the adaptive control of zero voltage switch, made converter soft switch high-efficiency operation in full load excursion.

For achieving the above object, concrete scheme of the present invention is as follows:

For the self adaptation adjustable delay circuit of soft switch ZVT converter, in the main circuit of described soft switch ZVT converter, introduce auxiliary switch, auxiliary switch, prior to corresponding main switch conducting, adopts the zero hour of auxiliary switch control resonance;

Described self adaptation adjustable delay circuit comprises for detection of the main switch zero cross detection circuit of converter main switch voltage over zero and for automatically regulating the main and auxiliary switching logic control circuit of delay time between converter auxiliary switch and main switch; The zero crossing that described main and auxiliary switching logic control circuit detects main switch according to main switch zero cross detection circuit makes main switch open the moment of being down to zero at main switch voltage.

The main switch of described converter and auxiliary switch are gated transistor IGBT or field effect transistor M OSFET.

Described main switch zero cross detection circuit comprises fast recovery diode and high speed voltage comparator, the negative electrode of fast recovery diode and the collector electrode of main switch join, the anode of fast recovery diode and the inverting input of high speed voltage comparator join, the reference ground of high speed voltage comparator and the emitter of main switch join, and in-phase input end and the resistor network of high speed voltage comparator join.

The in-phase input end of described high speed voltage comparator and the resistor network formation hysteresis loop comparator that joins, described hysteresis loop comparator upper limit U _ref+provided by following formula:

$U_{\mathrm{ref}+}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\×V_{+}-\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}\×V_{-}---\left(1\right)$

Hysteresis loop comparator lower limit U _ref-provided by following formula:

$U_{\mathrm{ref}-}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\×V_{+}-(\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}+\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2})\×V_{-}---\left(2\right)$

The upper limit U of hysteresis loop comparator _ref+hysteresis loop comparator lower limit U _ref-the return difference Δ U forming is:

$\mathrm{\ΔU}{=U}_{\mathrm{ref}+}-U_{\mathrm{ref}-}=\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2}\×V_{-}---\left(3\right)$

Wherein, R ₁r ₂r ₃for forming the resistance of resistor network, V ₊for the positive supply voltage of high speed voltage comparator, V _-for the negative supply power voltage of high speed voltage comparator.

Described master, auxiliary switch logic control circuit comprise first with door and second with, or door, dead band delay circuit and reset delay circuit, described first with input and the main switch zero cross detection circuit of door in the output of high speed voltage comparator join, first with door another input with second and output join, the second pwm signal of exporting with input of door and control circuit joins, second with door another input with by pwm signal the output after the delay circuit of dead band join, first with door output with or door an input join, or another input of door with join with the output of output after reset delay circuit of door second, or the output signal of door is as the control signal of main switch, second with the output of door as the control signal of auxiliary switch.

Operation principle: the pwm switching signal of being exported by control circuit, it is open-minded that the control signal after Dead Time (for avoiding the straight-through time delay of introducing of upper and lower two pipe of same bridge) time delay goes to control auxiliary switch.The moment of opening that auxiliary switch is opened rear main switch regulates by the voltage adaptive that detects main switch two ends, in the zero cross detection circuit of main switch, when the voltage at main switch two ends is down to reference voltage U _ref-, high speed voltage comparator output switching activity uprises, through first with door and or behind the door main switch control signal uprise, now can control main switch no-voltage open-minded.Complete thus the adaptive control to main switch zero voltage switch.

Beneficial effect of the present invention:

The present invention regulates the delay time between auxiliary switch and main switch automatically, main switch is opened just occur in main switch voltage to be down to moment of zero, realize the adaptive control of zero voltage switch, made converter soft switch high-efficiency operation in full load excursion.

The results show, when main switch turn-offs, collection radio is pressed and is not had obvious overshoot, and voltage stress is very little, visible, and soft switch, in reducing switching loss, raising the efficiency, has also been optimized the running environment of switch, has reduced electromagnetic interference.When output is by underloading during to specified variation, the efficiency of surveying this soft switch ZVT inverter maintains 98% left and right.

Brief description of the drawings

Fig. 1 is the soft switch ZVT of coupling inductance inverter one bridge topological diagram;

Fig. 2 is control signal sequential chart and main oscillogram;

Fig. 3 is main switch S in the present invention ₁zero cross detection circuit figure;

Fig. 4 is major-minor switching logic control circuit figure in the present invention;

Fig. 5 is the experimental waveform figure (Io=0.3A) of the present invention during for the soft switch ZVT of coupling inductance inverter control;

Fig. 6 is the experimental waveform figure (Io=7.6A) of the present invention during for the soft switch ZVT of coupling inductance inverter control.

Embodiment:

Below in conjunction with accompanying drawing, the present invention is described in detail:

In the application, soft switch ZVT converter is taking the soft switch ZVT of coupling inductance inverter as example, and one bridge topology as shown in Figure 1.S in Fig. 1 ₁, S ₂be respectively the upper and lower main switch of same bridge; S _x1, S _x2be respectively S ₁, S ₂auxiliary switch; T _r1, T _r2be two coupling inductances, L _m1, L _r1be respectively T _r1magnetizing inductance and leakage inductance, L _m2, L _r2be respectively T _r2magnetizing inductance and leakage inductance; C ₁, C ₂for resonant capacitance; D _x1-D _x6for booster diode.Main switch and auxiliary switch are all selected IGBT pipe.Can form the soft switch ZVT of single-phase H bridge inverter with the identical two cover topologys of Fig. 1, wherein the mid point of main switch bridge, the interchange output that produces inverter after the filtering of LC low pass filter.

Fig. 2 is the main and auxiliary control signal of switch and the main voltage and current waveform of helping, and wherein PWM is the pulse-width signal that carrys out self-controller; u _gs1, u _gs2, u _gsx1, u _gsx2be respectively main switch S ₁, S ₂with auxiliary switch S _x1, S _x2control signal; I ₀be load current, while analyzing soft switching process, can be similar to and regard constant as; i _lrit is resonance current; u _ce1for main switch S ₁on voltage; u _lm1, i _lm1be respectively T _r1voltage and current on magnetizing inductance.In order to explain self adaptation adjustable delay circuit of the present invention, the operation principle of the soft switch ZVT of coupling inductance inverter is first described in conjunction with Fig. 2.

Suppose circuit initial condition: t ₀before moment, S ₁in off-state, S ₂(press the sense of current in figure, be actually D in on-state ₂conducting).

1) mode [t ₀～t ₁]: t ₀moment, main switch S ₂no-voltage is turn-offed, load current I ₀through anti-paralleled diode D ₂afterflow.

2) mode [t ₁～t ₂]: t ₁moment, main switch S ₁auxiliary switch S _x1controlled open-minded, meanwhile, diode D _x3also start conducting, make coupling inductance T _x1in current i _lrlinear increasing, exciting current i _lm1the foundation of starting from scratch.

3) mode [t ₂～t ₃]: t ₂moment, current i _lrrise to and load current I ₀equate after this leakage inductance and resonance capacitor C ₁, C ₂start resonance, i _lrcontinuing increases, C ₂charging, C ₁electric discharge.Therefore S ₁both end voltage u _ce1start to decline, S in like manner ₂both end voltage u _ce2start to rise.

4) mode [t ₃～t ₄]: t ₃moment, C ₂charging voltage rise to DC voltage U _dc, C ₁discharging into voltage is zero, i.e. u _ce1drop to zero, now control S ₁no-voltage is open-minded, resonance current i _lrstart to decline.

5) mode [t ₄～t ₅]: t ₄moment, booster diode D _x3naturally turn-off resonance current i _lrdrop to exciting current value i _lm1, due to the voltage u on winding after this _lm1be zero, therefore this stage exciting current value i _lm1remain unchanged.

6) mode [t ₅～t ₆]: t ₅moment, auxiliary switch S _x1controlled shutdown, diode D _x4afterflow is open-minded, exciting current i _lm1start to reset.Because resetting voltage equals DC voltage U _dc, therefore i _lm1reset-to-zero rapidly.

7) mode [t ₆～t ₇]: t ₆moment, exciting current i _lm1reset-to-zero, diode D _x4naturally turn-off this one-phase main switch S ₁whole load currents of flowing through.

8) mode [t ₇～t ₈]: t ₇moment, S ₁no-voltage is turn-offed, load current I ₀then the C that flows through ₁, C ₂, to C ₁charging, C ₂electric discharge, u _ce1start rising, u _ce2start to decline.

9) mode [t ₈～t ₉]: t ₈moment, C ₁charge complete, terminal voltage u _ce1rise to U _dc.C ₂discharge off, u _ce2drop to zero, load current is by diode D ₂afterflow.

10) mode [t ₉～t ₀]: t ₉moment S ₂no-voltage is open-minded, considers the direction of load current, in fact from t ₈after moment, be D always ₂whole load currents are born in afterflow, and in circuit, each amount does not change.S during this period _x2controlled open-minded, but because resonance does not occur this one-phase, that is S _x2flow through though opened but no current, belong to zero current turning-on.

In the time that load current is reverse, operation principle, is not repeating to above-mentioned similar with waveform.

Below explain how to realize the soft switch of ZVS by self adaptation adjustable delay circuit.Without loss of generality, with S ₁for example explanation.Because of resonant capacitance C ₁with S ₁parallel connection, S ₁always can realize no-voltage and turn-off, therefore, below Main Analysis how self adaptation regulate delay time to make S ₁realize no-voltage open-minded.As mentioned above, at mode [t ₂～t ₃], work as current i _lrrise to and load current I ₀after, leakage inductance and resonance capacitor C ₁, C ₂start resonance, i _lrcontinuing increases, C ₂charging, C ₁electric discharge.That is t ₂moment, u _ce1start to decline until t ₃moment is reduced to zero.If now control S ₁open-minded, S ₁be no-voltage open-minded.

Fig. 3 is the zero cross detection circuit of main switch in the present invention, without loss of generality, and with S ₁for example explanation, its zero cross detection circuit is by high speed voltage comparator A ₁, fast recovery diode VD ₁, and resistance R ₁, R ₂and R ₃composition, wherein VD ₁negative electrode and the collector electrode of main switch join, VD ₁anode and A ₁inverting input join, A ₁reference ground and the emitter of main switch join, A ₁in-phase input end and R ₁-R ₃the resistor network of composition joins.So connect A ₁inverting input can detect main switch S ₁collection emitter voltage u _ce1, in-phase input end is reference voltage U _ref.In order to prevent u _ce1testing circuit in the shake of near zero-crossing point, cause switching noise, high speed voltage comparator is designed to hysteresis loop comparator by the present invention, A shown in Fig. 3 ₁in-phase input end and R ₁-R ₃the resistor network of composition forms hysteresis loop comparator.

Hysteresis loop comparator upper limit U _ref+provided by following formula:

$U_{\mathrm{ref}+}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\×V_{+}-\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}\×V_{-}---\left(1\right)$

Hysteresis loop comparator lower limit U _ref-provided by following formula:

$U_{\mathrm{ref}-}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\×V_{+}-(\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}+\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2})\×V_{-}---\left(2\right)$

Return difference Δ U is:

$\mathrm{\ΔU}{=U}_{\mathrm{ref}+}-U_{\mathrm{ref}-}=\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2}\×V_{-}---\left(3\right)$

Return difference Δ U generally can be designed to 2V left and right, can avoid the shake of zero cross detection circuit near zero-crossing point.Work as u _ce1>U _ref+time, hysteresis loop comparator output logic low level; u _ce1<=U _ref-time, hysteresis loop comparator output switching activity becomes logic high, shows main switch S ₁collection emitter voltage zero passage.

Fig. 4 is main switch S in the present invention ₁, S ₂with auxiliary switch S _x1, S _x2logic control circuit, without loss of generality, still with S ₁and S _x1for example illustrates: by two inputs and a door AND ₁and AND ₂, two input or door OR ₁, dead band time delay Y ₁with reset delay Y ₂composition, wherein with door AND ₁input and main switch S ₁high speed voltage comparator A in zero cross detection circuit ₁output join, another input with door AND ₂output join, with door AND ₂input and the pwm signal of control circuit output join, another input with by pwm signal through dead band time delay Y ₁after output join, or door OR ₁input with door AND ₁output join, another input with by AND ₂output through reset delay Y ₂after output join, or door OR ₁output signal as the control signal u of main switch _gs1, with door AND ₂output as the control signal u of auxiliary switch _gsx1.So connect, can produce the control signal u of major-minor switch as shown in Figure 2 _gs1, u _gsx1deng.

Implementation brief introduction is as follows: the pwm switching signal of being exported by control circuit, the control signal u after Dead Time (for avoiding the straight-through time delay of introducing of upper and lower two pipe of same bridge) time delay _gsx1remove to control auxiliary switch S _x1open (the t in corresponding diagram 2 ₁moment).S _x1open rear main switch S ₁when open by detecting S ₁the voltage u at two ends _ce1self adaptation regulates, and from the zero cross detection circuit of S1 in Fig. 3, works as u _ce1be down to reference voltage U _ref, comparator output switching activity uprises, warp and door AND ₁with or door OR ₁rear u _gs1uprise, now can control S ₁no-voltage is opened the (t in corresponding diagram 2 ₃moment).Complete thus the adaptive control to main switch zero voltage switch.

Fig. 5, Fig. 6 are the experimental waveform of the present invention during for the soft switch ZVT of coupling inductance inverter control different loads electric current, wherein load current Io=0.3A in Fig. 5, load current Io=7.6A in Fig. 6.Experiment condition is: inverter DC input voitage is 400V, and inverter output connects an adjustable resistance as load after LC low pass filter, tests the performance of soft switch ZVT inverter.Analyze comparison diagram 5 and Fig. 6, can obviously find out that coupling inductance resonance current peak value is relevant with load current size, load current is larger, and resonance current peak value is higher, and it is longer that main switch voltage is down to time of zero; Otherwise shorter.But owing to having adopted self adaptation adjustable delay method, regardless of load current size, main switch always can be realized no-voltage (ZVS) switch, and experimental waveform and theory analysis match.And collection radio is pressed and do not had obvious overshoot when main switch turn-offs, voltage stress is very little, visible, and soft switch, in reducing switching loss, raising the efficiency, has also been optimized the running environment of switch, has reduced electromagnetic interference.When output is by underloading during to specified variation, the efficiency of surveying this soft switch ZVT inverter maintains 98% left and right, and this is that the soft switch of ZVT of hard switching circuit and employing constant time lag method cannot be realized.

By reference to the accompanying drawings the specific embodiment of the present invention is described although above-mentioned; but not limiting the scope of the invention; one of ordinary skill in the art should be understood that; on the basis of technical scheme of the present invention, those skilled in the art do not need to pay various amendments that creative work can make or distortion still in protection scope of the present invention.

Claims (8)

1. for the self adaptation adjustable delay circuit of soft switch ZVT converter, it is characterized in that, in the main circuit of described soft switch ZVT converter, introduce auxiliary switch, auxiliary switch, prior to corresponding main switch conducting, adopts the zero hour of auxiliary switch control resonance; Described self adaptation adjustable delay circuit comprises for detection of the main switch zero cross detection circuit of converter main switch voltage over zero and for automatically regulating the main and auxiliary switching logic control circuit of delay time between converter auxiliary switch and main switch; The zero crossing that described main and auxiliary switching logic control circuit detects main switch according to main switch zero cross detection circuit makes main switch open the moment of being down to zero at main switch voltage.

2. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 1, is characterized in that, the main switch of described converter and auxiliary switch are gated transistor IGBT or field effect transistor M OSFET.

3. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 1, it is characterized in that, described main switch zero cross detection circuit comprises fast recovery diode and high speed voltage comparator, the negative electrode of fast recovery diode and the collector electrode of main switch join, the anode of fast recovery diode and the inverting input of high speed voltage comparator join, the reference ground of high speed voltage comparator and the emitter of main switch join, and in-phase input end and the resistor network of high speed voltage comparator join.

4. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 1, is characterized in that, the in-phase input end of described high speed voltage comparator and the resistor network formation hysteresis loop comparator that joins.

5. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 4, is characterized in that the upper limit U of described hysteresis loop comparator _ref+provided by following formula:

$U_{\mathrm{ref}+}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\&times;V_{+}-\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}\&times;V_{-}---\left(1\right)$

Wherein, R ₁r ₂r ₃for forming the resistance of resistor network, V ₊for the positive supply voltage of high speed voltage comparator, V _-for the negative supply power voltage of high speed voltage comparator.

6. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 5, is characterized in that, hysteresis loop comparator lower limit U _ref-provided by following formula:

$U_{\mathrm{ref}-}=\frac{R_2\left|\right|R_3}{R_1+R_2\left|\right|R_3}\&times;V_{+}-(\frac{R_1\left|\right|R_3}{R_2+R_1\left|\right|R_3}+\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2})\&times;V_{-}---\left(2\right)$

Wherein, R ₁r ₂r ₃for forming the resistance of resistor network, V ₊for the positive supply voltage of high speed voltage comparator, V _-for the negative supply power voltage of high speed voltage comparator.

7. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 6, is characterized in that the upper limit U of hysteresis loop comparator _ref+hysteresis loop comparator lower limit U _ref-the return difference Δ U forming is:

$\mathrm{\&Delta;U}{=U}_{\mathrm{ref}+}-U_{\mathrm{ref}-}=\frac{R_1\left|\right|R_2}{R_3+R_1\left|\right|R_2}\&times;V_{-}---\left(3\right)$

Wherein, R ₁r ₂r ₃for forming the resistance of resistor network, V ₊for the positive supply voltage of high speed voltage comparator, V _-for the negative supply power voltage of high speed voltage comparator.

8. the self adaptation adjustable delay circuit for soft switch ZVT converter as claimed in claim 1, it is characterized in that, described master, auxiliary switch logic control circuit comprise first with door and second with, or door, dead band delay circuit and reset delay circuit, described first with input and the main switch zero cross detection circuit of door in the output of high speed voltage comparator join, first with door another input with second and output join, the second pwm signal of exporting with input of door and control circuit joins, second with door another input with by pwm signal the output after the delay circuit of dead band join, first with door output with or door an input join, or another input of door with join with the output of output after reset delay circuit of door second, or the output signal of door is as the control signal of main switch, second with the output of door as the control signal of auxiliary switch.