CN104022060A - Method for wafer back side alignment - Google Patents
Method for wafer back side alignment Download PDFInfo
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- CN104022060A CN104022060A CN201310066825.9A CN201310066825A CN104022060A CN 104022060 A CN104022060 A CN 104022060A CN 201310066825 A CN201310066825 A CN 201310066825A CN 104022060 A CN104022060 A CN 104022060A
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- wafer
- alignment mark
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- aiming
- wafer rear
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a method for wafer back side alignment. When back side alignment is performed, a wafer is etched from a second surface, thereby enabling a first alignment mark to be shown, and alignment marks in mirror symmetry are adopted on two main surfaces of the wafer, so that production of a back side alignment product can be realized under the circumstance of not changing single side alignment equipment, thereby improving the utilization rate of the equipment, and greatly reducing production costs.
Description
Technical field
The present invention relates to semiconductor fabrication process, be particularly related to the method that the wafer rear in back-illuminated type imaging sensing technology (backside image sensor technology) is aimed at, also can be applied in MEMS (micro electro mechanical system) (Micro-Electro Mechanical System, MEMS).
Background technology
Since 21 century, electronic product emerges in an endless stream, the performance of various electric terminals has obtained significant raising, for example current smart mobile phone high-quality picture rich in detail of same acquisition under low-light (level), this is to have applied backside-illuminated sensor, it has stronger photoperceptivity than front illuminated sensor, has obtained high-resolution collection effect.
Corresponding, the manufacture process of its chip is also different from tradition, at present, for back-illuminated type imaging sensor, be that first the one side to wafer (front) is processed, be reversed in afterwards another side (back side, or reverse side) and process, device is made on the tow sides of wafer, forms stereochemical structure.
For described stereochemical structure, its double-edged device is not arbitrarily to arrange to form, must make it obtain correct aligning just can come into force, for example, for a contact point (CT), it is to run through wafer, and this element must be aimed at accurately with other elements so, can produce in electrical contact.And these still have larger difference to traditional single-sided operation technique in equipment and formation technique, how for example positive component graphics aims at the component graphics at the back side is exactly a great problem.
The technique of aiming at for back, a kind of more conventional method comprises visible ray measurement and infrared survey at present, particularly, these methods can be summed up as the improvement of carrying out on the basis of original front aligning equipment, aim at by relevant apparatus being installed and then being obtained the back side in for example wafer platform bottom.But this method is in fact larger to the transformation of exposure bench, and expense is very high, in addition, due to the limitation of some equipment itself, such as spatial limitation etc., can not realize this repacking.
Summary of the invention
A kind of method that the object of the present invention is to provide wafer rear to aim at, aims to solve wafer rear of the prior art the problem that is subject to device-restrictive and be difficult for aligning.
For solving the problems of the technologies described above, the invention provides a kind of method that wafer rear is aimed at, comprising:
On the first surface of the first wafer, form ground floor device, and described the first wafer that reverses makes it to be incorporated on the second wafer, on the first surface of described the first wafer, be formed with the first alignment mark;
By described the first wafer, from second surface skiving to the first thickness, and the first alignment mark region described in etching, manifests described the first alignment mark;
Employing comprises that the light shield of the second alignment mark carries out photoetching;
Wherein, described the first alignment mark and the second alignment mark are mirror image symmetry.
Optionally, the method for aiming at for described wafer rear, adopt CMP technique by described the first wafer from second surface skiving to the first thickness.
Optionally, the method for aiming at for described wafer rear, described the first thickness is less than or equal to 30 μ m.
Optionally, the method for aiming at for described wafer rear, adopts the first alignment mark region described in wet-etching technology etching.
Optionally, the method for aiming at for described wafer rear, the area in the region of described etching is greater than the area of described the first alignment mark.
Optionally, the method for aiming at for described wafer rear, described the first alignment mark is made up of four groups of gratings, and wherein two groups of gratings are for laterally aiming at, and other two groups of gratings are for longitudinally aiming at.
Optionally, the method for aiming at for described wafer rear, described for laterally aiming at the grating of longitudinally aiming at and be spaced and be matrix pattern.
Optionally, the method for aiming at for described wafer rear, at least has two kinds of different pitches in described four groups of gratings.
Optionally, the method for aiming at for described wafer rear, described pitch is 2～6 μ m.
Compared with prior art, in the method for aiming at wafer rear provided by the invention, carrying out the back side on time wafer being carried out to etching from second surface, the first alignment mark is displayed, and two main surfaces at wafer have adopted the alignment mark that is mirror image symmetry, just can be in the situation that not changing one side aligning equipment, realize the production of back side aligning product, thereby improve the utilance of equipment, and greatly reduced production cost.
Brief description of the drawings
Fig. 1 is the left view of the first wafer in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 2 is the vertical view of the first wafer in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 3 be the embodiment of the present invention wafer rear aim at method in by the schematic diagram of the first wafer and the second wafer combination;
Fig. 4 is the schematic diagram of skiving the first wafer in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 5 carries out the left view of etching to the first wafer in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 6 carries out the vertical view of etching to the first wafer in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 7 forms the schematic diagram of second layer device in the wafer rear of the embodiment of the present invention method of aiming at;
Fig. 8 is the structural representation of the alignment mark of the embodiment of the present invention.
Embodiment
The method of wafer rear provided by the invention being aimed at below in conjunction with the drawings and specific embodiments is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, consider that the back side makes the alignment mark on first surface (front) invisible to the opaque of punctual wafer, so by wafer from the second surface (back side, or reverse side) carry out etching and just can make described alignment mark visible, after wafer inversion, alignment mark also changes thereupon, after etching, being seen alignment mark is mirror image symmetry, therefore, the alignment mark on front be set to its mirror-image structure just can, and this need be only slightly changing light shield.
Please refer to Fig. 1 and Fig. 2, the first wafer 1 is provided, described the first wafer 1 has first surface 10 and second surface 11, described first surface 10 and second surface 11 are the main surfaces of two of described the first wafer 1, namely what is often called obverse and reverse, on the first surface 10 of described the first wafer, form the first alignment mark 2, then, on the first surface 10 of the first wafer 1, form ground floor device 3.
It should be noted that, be only signal shown in figure, and described the first alignment mark 2 can be multiple conventionally, and it is positioned at Cutting Road or the center of described the first wafer 1, and the structure of device and distribution are determined according to different requirements.
Please refer to Fig. 3, described the first wafer 1 that reverses makes it to be incorporated on the second wafer 4, can adopt more conventional bonding method, and the present invention does not limit this.
Then, as shown in Figure 4, by described the first wafer from second surface 11 skiving to the first thickness, this is that thickness due to common wafer is for back-illuminated type imaging sensor or thicker, therefore the first thickness is 30 μ m left and right (being normally less than), conventionally can adopt the first wafer described in cmp (CMP) technique skiving, for CMP technique before the first wafer 1 distinguish, be designated as the first wafer 1' at this.
Please refer to Fig. 5 and Fig. 6, the first alignment mark 2 regions described in etching, described the first alignment mark 2 is manifested, concrete, to carry out etching from second surface 11, the region at 11 correspondences of described second surface the first alignment mark 2 places is etched away to a part, make this region become thinner from 30 μ m, make can demonstrate described the first alignment mark from second surface 11.The main material of considering described the first wafer is silicon, adopts wet-etching technology to carry out etching, forms a groove 5.Etching can be removed the silicon in first this region of wafer completely, because the first alignment mark 2 is to form in addition, therefore removes silicon and can not exert an influence to it, also can leave skim, can make described the first alignment mark 2 be revealed as good.Preferably, the area in the region of described etching is greater than the area of described the first alignment mark 2, and the groove 5 forming can contain described the first mark 2 completely, so that subsequent technique can normally be carried out.
Please refer to Fig. 7, adopt and comprise that the light shield of the second alignment mark carries out photoetching and other subsequent techniques, to form second layer device 6.Because back Alignment Process makes the first wafer upset, after upset, the first alignment mark is shown as its mirror image, conventionally alignment procedures adopts identical alignment mark to aim at, therefore, for described the second alignment mark can normally be played a role, in the present embodiment, the first alignment mark and the second alignment mark are set to be mirror image symmetrical structure, after the first wafer upset, just can accurately aim at the second alignment mark, this set only need to be arranged on the first alignment mark and the second alignment mark on different light shields, may be different between device between layers, and all need to be provided with alignment mark for the light shield of different layers, therefore, this set does not need extra expending yet.
Please refer to the schematic diagram of the first alignment mark shown in Fig. 8, described the first alignment mark is made up of four groups of gratings, wherein two groups of gratings are aimed at for horizontal (x direction), other two groups of gratings are for longitudinal (y direction) aligning, and the described grating for horizontal aligning and longitudinal aligning is spaced and is matrix pattern (outline is rectangle).In order to be adapted to kinds of processes needs, in described four groups of gratings, at least there are two kinds of different pitches, for example, preferred, described pitch is 2～6 μ m.In the present embodiment, at least comprise that live width (Line) is 1.15 μ m, 1.6 μ m and 2.6 μ m, gap (Space) is 1.15 μ m, 1.6 μ m and 2.8 μ m, pitch (Pitch) be live width and gap and.
Compared with prior art, in the method for aiming at wafer rear provided by the invention, carrying out the back side on time wafer being carried out to etching from second surface, the first alignment mark is displayed, and two main surfaces at wafer have adopted the alignment mark that is mirror image symmetry, just can be in the situation that not changing one side aligning equipment, realize the production of back side aligning product, thereby improve the utilance of equipment, and greatly reduced production cost.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to including these changes and modification.
Claims (9)
1. the method that wafer rear is aimed at, is characterized in that, comprising:
On the first surface of the first wafer, form ground floor device, and described the first wafer that reverses makes it to be incorporated on the second wafer, on the first surface of described the first wafer, be formed with the first alignment mark;
By described the first wafer, from second surface skiving to the first thickness, and the first alignment mark region described in etching, manifests described the first alignment mark;
Employing comprises that the light shield of the second alignment mark carries out photoetching;
Wherein, described the first alignment mark and the second alignment mark are mirror image symmetry.
2. the method that wafer rear as claimed in claim 1 is aimed at, is characterized in that, adopt CMP technique by described the first wafer from second surface skiving to the first thickness.
3. the method that wafer rear as claimed in claim 2 is aimed at, is characterized in that, described the first thickness is less than or equal to 30 μ m.
4. the method that wafer rear as claimed in claim 1 is aimed at, is characterized in that, adopts wet-etching technology from the first alignment mark region described in second surface etching.
5. the method that wafer rear as claimed in claim 4 is aimed at, is characterized in that, the area in the region of described etching is greater than the area of described the first alignment mark.
6. the method that wafer rear as claimed in claim 1 is aimed at, is characterized in that, described the first alignment mark is made up of four groups of gratings, and wherein two groups of gratings are for laterally aiming at, and other two groups of gratings are for longitudinally aiming at.
7. the method that wafer rear as claimed in claim 6 is aimed at, is characterized in that, described for laterally aiming at the grating of longitudinally aiming at and be spaced and be matrix pattern.
8. the method that wafer rear as claimed in claim 6 is aimed at, is characterized in that at least having two kinds of different pitches in described four groups of gratings.
9. the method that wafer rear as claimed in claim 8 is aimed at, is characterized in that, described pitch is 2～6 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310066825.9A CN104022060A (en) | 2013-03-01 | 2013-03-01 | Method for wafer back side alignment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310066825.9A CN104022060A (en) | 2013-03-01 | 2013-03-01 | Method for wafer back side alignment |
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| Publication Number | Publication Date |
|---|---|
| CN104022060A true CN104022060A (en) | 2014-09-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201310066825.9A Pending CN104022060A (en) | 2013-03-01 | 2013-03-01 | Method for wafer back side alignment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687759A (en) * | 2018-07-06 | 2020-01-14 | 上海微电子装备（集团）股份有限公司 | Mask plate and bonding alignment method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338960A (en) * | 2000-05-26 | 2001-12-07 | Hitachi Ltd | Semiconductor device, semiconductor device measuring equipment and semiconductor device manufacturing method |
| CN101279710A (en) * | 2007-04-06 | 2008-10-08 | 台湾积体电路制造股份有限公司 | Method for judging wafer backside alignment overlay accuracy and wafer thereof |
| CN101452912A (en) * | 2007-12-06 | 2009-06-10 | 台湾积体电路制造股份有限公司 | Alignment for backside illumination sensor |
| CN102386168A (en) * | 2010-09-02 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Alignment marks in substrate having through-substrate via |
| WO2012089043A1 (en) * | 2010-12-28 | 2012-07-05 | 上海微电子装备有限公司 | Backside registration apparatus and method |
-
2013
- 2013-03-01 CN CN201310066825.9A patent/CN104022060A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001338960A (en) * | 2000-05-26 | 2001-12-07 | Hitachi Ltd | Semiconductor device, semiconductor device measuring equipment and semiconductor device manufacturing method |
| CN101279710A (en) * | 2007-04-06 | 2008-10-08 | 台湾积体电路制造股份有限公司 | Method for judging wafer backside alignment overlay accuracy and wafer thereof |
| CN101452912A (en) * | 2007-12-06 | 2009-06-10 | 台湾积体电路制造股份有限公司 | Alignment for backside illumination sensor |
| CN102386168A (en) * | 2010-09-02 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Alignment marks in substrate having through-substrate via |
| WO2012089043A1 (en) * | 2010-12-28 | 2012-07-05 | 上海微电子装备有限公司 | Backside registration apparatus and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110687759A (en) * | 2018-07-06 | 2020-01-14 | 上海微电子装备（集团）股份有限公司 | Mask plate and bonding alignment method |
| CN110687759B (en) * | 2018-07-06 | 2021-04-02 | 上海微电子装备（集团）股份有限公司 | Mask plate and bonding alignment method |
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Application publication date: 20140903 |
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