CN104021097A - Data transmission method and device and direct memory access - Google Patents
Data transmission method and device and direct memory access Download PDFInfo
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- CN104021097A CN104021097A CN201310066641.2A CN201310066641A CN104021097A CN 104021097 A CN104021097 A CN 104021097A CN 201310066641 A CN201310066641 A CN 201310066641A CN 104021097 A CN104021097 A CN 104021097A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The invention discloses a data transmission method and device and DMA. The method comprises the steps that the DMA receives data of a source end through a first physical bus, and the width of the first physical bus is equal to the data width of the data of the source end; the DMA converts the data of the source end into data of a destination end, and the data width of the data of the destination end corresponds to the destination end; the DMA sends the data of the destination end to the destination end through a second physical bus, and the data width of the second physical bus is equal to that of the data of the destination end. Through the data transmission method and device and the DMA, the resource utilization rate with the DMA for data transmission is improved.
Description
Technical field
The present invention relates to the communications field, in particular to a kind of data transmission method, device and direct memory access (DMA) (Direct Memory Access, referred to as DMA).
Background technology
DMA controller technology is widely used in processor and SOC (system on a chip) (System-On-a-Chip, referred to as SoC) system.Its function is to realize the high speed data transfer between I/O interface and storer.For digital signal processor (Digital Signal Processor, referred to as DSP), dma module can be the same as with processor core Master access DSP external storage resources and internal storage, make the SoC storer of DSP outside and program storage (the Program Memory of DSP inside, referred to as PM), data-carrier store (Data Memory, referred to as DM) between can carry out fast data carrying, and do not need DSP core to use its internal register to carry out inefficient data relay.The DMA also parameter configuration that can receive DSP core the same as other peripheral hardwares carries out data carrying, and during DMA carrying, DSP endorses to select to do other thing.That is, DMA is specifically designed to the transmission of big data quantity, and DMA has done the thing that DSP core is bad on the one hand, and DSP endorses to leave to do other thing on the other hand.
In correlation technique, the DMA technology of DSP often contains a plurality of passages, and advantage is to realize parallel transmission, and shortcoming is that resource utilization is lower, for example: the hardware resource taking is more.If once transmission only needs a source and a destination, obvious multichannel design resource utilization is not high, and except a passage job, other passages will be in idle state.
The lower problem of resource utilization of carrying out data transmission for DMA in correlation technique, not yet proposes effective solution at present.
Summary of the invention
The lower problem of resource utilization of carrying out data transmission for DMA in correlation technique, the invention provides a kind of data transmission method, device and direct memory access (DMA), at least to address this problem.
According to an aspect of the present invention, provide a kind of DMA data transmission method, having comprised: DMA has received the data of source by the first physical bus, the width of wherein said the first physical bus is identical with the data width of the data of described source; Described DMA is converted to the data of described source the data of destination, and the data width of the data of the wherein said destination data width corresponding with described destination is identical; Described DMA sends to described destination by the second physical bus by the data of described destination, and wherein, the data width of described the second physical bus is identical with the data width of the data of described destination.
Preferably, before described DMA is converted to the data of destination by the data of described source, also comprise: described DMA is by the data of source described in bi-directional synchronization first-in first-out FIFO buffer memory.
Preferably, the data that described DMA is converted to destination by the data of described source comprise: described DMA selects a predetermined number read data in described bi-directional synchronization FIFO; Described DMA aligns described read data by the processing logic that do not line up on this DMA according to the data width of the data of described destination, obtain the data of described destination.
Preferably, described source is SOC storer (Soc Memory, referred to as SM), and described destination is program storage PM; Described source is described SM, and described destination is data-carrier store DM; Described source is described DM, and described destination is described SM.
Preferably, the described data width between described DMA and SM is 64 bits; Described data width between described DMA and described PM is 128 bits; Described data width between described DMA and described DM is 256 bits.
According to a further aspect in the invention, a kind of DMA data transmission device is provided, has been positioned at DMA, having comprised: receiver module, for receive the data of source by the first physical bus, the width of wherein said the first physical bus is identical with the data width of the data of described source; Modular converter, for the data of described source being converted to the data of destination, the data width of the data of wherein said destination is the data width that described destination is corresponding;
Sending module, for the data of described destination being sent to described destination by the second physical bus, wherein, the data width of described the second physical bus is identical with the data width of the data of described destination.
Preferably, said apparatus also comprises: cache module, and for by the data of source described in bi-directional synchronization first-in first-out FIFO buffer memory.
Preferably, described modular converter comprises: select module, for select a predetermined number read data at described bi-directional synchronization FIFO; Processing module, for by lining up processing logic, described read data not being alignd according to the data width of the data of described destination, obtains the data of described destination.
Preferably, described source is SM, and described destination is program storage PM;
Described source is described SM, and described destination is data-carrier store DM;
Described source is described DM, and described destination is described SM.
Preferably, the described data width between described DMA and SM is 64 bits.
Described data width between described DMA and described PM is 128 bits;
Described data width between described DMA and described DM is 256 bits.
According to another aspect of the invention, also provide a kind of DMA, having comprised: above-mentioned DMA data transmission device.
By the present invention, adopt DMA by the first physical bus, to receive the data of source, wherein the data width of the width of this first physical bus and the data of source is identical; DMA is converted to the data of source the data of destination, and wherein the data width of the data of destination is the data width that destination is corresponding; DMA sends to destination by the second physical bus by the data of destination, wherein, the data width of the second physical bus is identical with the data width of the data of destination, solved DMA in correlation technique and carried out the lower problem of resource utilization of data transmission, and then reached and improve the effect that DMA carries out data transmission efficiency.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is according to the process flow diagram of the data transmission method of the embodiment of the present invention;
Fig. 2 is according to the structured flowchart of the data transmission device of the embodiment of the present invention;
Fig. 3 is the preferred structured flowchart according to the data transmission device of the embodiment of the present invention;
Fig. 4 is according to the structured flowchart of the DMA of the embodiment of the present invention;
Fig. 5 is DMA structured flowchart according to the preferred embodiment of the invention;
Fig. 6 is according to the schematic diagram of the realization of the two-way FIFO of 5 * 32-bit of the embodiment of the present invention;
Fig. 7 (a) is the schematic diagram one that DM address is the processing while aliging address (DM address is 0) and non-alignment address (DM address is 2) of writing according to the embodiment of the present invention;
Fig. 7 (b) is the schematic diagram two that DM address is the processing while aliging address (DM address is 0) and non-alignment address (DM address is 2) of writing according to the embodiment of the present invention;
Fig. 8 be according to the embodiment of the present invention write DM time address do not line up the schematic diagram of processing MUX;
Fig. 9 be according to the embodiment of the present invention read DM time address do not line up the schematic diagram of processing MUX;
Figure 10 is according to the schematic diagram of the SM read-write steering logic state machine of the embodiment of the present invention; And
Figure 11 is according to the schematic diagram of the PM/DM read-write steering logic state machine of the embodiment of the present invention.
Embodiment
Hereinafter with reference to accompanying drawing, also describe the present invention in detail in conjunction with the embodiments.It should be noted that, in the situation that not conflicting, embodiment and the feature in embodiment in the application can combine mutually.
The DMA technology of DSP in correlation technique, the same bit wide of the general employing of physical bus of source and destination.Mathematical logic width is sometimes inconsistent with bus physical width, when mathematical logic width is less than bus physical width, has wasted bus hardware resource; When mathematical logic width is greater than bus physical width, not only affect transfer efficiency, also increased design complexity.In this application, adopt direct memory access by the first physical bus, to receive the data of source, wherein the data width of the width of the first physical bus and the data of source is identical; DMA is converted to the data of source the data of destination, and wherein the data width of the data of the destination data width corresponding with destination is identical; DMA sends to destination by the second physical bus by the data of destination, and wherein, the data width of the second physical bus is identical with the data width of the data of destination.By the method, realize according to different transmission mode separated feature in time, only adopt a transmission channel to realize different transfer functions; DMA physical bus width design one-tenth and data width is consistent (for example: between DMA and SM, data width is 64bit, between DMA and PM, data width is 128bit, between DMA and DM, data width is 256bit), adopt the inconsistent of many groups of (multi-bank) FIFO buffering sources and destination highway width, solve DMA in correlation technique and carried out the lower problem of resource utilization of data transmission, thereby reached, improved the effect that DMA carries out data transmission efficiency.
The present embodiment provides a kind of data transmission method, and Fig. 1 is according to the process flow diagram of the data transmission method of the embodiment of the present invention, comprises that following step S102 is to step S106.
Step S102:DMA receives the data of source by the first physical bus, wherein the data width of the width of this first physical bus and the data of this source is identical.
Step S104:DMA is converted to the data of this source the data of destination, and wherein the data width of the data of this destination data width corresponding with this destination is identical.
Step S106:DMA sends to described destination by the second physical bus by the data of this destination, and wherein, the data width of this second physical bus is identical with the data width of the data of this destination.
Pass through above-mentioned steps, DMA receives the data of source by the first identical physical bus of the data width of the data with source, and the data that receive are converted to the destination data identical with the data width of destination, and send by the second identical physical bus of the data width of the data with destination, realized the data transmission of carrying out the data of different bit wides by a passage, solved DMA in correlation technique carry out the resource utilization of data transmission lower problem, thereby reached, improve the effect that DMA carries out data transmission efficiency.
As an embodiment preferably, before DMA is converted to the data of destination by the data of described source, this DMA can pass through bi-directional synchronization first-in first-out (First In First Out, referred to as FIFO) data of this source of buffer memory, by the data of buffer memory source, can improve the follow-up efficiency of changing.
When implementing, DMA can be converted to the data of source by numerous embodiments the data of destination, for example: DMA selects a predetermined number read data in described bi-directional synchronization FIFO; DMA aligns read data by the processing logic that do not line up on this DMA according to the data width of the data of described destination, obtain the data of destination.This preferred implementation is relatively easy to realize.
When implementing, corresponding to several data transmission, source and destination can be one of following combination:
Source is SM, and destination is program storage (PM);
Source is SM, and destination is data-carrier store (DM);
Source is DM, and destination is SM.
Preferably, the data width between above-mentioned source and destination can be: the data width between DMA and SM is 64 bits; Data width between DMA and PM is 128 bits; Data width between DMA and DM is 256 bits.
It should be noted that, in the step shown in the process flow diagram of accompanying drawing, can in the computer system such as one group of computer executable instructions, carry out, and, although there is shown logical order in flow process, but in some cases, can carry out shown or described step with the order being different from herein.
In another embodiment, also provide a kind of data transmission software, the technical scheme that this software is described for carrying out above-described embodiment and preferred embodiment.
In another embodiment, also provide a kind of storage medium, stored above-mentioned data transmission software in this storage medium, this storage medium includes but not limited to: CD, floppy disk, hard disk, scratch pad memory etc.
The embodiment of the present invention also provides a kind of data transmission device, be positioned at DMA, this data transmission device can be for realizing above-mentioned data transmission method and preferred implementation, carried out explanation, repeat no more, below the module relating in this data transmission device is described.As used below, the combination of software and/or the hardware of predetermined function can be realized in term " module ".Although the described system and method for following examples is preferably realized with software, hardware, or the realization of the combination of software and hardware also may and be conceived.
Fig. 2 is according to the structured flowchart of the data transmission device of the embodiment of the present invention, and as shown in Figure 2, this device comprises: receiver module 22, modular converter 24 and sending module 26, be described in detail said structure below.
Receiver module 22, for receive the data of source by the first physical bus, wherein the data width of the width of this first physical bus and the data of this source is identical; Modular converter 24, is connected to receiver module 22, is converted to the data of destination for the data of source that receiver module 22 is received, and wherein the data width of the data of the destination data width corresponding with this destination is identical; Sending module 26, is connected to modular converter 24, for the data of the destination that modular converter 24 is converted to by the second physical bus, sends to this destination, and wherein, the data width of this second physical bus is identical with the data width of the data of this destination.
Fig. 3 is the preferred structured flowchart according to the data transmission device of the embodiment of the present invention, and as shown in Figure 3, this device also comprises: cache module 32; Preferably, modular converter 24 comprises ratio: select module 242 and processing module 244, below said structure is described in detail.
Data transmission device also comprises: cache module 32, is connected to modular converter 24, for by the data of source described in bi-directional synchronization first-in first-out FIFO buffer memory.
Preferably, modular converter 24 comprises: select module 242, for select a predetermined number read data at described bi-directional synchronization FIFO; Processing module 244, is connected to and selects module 242, for by lining up processing logic, the read data of selecting module 242 to select not being alignd according to the data width of the data of destination, obtains the data of destination.
Preferably, source is SM, and destination is program storage (PM);
Source is SM, and destination is data-carrier store (DM);
Source is DM, and destination is SM.
Preferably, the described data width between DMA and SM is 64 bits;
Described data width between DMA and PM is 128 bits;
Described data width between DMA and DM is 256 bits.
The present embodiment provides a kind of DMA, and Fig. 4 is according to the structured flowchart of the DMA of the embodiment of the present invention, and as shown in Figure 4, this DMA comprises the data transmission device 2 of above-described embodiment, and the structure of this data transmission device 2 as shown in Figures 2 and 3, does not repeat them here.
Below in conjunction with preferred embodiment, describe, following preferred embodiment combines above-described embodiment and preferred implementation.
Preferred embodiment one
This preferred embodiment provides a kind of improved DMA to carry out the method for data transmission.According to different transmission mode separated feature in time, only adopt a transmission channel to realize different transfer functions; DMA physical bus width design one-tenth and data width is consistent (for example: between DMA and SM, data width is 64bit, between DMA and PM, data width is 128bit, between DMA and DM, data width is 256bit), adopt the inconsistent of many groups of (multi-band) FIFO buffering sources and destination highway width.
In the present embodiment, the executable function of DMA comprises: SM is to the director data carrying of PM, and SM carries to the data of SM to data carrying and the DM of DM.This DMA can be configured and be accessed by ARM or DSP core.
Preferably, DMA comprises as follows:
The bi-directional synchronization FIFO of (1) 8 32 bit width, for cushioning the inconsistent of source and destination memory data bit wide.
(2) SM MUX, selects 2 read datas of 8 FIFO during to SM data transmission for DM.
(3) PM MUX selects 4 read datas of 8 FIFO when PM transmits for SM.
(4) write DM address and do not line up processing logic, for SM during to DM data transmission by 256 Bit datas of reading from 8 FIFO according to DM address (take 32 bits as unit) automatic aligning.
(5) read DM address and do not line up processing logic, for DM during to SM data transmission by 256 Bit datas of reading from DM according to DM address automatic aligning.
(6) dma control logic and register, be used for accepting external reference and control data stream, wherein SM read-write steering logic is controlled SM and 8 FIFO burst with AXI bus burst() mode carries out data transmission, and the data that PM/DM read-write steering logic is controlled 8 FIFO and PM/DM transmit.DMA configuration register comprises ext_addr, int_addr and size_ctrl_start, and wherein ext_addr and int_addr indicate respectively SM address and PM/DM address, and size, ctrl and start represent respectively to transmit data volume, transmission mode and start bit.
In a preferred embodiment, DMA carries out following steps S302 to step S306.
Step S302:DSP core or ARM configuration DMA register, arrange the start address of DMA access SM, PM or DM and data volume, transmission mode and the start bit of DMA carrying.Start bit place register needs last configuration.
Step S304: after start bit is set high, DMA starts carrying work.The read-write requests that SM and PM/DM both sides respectively have a state machine to be responsible for respectively SM and PM/DM is initiated.Two end state machines respectively have a size register pair residue transmission quantity to count.Size register can corresponding successively decreasing after a read-write requests success.Whether two end state machines initiate read-write requests according to the residue size of size and the full Determines of the sky of DMAFIFO.
Step S306: by 0 o'clock, read-write requests was no longer initiated at two ends at size register meter, and the porter of DMA completes, and start register was become to 0 simultaneously.
By the technical scheme of this preferred embodiment, DMA supports the data transmission between the storer of different pieces of information bit wide, and the reading of source can be carried out with writing of destination simultaneously, and the efficient AXI bus of the read-write support burst of SM transmits, and the read-write support of DM is asked continuously.Above feature has significantly improved the transfer efficiency of DMA.This DMA is only used a passage to realize the transmitted in both directions between SM and DM, the register resources of FIFO has been carried out multiplexing, has saved hardware resource.The data transmission (only for DM, PM is 128 bits) that this DMA support minimum data amount is 32 bits and support automatically by alignment of data, facilitate software debugging according to DM address.
Preferred embodiment two
This preferred embodiment provides a kind of DMA, routine DMA as shown in Figure 5, and the present embodiment is described in detail the composition of this DMA.
In order to realize the non-alignment address date access of DM, DMAFIFO is divided into 8 groups (bank), and each group (bank) is that 32bit is wide.Fig. 6 is according to the schematic diagram of the realization of the two-way FIFO of 5 * 32-bit of the embodiment of the present invention, the realization of each 32bit FIFO as shown in Figure 6.This FIFO degree of depth is 5, than a burst-16 data volume bigger (when the degree of depth is 4, DMAFIFO size is 32 * 4 * 8bit=64 * 16bit=1024bit).This FIFO can realize transmitted in both directions, and 5 32-bit registers are multiplexing when transmitted in both directions.Transmission direction is by dir signal controlling, and mem distinguishes PM and DM, and dir and mem signal determine transmission mode (SM2PM, SM2DM, DM2SM) jointly." _ d " postfix notation descending (download) direction, i.e. SM2PM or SM2DM in figure; " _ u " postfix notation up (upload) direction, i.e. DM2SM.Preferably, read/write requests success, need to initiate a new request, but data that read from DMA FIFO or write may be than late several cycles of request signal, so also not renewal of the full state of the sky of DMAFIFO when need to initiate new request toward the data of DMA FIFO.By the time empty full state determines after upgrading that whether initiating new request can affect data transmission efficiency again.In FIFO inside, have two counter register: num and num2, they are for counting the 32-bit data amount check being stored in FIFO.Num and num2 may not be real data amount check, and they are used as the condition of initiating new request.When check initiating the full state of sky of new request, there is no need to wait until data corresponding to previous request read and write completely complete after.The definition of num and num2 respectively as shown in Table 1 and Table 2, wherein burst16_req represents 1 successful burst-16 request or first the successful burst request that (occurs this situation when running into 4KB border) when a burst-16 is splitted into two little burst, and new_dm_req represents to reply the request of successful DMA access DM.
The definition of num in the two-way FIFO of table 15 * 32-bit
It should be noted that, as shown in table 1, the counting of num register is divided into SM2PM, SM2DM, tri-kinds of situations of DM2SM.Wherein, in order earlier to initiate request, the counting of the num of SM2DM and two kinds of transmission modes of DM2SM is not used real read-write enable signal completely.For SM2DM transmission mode, when really writing, enable (wen_d) when high; Counter adds 1, and when new_dm_req is while being high, counter subtracts 1.For DM2SM transmission mode, when really reading to enable (ren_u) when high; Counter subtracts 1, and when new_dm_req is while being high, counter adds 1.
The definition of num2 in the two-way FIFO of table 25 * 32-bit
It should be noted that, as shown in table 2, the counting of num2 register is divided into descending and up two kinds of situations.In order earlier to initiate request, the counting of num2 is not used real read-write enable signal completely.For down direction, when burst16_req is while being high, counter adds 4; When really reading to enable (ren_d) when high, counter subtracts 1.For up direction, when burst16_req is while being high, counter subtracts 4; When really writing, enable (wen_u) when high, counter subtracts 1.
Due to the needs of burst-16, the full signal of the sky in FIFO left side has special judgment mechanism.For down direction, if num2>1, full_d is set to 1, represents that the 32-bit data amount check that FIFO can receive is less than 4.So when the full_d of 8 FIFO signal is all 0, DMA can receive the data volume of a burst-16.For up direction, if num2<4, empty_u is set to 1, represents that the 32-bit data amount check that is stored in FIFO is less than 4.So when the empty_u of 8 FIFO is 0, DMA can send a burst-16 and request.
On the right side of FIFO, the full signal of these two skies of empty_d and full_u is used conventional judgment mechanism, and num equals at 0 o'clock, and empty_d is high; Num equals at 5 o'clock, and full_u is high.The definition of full_d, empty_d, full_u and empty_u is as shown in table 3.
The empty full signal definition of table 3
| Signal | Definition |
| full_d | num2=2,3,4,5 |
| empty_u | num2=0,1,2,3 |
| empty_d | num=0 |
| full_u | num=5 |
| empty_d_one | num=0,1 |
| full_u_four | num=4,5 |
On the right side of FIFO, except empty_d and full_u signal, also have other one group of empty full signal: empty_d_one and full_u_four(table 3).These two signals are for when DMA connected reference DM.For example, when transferring data to DM from DMA FIFO, if at current period, num=1 and request signal req=1, and this request by successful respond, num will become 0 in the next cycle so, were it not for the words that data are write into FIFO.At current period, can not be using empty_d signal as the condition that judges whether to initiate in next week new request, because num just can upgrade in next week.If num=0 or 1 is thought to empty, this problem can solve.
SM MUX is one 4 and selects 1MUX.When SM is carried out to burst write operation, reading DMA FIFO is according to { fifo_1, fifo0}, { fifo_3, fifo_2}, { fifo_5, fifo_4}, { fifo_7, the mode of fifo_6} poll conducts interviews.
PM MUX is one 2 and selects 1MUX.When PM is carried out to write operation, reading DMA FIFO according to fifo_3, fifo_2, fifo_1, fifo_0}, fifo_7, fifo6, fifo_5, the mode of fifo_4} poll conducts interviews.
Because the data width of read-write DM is 256bit, when DM address (32bit is unit) is 8 multiple when (comprising 0), this access is the access of address align, as shown in Figure 7 (a).When DM address is not 8 multiple, DM address is the address of non-alignment, at this moment needs data to do special processing.As shown in Figure 7 (b) shows, when writing DM start address and be 2, writing for the first time DM only need be by minimum 6 32bit of current data, and c_data0, to c_data5, writes into DM.Which 32bit of the mask signal controlling DM of 8bit need to write.Write for the second time the fashionable 256bit data that the p_data6 of buffer memory, p_data7 and the c_data0 that refreshes are spliced to c_data5 and all write DM.After writing mode several times with identical for the second time.The size that transmits data volume is depended in last writing.In figure, if transmit the multiple that data volume is 256bit, write for the last time 2 32bit, because write for the first time 6 32bit.The task of data buffer storage is completed by a register, and c_data and p_data synchronously upgrade.
When reading DM, with to write DM similar, if read DM address non-alignment, such as being 2 o'clock, need for the first time the read data p_data2 of buffer memory all to write DMAFIFO to p_data7 and the read data c_data0 refreshing, the 256bit data that c_data1 is spliced.After write several times with identical for the first time.Write for the last time and also depend on the size that transmits data volume.Equally, need the data that register buffer memory reads back from DM, readback data c_data and data cached p_data synchronously upgrade.Register for cache read data can be multiplexing with the register of cache writing data.
Fig. 8 be according to the embodiment of the present invention write DM time address do not line up the schematic diagram of processing MUX, as shown in Figure 8, it is the selection to c_data and p_data in 0 to 7 o'clock that the MUX of Fig. 8 has provided the low 3bit in DM address while writing DM.When the low 3bit in DM address is 0, directly select c_data as the output of MUX; When the low 3bit in DM address is not 0, select a part of c_data and a part of p_data to be spliced into 256bit.
Fig. 9 be according to the embodiment of the present invention read DM time address do not line up the schematic diagram of processing MUX, as shown in Figure 9, it is the selection to c_data and p_data in 0 to 7 o'clock that the MUX of Fig. 9 has provided the low 3bit in DM address while reading DM.When the low 3bit in DM address is 0, directly select c_data as the output of MUX; When the low 3bit in DM address is not 0, select a part of c_data and a part of p_data to be spliced into 256bit.
Figure 10 is according to the schematic diagram of the SM read-write steering logic state machine of the embodiment of the present invention, and as shown in figure 10, Figure 10 is SM read-write steering logic state machine.There are three state: IDLE_BURST, REQ_BURST and WAIT_BURST.IDLE_BURST is default conditions; Under REQ_BURST, DMA reads or writes request signal for high to AXI matrix; Under WAIT_BURST state, wait for burst request next time or wait for the IDLE_BURST state of getting back to.Under IDLE_BURST state, when start is high, size is not 0, and DMA FIFO sky is when completely meet the demands, and enters REQ_BURST state.Under REQ state, when request with after answer signal shakes hands successfully, enter WAIT_BURST state, while scheduler (addr), size, burst length(len) etc. signal, request signal req is cleared.Under WAIT_BURST state, when size is not 0 and when meeting DMA FIFO sky and completely requiring, reenter REQ_BURST state and ask next time; When size is 0, enter IDLE_BURST state.
Figure 11 is according to the schematic diagram of the PM/DM read-write steering logic state machine of the embodiment of the present invention, as shown in figure 11, and PM/DM read-write steering logic state machine.There are three state: IDLE_256, REQ_256 and WAIT_256.IDLE_256 is default conditions; Under REQ_256 state, DMA reads or writes request signal for high to DM moderator; Under WAIT_256 state, wait for that next time DM read-write requests or wait get back to IDLE256 state.Under IDLE256 state, when answer signal aready is high (aready is defaulted as height), start be height, and size is not 0, and DMA FIFO sky is when completely meet the demands, and enters REQ_256 state.Under REQ_256 state, when unsuccessful when shaking hands (aready is 0), continue to keep REQ state; When shaking hands successfully, size is greater than 8, and DMA FIFO sky is while completely meeting the demands (using empty_d_one above-mentioned or full_u_four), initiates next request, simultaneously address, data and size signal update; When shaking hands successfully, size be less than or equal to 8 or size to be greater than 8 single DMA FIFO empty full while not meeting the demands, enter WAIT_256 state, simultaneously address, data and size signal update.Under WAIT_256 state, when size is not 0 and when meeting DMA FIFO sky and completely requiring, reenter REQ_256 state and ask next time; When size is 0 and areay while being high, enter IDLE_256 state.When two state machines all enter IDLE state, the zero clearing of start signal, some other critical registers is got back to initial state simultaneously.
Above to the description of Figure 11 state machine for access DM.Same this state machine that uses during access PM.Difference is that PM access does not need continuous access, does not have REQ_256 to twice connected reference of REQ_256.Access PM only has write operation, and PM address width is 128bit, need to judge in turn the spacing wave of fifo_0 to fifo_3 and fifo_4 to fifo_7.
By above-described embodiment, a kind of data transmission method, device and direct memory access (DMA) are provided, according to different transmission mode separated feature in time, only adopt a transmission channel to realize different transfer functions, DMA physical bus width design one-tenth and data width is consistent (for example: between DMA and SM, data width is 64bit, between DMA and PM, data width is 128bit, between DMA and DM, data width is 256bit), adopt the inconsistent of many group bank FIFO buffering sources and destination highway width, solved the resource utilization lower problem that DMA in correlation technique carries out data transmission, thereby reached and improved the effect that DMA carries out data transmission efficiency and it should be noted that, these technique effects are not that above-mentioned all embodiments have, some technique effect is that some preferred implementation just can obtain.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby they can be stored in memory storage and be carried out by calculation element, or they are made into respectively to each integrated circuit modules, or a plurality of modules in them or step are made into single integrated circuit module to be realized.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (11)
1. a data transmission method, is characterized in that comprising:
Direct memory access receives the data of source by the first physical bus, the width of wherein said the first physical bus is identical with the data width of the data of described source;
Described DMA is converted to the data of described source the data of destination, and the data width of the data of the wherein said destination data width corresponding with described destination is identical;
Described DMA sends to described destination by the second physical bus by the data of described destination, and wherein, the data width of described the second physical bus is identical with the data width of the data of described destination.
2. method according to claim 1, is characterized in that, before described DMA is converted to the data of destination by the data of described source, also comprises:
Described DMA is by the data of source described in bi-directional synchronization first-in first-out FIFO buffer memory.
3. method according to claim 2, is characterized in that, the data that described DMA is converted to destination by the data of described source comprise:
Described DMA selects a predetermined number read data in described bi-directional synchronization FIFO;
Described DMA aligns described read data by the processing logic that do not line up on this DMA according to the data width of the data of described destination, obtain the data of described destination.
4. according to the method in any one of claims 1 to 3, it is characterized in that,
Described source is SM, and described destination is program storage PM;
Described source is described SM, and described destination is data-carrier store DM;
Described source is described DM, and described destination is described SM.
5. method according to claim 4, is characterized in that,
Described data width between described DMA and SM is 64 bits;
Described data width between described DMA and described PM is 128 bits;
Described data width between described DMA and described DM is 256 bits.
6. a data transmission device, is positioned at direct memory access, it is characterized in that comprising:
Receiver module, for receive the data of source by the first physical bus, the width of wherein said the first physical bus is identical with the data width of the data of described source;
Modular converter, for the data of described source being converted to the data of destination, the data width of the data of the wherein said destination data width corresponding with described destination is identical;
Sending module, for the data of described destination being sent to described destination by the second physical bus, wherein, the data width of described the second physical bus is identical with the data width of the data of described destination.
7. device according to claim 6, is characterized in that, also comprises:
Cache module, for by the data of source described in bi-directional synchronization first-in first-out FIFO buffer memory.
8. device according to claim 7, is characterized in that, described modular converter comprises:
Select module, for select a predetermined number read data at described bi-directional synchronization FIFO;
Processing module, for by lining up processing logic, described read data not being alignd according to the data width of the data of described destination, obtains the data of described destination.
9. according to the device described in any one in claim 6 to 8, it is characterized in that,
Described source is SM, and described destination is program storage PM;
Described source is described SM, and described destination is data-carrier store DM;
Described source is described DM, and described destination is described SM.
10. device according to claim 9, is characterized in that,
Described data width between described DMA and SM is 64 bits;
Described data width between described DMA and described PM is 128 bits;
Described data width between described DMA and described DM is 256 bits.
11. 1 kinds of direct memory access, is characterized in that comprising: the data transmission device in claim 6 to 10 described in any one.
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| PCT/CN2013/082369 WO2014131273A1 (en) | 2013-03-01 | 2013-08-27 | Data transmission method and apparatus, and direct memory access |
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