CN104020981B - A kind of central processing unit and its command processing method - Google Patents
A kind of central processing unit and its command processing method Download PDFInfo
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- CN104020981B CN104020981B CN201410276522.4A CN201410276522A CN104020981B CN 104020981 B CN104020981 B CN 104020981B CN 201410276522 A CN201410276522 A CN 201410276522A CN 104020981 B CN104020981 B CN 104020981B
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Abstract
The present invention provides a kind of CPU and its command processing method, and the CPU includes：Instruction buffer selector；Two instruction buffer units；Decoding unit is used for according to the instruction generation instruction anticipation signal decoded；Instruction anticipation signal is used to indicate whether execution unit will to perform jump instruction next time；Instruction buffer selector is used for when execution unit will perform jump instruction to the instruction anticipation signal designation received next time, another buffered instructions unit is switched to from the instruction buffer unit currently selected, controls the buffered instructions unit being switched to be read since the position of the program storage pointed by the jump instruction and instructs and preserve；When redirecting, read instruction from the buffered instructions unit being switched to and be sent to decoding unit；When the implementing result of jump instruction is not redirect, switches back into selected buffered instructions unit before switching and continue to read instruction.The present invention can make former CPU CPU kernel speed is lifted 25% on the basis of not area increased.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a central processing unit and an instruction processing method thereof.
Background
In recent years, with the rapid development of the field of integrated circuits, the application range of the traditional and small-sized independently developed 16-bit CPU (central processing unit) is more and more extensive, and the price of the CPU is also required to be lower and lower. However, 16-bit CPU core with high operation speed and low cost is an urgent need in the market. Particularly in low and mid-end integrated circuit products, the price of using high-end chip cores may even affect the profit margin of the overall product. For example: the ARM corporation product in the united states has its CPU dominated by both performance and area volume, but is expensive. Especially for low and medium-end products, the profit and the sales of the products are seriously influenced. At present, 16-bit CPU with low price and slow operation speed is adopted in low-end and middle-end integrated circuit products in the market, and the improvement of the product quality is also restricted by the CPU. A novel 16-bit CPU design with low price and high operation speed is expected in the high-speed development of the field of future integrated circuits.
The traditional 16-bit CPU core design is as shown in fig. 1, and the core structure of fig. 1 includes: the system comprises a program bus interface unit, an instruction buffer unit, a decoding unit, an execution unit and a series of auxiliary units. When the CPU works, reading a program instruction needing to be executed from a program memory; the instruction is stored into an instruction buffer unit through a program bus interface; the instruction buffer unit sends the instruction to be executed to the decoding unit; the decoding unit analyzes a series of control signals and sends the control signals to the execution unit for execution.
The core operation process of the conventional 16-bit CPU is shown in fig. 2, and a series of control signals are obtained from the decoding unit, and these control signals include: operation operands A and B and operation type; the execution unit performs different operation operations on the operation operands A and B according to different operation types. The operation types comprise: data transfer type operations, arithmetic logic type operations, boolean type operations, and control transfer type operations.
The result after the operation includes: updates to registers, updates to associated memory, instruction jumps, and no-op operations. When instruction jump occurs, the execution unit informs the instruction buffer unit to carry out the operation of clearing the instruction buffer; after the emptying is finished, the instruction buffer unit will request to read the program instruction from the program memory again according to the position indicated by the instruction jump result; when an instruction clears and re-requests a program instruction to be read from the program memory, the CPU consumes at least 2 time units. During the work periods of clearing, re-requesting, re-reading programs and the like, the CPU does not do any operation, so that the execution efficiency of the CPU is low, and the operation speed of the kernel is low; the commercial 16-bit CPU core of an established manufacturer has a high operation speed but is expensive.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a central processing unit and an instruction processing method thereof, so as to greatly increase the operation speed of the traditional 16-bit CPU core and keep the low price of the novel traditional 16-bit CPU on the premise that the structural volume of the traditional 16-bit CPU core is not changed.
In order to solve the above technical problem, the present invention provides a central processing unit, including: the system comprises a decoding unit, an execution unit and an instruction buffer unit; wherein, still include:
an instruction buffer selector;
the number of the instruction buffer units is two;
the decoding unit is used for generating an instruction prejudging signal according to the decoded instruction; the instruction prejudging signal is used for indicating whether a next execution unit needs to execute a jump instruction or not;
the instruction buffer selector is used for switching from the currently selected instruction buffer unit to another buffer instruction unit when the received instruction prejudging signal indicates that the next execution unit needs to execute the jump instruction, and controlling the switched buffer instruction unit to read and store the instruction from the position of the program memory pointed by the jump instruction; when jumping occurs, reading an instruction from the switched buffer instruction unit and sending the instruction to the decoding unit; and when the execution result of the jump instruction is no jump, switching back to the selected buffer instruction unit before switching to continue reading the instruction.
Further, the central processing unit has the following characteristics: further comprising:
the one-bit accumulator is used for accumulating the jump effective signals of the jump instruction executed by the execution unit and sending the accumulated result to the instruction buffer selector;
and the instruction buffer selector selects different instruction buffer units when jumping occurs according to the accumulation result, reads an instruction from the selected instruction buffer unit and sends the instruction to the decoding unit.
Further, the central processing unit has the following characteristics:
when a jump occurs, the instruction buffer selector is further configured to send a non-selected signal to the pre-switch selected instruction buffer unit,
and the instruction buffer unit selected before switching empties the stored instruction after receiving the unselected signal of the instruction buffer selector.
Further, the central processing unit has the following characteristics:
when the execution result of the jump instruction is no jump, the instruction buffer selector is further used for sending a jump invalid signal to the switched buffer instruction unit,
the switched buffer instruction unit clears the stored instruction upon receiving a jump disable signal of the instruction buffer selector.
In order to solve the above problem, the present invention further provides an instruction processing method, applied to the central processing unit, including:
the decoding unit generates an instruction pre-judging signal according to the decoded instruction, wherein the instruction pre-judging signal is used for indicating whether a next execution unit needs to execute a jump instruction or not;
when the received instruction prejudging signal indicates that the next execution unit needs to execute the jump instruction, the instruction buffer selector switches from the currently selected instruction buffer unit to another buffer instruction unit, and controls the switched buffer instruction unit to read and store the instruction from the position of the program memory pointed by the jump instruction; when jumping occurs, reading an instruction from the switched buffer instruction unit and sending the instruction to the decoding unit; and when the execution result of the jump instruction is no jump, switching back to the selected buffer instruction unit before switching to continue reading the instruction.
Further, the method also has the following characteristics: further comprising:
the one-bit accumulator accumulates jump effective signals of the jump instruction executed by the execution unit and sends an accumulation result to the instruction buffer selector;
and the instruction buffer selector selects different instruction buffer units when jumping occurs according to the accumulation result, reads an instruction from the selected instruction buffer unit and sends the instruction to the decoding unit.
Further, the method also has the following characteristics:
when a jump occurs, the instruction buffer selector also sends a non-selected signal to the pre-switch selected instruction buffer unit,
and the instruction buffer unit selected before switching empties the stored instruction after receiving the unselected signal of the instruction buffer selector.
Further, the method has the following characteristics:
when the execution result of the jump instruction is no jump, the instruction buffer selector also sends a jump invalid signal to the switched buffer instruction unit,
the switched buffer instruction unit clears the stored instruction upon receiving a jump disable signal of the instruction buffer selector.
In summary, the present invention provides a CPU and an instruction processing method thereof, which aim at the core structure characteristics of a conventional and small-sized independently developed 16-bit CPU, and compare the results in advance by adding an instruction cache unit to the core based on a result pre-judging mechanism, so that the core is converted into a pseudo dual core. Due to the pre-judging mechanism, the core speed of the CPU can be increased by 25% on the basis of not increasing the area of the original CPU. The CPU of the invention can greatly improve the operation speed of the traditional 16-bit CPU core and keep the lower price of the novel traditional 16-bit CPU on the premise of keeping the structural volume of the traditional 16-bit CPU core unchanged.
Drawings
FIG. 1 is a diagram of a conventional 16-bit CPU core architecture;
FIG. 2 is a block diagram of the kernel operation of a conventional 16-bit CPU;
FIG. 3 is a general block diagram of a CPU according to an embodiment of the present invention;
FIG. 4 is a block diagram of the CPU operation mechanism and operation process according to an embodiment of the present invention;
fig. 5 is a block diagram of a specific control mechanism and control process of the CPU according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
As shown in fig. 3, a CPU provided in an embodiment of the present invention includes: the system comprises a program bus interface, two instruction buffer units (including an instruction buffer unit A and an instruction buffer unit B), an instruction buffer selector, a decoding unit, an execution unit and a series of auxiliary units. Wherein,
the decode unit may be configured to generate an instruction anticipation signal, where the instruction anticipation signal is used to indicate whether a next execution unit is to execute a jump instruction;
the instruction buffer selector is used for switching from the currently selected instruction buffer unit to another buffer instruction unit when the received instruction anticipation signal indicates that the next execution unit is to execute the jump instruction, and controlling the switched buffer instruction unit to read and store the instruction from the position of the program memory pointed by the jump instruction; when jumping occurs, reading an instruction from the switched buffer instruction unit and sending the instruction to the decoding unit; and when the execution result of the jump instruction is no jump, switching back to the selected buffer instruction unit before switching to continue reading the instruction.
The specific execution of each unit in the CPU of the present embodiment is as follows:
the instruction buffer unit is used for reading and storing a program instruction according to a received reading signal of the instruction buffer selector, and sending the read program instruction to the instruction buffer selector after receiving a selected signal of the instruction buffer selector or clearing the stored instruction after receiving a jump invalid signal of the instruction buffer selector; or stopping reading the program instruction according to the received reading stopping signal of the instruction buffer selector, emptying the stored instruction after receiving the unselected signal of the instruction buffer selector or continuing reading the program instruction after receiving the jump invalid signal of the instruction buffer selector;
the instruction buffer selector is used for sending the program instruction to the decoding unit; after receiving the instruction pre-judging signal sent by the decoding unit, sending the reading stopping signal to an instruction buffer unit which reads a program instruction currently, and sending a reading signal to another instruction buffer unit; after receiving an execution result signal of the execution unit, judging whether the execution unit successfully executes the jump instruction, if so, switching selected signals of the two instruction buffer units, and if not, respectively sending jump invalid signals to the two instruction buffer units;
the decoding unit is used for analyzing the program instruction into a series of control signals and sending the control signals to the execution unit, and analyzing whether the program instruction comprises a jump instruction or not, and if the program instruction comprises the jump instruction, sending an instruction pre-judgment signal to the instruction buffer selector;
and the execution unit is used for executing after receiving the control signal, and sending an execution result signal of the jump instruction to the instruction buffer selector if the jump instruction is executed.
The CPU instruction processing method, the arithmetic mechanism, and the arithmetic process of this embodiment are shown in fig. 4, where the pseudo dual core of the CPU of this embodiment first reads a program instruction to be executed from the program memory; selectively storing the instruction into an instruction buffer unit A or an instruction buffer unit B through a program bus interface, and sending the instruction to an instruction buffer selector by the instruction buffer unit A and the instruction buffer unit B; the instruction buffer selector selects the instruction which needs to be executed currently and sends the instruction to the decoding unit; the decoding unit analyzes a series of control signals and sends the control signals to the execution unit for execution, and the decoding unit simultaneously analyzes an instruction prejudging signal which indicates whether the next execution unit needs to execute a jump instruction or not. When the anticipation signal is valid (i.e. the next time the execution unit will execute a jump instruction), the instruction buffer unit will automatically switch to another instruction buffer unit, and the switched instruction buffer unit will read the program from the location of the program memory pointed by the jump instruction and store the program in the switched instruction buffer unit.
When instruction jump occurs (namely the instruction jump is effective, and an execution unit successfully executes a jump instruction), an instruction buffer selector can directly read an instruction from the switched instruction buffer unit for execution, and the other instruction buffer unit is emptied at the same time, so that the operation is restarted when the next jump instruction occurs; if the execution result of the jump instruction is that no jump occurs (i.e. instruction jump is invalid and execution of the jump instruction by the execution unit fails), the instruction buffer selector will continue to read instructions from the original instruction buffer unit, and the instruction buffer unit to which the instruction buffer selector is switched will be automatically emptied, and the original instruction buffer unit will continue to read instructions from the program memory.
As shown in fig. 5, it can be seen that both the instruction buffer units a and B can send the position information of the program to be read from the program bus interface, and can obtain the program instruction at the position from the program bus interface for storage. The instruction buffer units A and B may provide instructions to be executed to the instruction buffer selector, which selects the instructions to be provided to the decode unit. Meanwhile, the instruction buffer selector can send an instruction buffer unit A control signal to the instruction buffer unit A, wherein the signal can indicate whether the instruction buffer unit A needs to read the program instruction from the program bus interface; the instruction buffer selector may also send an instruction buffer unit B control signal to instruction buffer B, which may indicate whether instruction buffer unit B needs to read program instructions from the program bus interface.
Instruction buffer units A and B feed the selected instruction as the current instruction to the decode unit through the instruction buffer selector. The instruction buffer selector takes an instruction selection signal as a discrimination standard, and the instruction selection signal is generated by a one-bit accumulator. The initial value of the accumulator is 0, namely the instruction input of the default selection instruction buffer unit A, when the instruction jump signal is valid (namely the execution unit is judged to successfully execute the jump instruction), the one-bit accumulator automatically adds one to change the instruction selection signal from 0 to 1, namely the instruction input of the selected instruction buffer unit B is selected, when the instruction jump signal is valid again, the instruction selection signal is changed from 1 to 0, and the instruction input of the selected instruction buffer unit A is selected again.
The instruction buffer selector selects to control the instruction buffer units A and B to read instructions from the program bus interface through the instruction pre-judging signal, and in an initial state, the instruction pre-judging signal is 0, namely the instruction buffer unit A is selected to read the program instructions from the program bus interface, and the instruction buffer unit B is idle. When the instruction prejudging signal is effective, the control bit of the instruction buffer unit B is effective, at the moment, the instruction buffer unit B is selected to read the program instruction from the program bus interface, and the instruction buffer unit A empties itself and waits for starting next time when the instruction skipping signal is effective.
The decoding unit is responsible for analyzing the current instruction, and generating a series of control signals to be sent to the execution unit for execution; the decoding unit comprises an instruction prejudging device which can prejudge whether the control signal analyzed by the decoding unit is a jump instruction or not, if the control signal is judged to be a jump instruction, the instruction prejudging signal is effective, and then the instruction prejudging signal is sent to the instruction buffer selector. The decoding unit sends a series of control signals to the execution unit, the execution unit carries out different operations according to different instruction types, and when a jump instruction is executed, a result signal of executing the jump instruction is sent to the instruction buffer selector. After receiving a result signal of executing the jump instruction, the instruction buffer selector judges whether the execution unit successfully executes the jump instruction, and if the execution unit successfully executes the jump instruction, the instruction jump signal is effective; if not, the instruction buffer selector will send an instruction jump invalidate signal to instruction buffer units A and B, respectively.
The pseudo dual core technology of the 16-bit CPU provided by the embodiment of the invention is characterized by comprising two instruction buffer units and a physical operation unit, and the operation speed of the CPU is improved under the condition that only one instruction is executed in the same time. However, in the true dual-core technology, two physical arithmetic units execute two unrelated instructions at the same time, so that the area of the original CPU core is doubled, and the price of the CPU is increased accordingly. The embodiment of the invention still adopts a single 16-bit CPU, and the instruction cache unit and the result prejudging mechanism are added to change the CPU into a pseudo dual core, so that the operation speed of the original kernel of the traditional 16-bit CPU is improved. Due to the pre-judging mechanism, the core speed of the CPU can be increased by 25% on the basis of not increasing the area of the original CPU. Therefore, the CPU of the embodiment of the invention can greatly improve the operation speed of the traditional 16-bit CPU core and keep the low price of the novel traditional 16-bit CPU on the premise of keeping the structural volume of the traditional 16-bit CPU core unchanged.
It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing the relevant hardware through a program, and the program may be stored in a computer readable storage medium, such as a read-only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present invention is not limited to any specific form of combination of hardware and software.
The foregoing is only a preferred embodiment of the present invention, and naturally there are many other embodiments of the present invention, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the scope of the appended claims.
Claims (4)
1. A central processing unit specifically comprises: a conventional 16-bit CPU, comprising: the system comprises a decoding unit, an execution unit and an instruction buffer unit; it is characterized by also comprising:
an instruction buffer selector;
the number of the instruction buffer units is two;
the decoding unit is used for generating an instruction prejudging signal according to the decoded instruction; the instruction prejudging signal is used for indicating whether a next execution unit needs to execute a jump instruction or not;
the instruction buffer selector is used for switching from the currently selected instruction buffer unit to another buffer instruction unit when the received instruction prejudging signal indicates that the next execution unit needs to execute the jump instruction, and controlling the switched buffer instruction unit to read and store the instruction from the position of the program memory pointed by the jump instruction; when jumping occurs, reading an instruction from the switched buffer instruction unit and sending the instruction to the decoding unit; when the execution result of the jump instruction is not jump, switching back to the selected buffer instruction unit before switching to continue reading the instruction;
when the execution result of the jump instruction is no jump, the instruction buffer selector is further used for sending a jump invalid signal to the switched buffer instruction unit,
the switched buffer instruction unit clears the stored instruction after receiving the jump invalid signal of the instruction buffer selector;
further comprising:
the one-bit accumulator is used for accumulating the jump effective signals of the jump instruction executed by the execution unit and sending the accumulated result to the instruction buffer selector;
and the instruction buffer selector selects different instruction buffer units when jumping occurs according to the accumulation result, reads an instruction from the selected instruction buffer unit and sends the instruction to the decoding unit.
2. The central processing unit of claim 1, wherein:
when a jump occurs, the instruction buffer selector is further configured to send a non-selected signal to the pre-switch selected instruction buffer unit,
and the instruction buffer unit selected before switching empties the stored instruction after receiving the unselected signal of the instruction buffer selector.
3. An instruction processing method applied to the central processing unit according to any one of claims 1-2, comprising:
the decoding unit generates an instruction pre-judging signal according to the decoded instruction, wherein the instruction pre-judging signal is used for indicating whether a next execution unit needs to execute a jump instruction or not;
when the received instruction prejudging signal indicates that the next execution unit needs to execute the jump instruction, the instruction buffer selector switches from the currently selected instruction buffer unit to another buffer instruction unit, and controls the switched buffer instruction unit to read and store the instruction from the position of the program memory pointed by the jump instruction; when jumping occurs, reading an instruction from the switched buffer instruction unit and sending the instruction to the decoding unit; when the execution result of the jump instruction is not jump, switching back to the selected buffer instruction unit before switching to continue reading the instruction;
when the execution result of the jump instruction is no jump, the instruction buffer selector also sends a jump invalid signal to the switched buffer instruction unit,
the switched buffer instruction unit clears the stored instruction after receiving the jump invalid signal of the instruction buffer selector;
further comprising:
the one-bit accumulator accumulates jump effective signals of the jump instruction executed by the execution unit and sends an accumulation result to the instruction buffer selector;
and the instruction buffer selector selects different instruction buffer units when jumping occurs according to the accumulation result, reads an instruction from the selected instruction buffer unit and sends the instruction to the decoding unit.
4. The method of claim 3, wherein:
when a jump occurs, the instruction buffer selector also sends a non-selected signal to the pre-switch selected instruction buffer unit,
and the instruction buffer unit selected before switching empties the stored instruction after receiving the unselected signal of the instruction buffer selector.
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| CN107194246B (en) * | 2017-05-19 | 2020-10-02 | 中国人民解放军信息工程大学 | CPU for realizing dynamic instruction set randomization |
| CN112540792A (en) * | 2019-09-23 | 2021-03-23 | 阿里巴巴集团控股有限公司 | Instruction processing method and device |
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| US3614747A (en) * | 1968-10-31 | 1971-10-19 | Hitachi Ltd | Instruction buffer system |
| US4992932A (en) * | 1987-12-29 | 1991-02-12 | Fujitsu Limited | Data processing device with data buffer control |
| CN1675626A (en) * | 2002-08-12 | 2005-09-28 | 皇家飞利浦电子股份有限公司 | Instruction cache way prediction for jump targets |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3614747A (en) * | 1968-10-31 | 1971-10-19 | Hitachi Ltd | Instruction buffer system |
| US4992932A (en) * | 1987-12-29 | 1991-02-12 | Fujitsu Limited | Data processing device with data buffer control |
| CN1675626A (en) * | 2002-08-12 | 2005-09-28 | 皇家飞利浦电子股份有限公司 | Instruction cache way prediction for jump targets |
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