CN104008974A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN104008974A
CN104008974A CN201310059403.9A CN201310059403A CN104008974A CN 104008974 A CN104008974 A CN 104008974A CN 201310059403 A CN201310059403 A CN 201310059403A CN 104008974 A CN104008974 A CN 104008974A
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semiconductor layer
gate
layer
region
semiconductor
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唐兆云
闫江
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201310059403.9A priority Critical patent/CN104008974A/zh
Priority to PCT/CN2013/074878 priority patent/WO2014131239A1/zh
Publication of CN104008974A publication Critical patent/CN104008974A/zh
Priority to US14/814,003 priority patent/US20150340464A1/en
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Abstract

公开了一种半导体器件及其制造方法，其中，所述制造半导体器件的方法，包括：在半导体层中形成栅极开口；在栅极开口中形成牺牲栅；在半导体层的邻近栅极开口的部分中形成源区和漏区；去除牺牲栅；以及在栅极开口中形成包括替代栅介质层和替代栅导体层的栅堆叠，其中，栅极开口用于限定半导体层的提供沟道区的部分的厚度。该方法形成的半导体器件可以改善沟道控制。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体技术，更具体地涉及采用后栅工艺制造半导体器件的方法及获得的半导体。
背景技术
集成电路的发展趋势是晶体管的尺寸的按比例缩小，这将导致公知的短沟道效应。近年来提出了超薄SOI晶体管，在超薄SOI晶片的顶部半导体中形成的沟道区完全耗尽，从而实现了对短沟道效应的良好控制。
如图20所示，常规的超薄SOI晶体管形成在包含底部衬底11、绝缘掩埋层(BOX)12、半导体层13的SOI晶片上，包括在半导体层中形成的沟道区，在沟道区上方形成的包括栅极电介质14和栅极导体15的栅极，在栅极侧面形成的侧墙16、以及抬高的源/漏区(RSD)17a、17b。
在上述超薄SOI晶体管中，RSD减小了源/漏电阻并使得栅-源和栅-漏寄生电容最小化。此外，在源/漏区上方形成硅化物时，RSD提供了足够的Si参与硅化，避免源/漏区的Si在硅化中完全消耗掉。
然而，由于使用超薄SOI晶片，超薄SOI晶体管的价格昂贵。此外，RSD的形成包括在形成栅极以及在栅极侧面形成侧墙之后，对超薄SOI晶片的半导体层进行预清洁并在其上外延生长硅层，这导致制造晶体管的工艺复杂化以及成品率低，这进一步导致制造成本升高。
发明内容
本发明的目的是提供一种可以改善沟道控制的半导体器件及其制造方法。
根据本发明的一方面，提供一种制造半导体器件的方法，包括：在半导体层中形成栅极开口；在栅极开口中形成牺牲栅；在半导体层的邻近栅极开口的部分中形成源区和漏区；去除牺牲栅；以及在栅极开口中形成包括替代栅介质层和替代栅导体层的栅堆叠，其中，栅极开口用于限定半导体层的提供沟道区的部分的厚度。
根据本发明的另一方面，提供一种半导体器件，包括：位于半导体层中的栅极开口；位于栅极开口中的包括替代栅介质层和替代栅导体层的栅堆叠；以及位于半导体层的邻近栅极开口的部分中的源区和漏区，其中，栅极开口用于限定半导体层的提供沟道区的部分的厚度。
根据本发明的半导体器件可以利用栅极开口减小沟道区的厚度，从而改善沟道控制。栅极开口限定沟道区的顶部表面。在优选的实施例中，利用与源区和漏区的掺杂剂类型相反的掺杂剂在半导体层下方形成阱区以限定沟道区的底部表面。由于源区和漏区形成在半导体层的邻近栅极开口的部分中，因此源区和漏区仍然保持较大的厚度及较小的寄生电阻。本发明不必采用附加的外延生长形成抬高的源区和漏区，从而可以降低制造成本。
附图说明
图1-14是示出了根据本发明的方法的第一实施例制造半导体器件的各个阶段的半导体结构的示意图，各个截面图均沿着沟道的纵向方向截取。
图15-17是示出了根据本发明的方法的第二实施例制造半导体器件的一部分阶段的半导体结构的示意图，各个截面图均沿着沟道的纵向方向截取。
图18-19是示出了根据本发明的方法的第三实施例制造半导体器件的一部分阶段的半导体结构的示意图，各个截面图均沿着沟道的纵向方向截取。
图20示出了根据现有技术的超薄SOI晶体管的结构示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将采用“直接在......上面”或“在......上面并与之邻接”的表述方式。
在本申请中，术语“半导体结构”指在制造半导体器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域；术语“沟道区的纵向方向”指从源区到漏区和方向，或相反的方向；术语“沟道区的横向方向”在与半导体衬底的主表面平行的平面内与沟道区的纵向方向垂直的方向。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出，半导体器件的各个部分可以由本领域的技术人员公知的材料构成。半导体材料例如包括III-V族半导体，如GaAs、InP、GaN、SiC，以及IV族半导体，如Si、Ge。栅极导体可以由能够导电的各种材料形成，例如金属层、掺杂多晶硅层、或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料，例如为TaC、TiN、TaTbN、TaErN、TaYbN、TaSiN、HfSiN、MoSiN、RuTax、NiTax，MoNx、TiSiN、TiCN、TaAlC、TiAlN、TaN、PtSix、Ni3Si、Pt、Ru、Ir、Mo、HfRu、RuOx|和所述各种导电材料的组合。栅极电介质可以由SiO2或介电常数大于SiO2的材料构成，例如包括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括SiO2、HfO2、ZrO2、A12O3、TiO2、La2O3，氮化物例如包括Si3N4，硅酸盐例如包括HfSiOx，铝酸盐例如包括LaAlO3，钛酸盐例如包括SrTiO3，氧氮化物例如包括SiON。并且，栅极电介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极电介质的材料。
<第一实施例>
按照本发明的第一实施例，执行图1至14中所示的以下步骤以制造半导体器件，在图中示出了不同阶段的半导体结构的截面图
如图1所示，作为初始结构的半导体结构例如是SOI(绝缘体上硅)晶片。该SOI晶片包括半导体衬底101、绝缘掩埋层102和半导体层103。然而，与图20所示的根据现有技术的超薄SOI晶体管不同，在本发明中使用的SOI晶片中的半导体层103的厚度(例如25nm-200nm)可以大于超薄SOI晶片的半导体层的厚度(例如10nm-15nm)，因而不需要使用昂贵的超薄SOI晶片。在一个示例中，SOI晶片中的半导体衬底101和半导体层103例如均由单晶硅组成，并且半导体层103的厚度约为50nm，绝缘掩埋层102例如由氧化硅组成，并且厚度约为140nm。
在半导体层103上依次形成衬垫氧化物层104和衬垫氮化物层105。衬垫氧化物层104例如由氧化硅组成，厚度约为2nm-20nm。衬垫氮化物层105例如由氮化硅组成，厚度约为50nm-200nm。正如已知的那样，衬垫氧化物层104可以减轻半导体层103和衬垫氮化物层105之间的应力。衬底氮化物层105在随后的蚀刻步骤中用作硬掩模。
用于形成上述各层的工艺是已知的。例如，通过热氧化形成衬垫氧化物层104。例如，通过化学气相沉积形成衬垫氮化物层105。
然后，通过旋涂在衬垫氮化物层105上形成光致抗蚀剂层PR1，并通过其中包括曝光和显影的光刻工艺将光致抗蚀剂层形成浅沟槽隔离的图案。利用光致抗蚀剂层作为掩模，通过干法蚀刻，如离子铣蚀刻、等离子蚀刻、反应离子蚀刻、激光烧蚀，或者通过其中使用蚀刻剂溶液的湿法蚀刻，从上至下依次去除衬垫氮化物层105和衬垫氧化物层104的暴露部分。该蚀刻在半导体层103的表面停止，并且在衬垫氮化物层105和衬垫氧化物层104形成浅沟槽隔离的图案。通过在溶剂中溶解或灰化去除光致抗蚀剂层PR1。
利用衬垫氮化物层105和衬垫氧化物层104一起作为硬掩模，通过上述已知的干法蚀刻或湿法蚀刻，进一步去除半导体层103的暴露部分，从而在半导体层103中形成浅沟槽，如图2所示。尽管非必需的，根据采用的蚀刻工艺，可以进一步蚀刻绝缘掩埋层102和半导体衬底101，使得浅沟槽延伸到绝缘掩埋层102或半导体衬底101中的预定深度。正如本领域的技术人员可以理解的那样，该浅沟槽围绕半导体器件的有源区。
然后，通过已知的沉积工艺，如电子束蒸发(EBM)、化学气相沉积(CVD)、原子层沉积(ALD)、溅射等，在半导体结构的表面上形成绝缘材料层。该绝缘材料层填充浅沟槽。通过化学机械抛光(CMP)去除绝缘材料层位于浅沟槽外部的部分。绝缘材料层留在浅沟槽内的部分形成浅沟槽隔离106，如图3所示。正如本领域的技术人员可以理解的那样，浅沟槽隔离106限定半导体器件的有源区。
然后，通过旋涂在衬垫氮化物层105上形成光致抗蚀剂层PR2，并通过光刻工艺将光致抗蚀剂层PR2形成栅极开口的图案(例如，条带状)。利用光致抗蚀剂层PR2作为掩模，通过上述已知的干法蚀刻或湿法蚀刻，从上至下依次去除衬垫氮化物层105和衬垫氧化物层104的暴露部分，如图4所示。该蚀刻在半导体层103的表面停止，并且在衬垫氮化物层105和衬垫氧化物层104形成栅极开口的图案。通过在溶剂中溶解或灰化去除光致抗蚀剂层PR2。
利用衬垫氮化物层105和衬垫氧化物层104一起作为硬掩模，通过上述已知的干法蚀刻或湿法蚀刻，进一步蚀刻半导体层103达到预定的深度，从而在半导体层103中形成栅极开口，如图5所示。通过控制蚀刻的时间，使得半导体层103位于栅极开口下方的部分(即最终形成的半导体器件的沟道区)的厚度为所需的数值。
作为优选的步骤，在形成栅极开口之后，可以进一步进行热氧化，使得半导体层103在栅极开口的底部和侧壁上的暴露部分形成氧化物。然后，上述已知的干法蚀刻或湿法蚀刻，相对于半导体层103的半导体材料选择性地去除氧化物，从而进一步减小半导体层103位于栅极开口下方的部分(即最终形成的半导体器件的沟道区)的厚度。
本发明人已经发现该部分的厚度可以减小至约1nm，例如可以控制在1nm-30nm之间的范围内。因此，最终形成的半导体器件的沟道区的厚度可以与常规的超薄SOI晶片提供的沟道区相当，但由于未使用超薄SOI晶片而成本更低。或者，最终形成的半导体器件的沟道区的厚度可以显著小于常规的超薄SOI晶片提供的沟道区的厚度，从而进一步改善沟道的控制。
然后，例如使用热磷酸去除衬垫氮化物层105，使用氢氟酸去除衬垫氧化物层104，接着进行热氧化或者化学气相沉积法沉积氧化硅，使得半导体层103在栅极开口中的底部和侧壁上的暴露部分以及在栅极开口外的顶部表面形成氧化物层107，如图6所示。该步骤形成的氧化物层107在随后的蚀刻步骤中作为停止层，厚度例如为约10nm。根据半导体器件的要求，可以在氧化硅生长之后进行离子注入用来调节阈值电压。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成共形的氮化物层，如图7所示。
然后，通过各向异性的蚀刻工艺(例如，反应离子蚀刻)，相对于氧化物层107，选择性地去除氮化物层位于栅极开口外的部分和位于栅极开口底部的部分，使得氮化物层位于栅极开口内壁上的部分保留形成栅极侧墙108，如图8所示。在一个示例中，该栅极侧墙108的厚度由先前的氮化物层的厚度决定，例如为厚度约5nm-50nm的氮化硅层。通过改变栅极侧墙108的厚度，可以获得所需的电绝缘性能以及减小栅极线宽。
然后，通过上述已知的沉积工艺，在半导体结构的表面形成氧化物层。该氧化物层填充栅极开口。采用化学机械抛光(CMP)平整半导体结构的表面。该化学机械抛光在半导体层103的顶部停止，从而去除了氧化物层位于栅极开口外部的部分以及浅沟槽隔离106的突出部分。在化学机械抛光之后，栅极开口中的氧化物层的剩余部分形成牺牲栅109，如图9所示。替代地，牺牲栅109可以由在蚀刻工艺提供所需选择性的任何材料构成，而不限于氧化物。
根据最终获得的半导体器件的导电类型采用N型或P型掺杂剂，以氧化物层107、栅极侧墙108、牺牲栅109和浅沟槽隔离106作为硬掩模进行离子注入。然后例如在约1000-1080℃的温度下执行尖峰退火(spikeanneal)或者激光退火(laser anneal)，以激活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤，从而在半导体层103中形成源区110a和漏区110b，如图10所示。
然后，通过上述已知的沉积工艺，在半导体结构的表面形成金属层111，如图11所示。该金属层111由选自Ni、W、Ti、Co以及这些元素与其它元素的合金构成的组中的一种组成。在一个示例中，该金属层111是通过溅射沉积的NiPt层。进行热退火，例如在300-500℃的温度下热退火1-10秒钟，使得金属层111在源区110a和漏区110b的表面进行硅化反应以形成金属硅化物层112a、112b，以减小源区和漏区的接触电阻，如图11所示。该硅化消耗源区110a和漏区110b的一部分半导体材料。在栅极开口中，由于牺牲栅109将金属层111与半导体层103隔开，因此硅化并未到达半导体层103位于栅极开口下方的部分中。也即，牺牲栅109在硅化工艺中作为半导体器件的沟道区的保护层。
然后，通过上述已知的干法蚀刻和湿法蚀刻去除金属层111未反应的部分，并且进一步去除牺牲栅109，如图12所示。该蚀刻可以分为两个步骤，分别去除金属层111未反应的部分和牺牲栅109，其中可以使用不同的蚀刻方法和/或蚀刻剂。在去除牺牲栅109时，氧化物层107作为蚀刻停止层，使得半导体层103的位于栅极开口下方的部分未受到过蚀刻。也即，氧化物层107在蚀刻工艺中作为半导体器件的沟道区的保护层。
然后，通过上述已知的沉积工艺，在半导体结构的表面上形成共形的替代栅介质层113，并进一步沉积替代栅导体层114填充栅极开口，从而形成包括栅介质层和栅导体层的栅堆叠，如图13所示。该替代栅介质层113例如是厚度约为1nm-3nm的HfO2层。该替代栅导体层114例如是厚度足以填充栅极开口的TiN层。
作为优选的步骤，在形成替代栅介质层113之后，在栅极开口首先形成阈值调节层(例如TIN、TaN、TiAlN、TaAlN)，然后才形成替代栅导体层114。该阈值调节层可以改变有效功函数，从而调节半导体器件的阈值电压。
然后，以金属硅化物层112a、112b作为停止层，通过化学机械抛光去除替代栅介质层113和替代栅导体层114位于栅极开口外的部分。替代栅介质层113和替代栅导体层114位于栅极开口内的部分保留，从而形成栅堆叠，如图14所示。该化学机械抛光还暴露金属硅化物层112a、112b的表面，以提供将要形成的柱塞与源区110a和漏区110b之间的电接触。
根据该实施例，在结合图1至14描述的步骤之后，可以在所得到的半导体结构上形成层间绝缘层、位于层间绝缘层中的柱塞、位于层间绝缘层上表面的布线或电极，从而完成半导体器件的其他部分。
根据第一实施例的半导体器件，在半导体层103的提供沟道区的部分上方的栅极开口限定了沟道区的顶部表面，从而减小了沟道区的厚度而改善沟道控制。
<第二实施例>
图15-17是示出了根据本发明的方法的第二实施例制造半导体器件的一部分阶段的半导体结构的示意图，各个截面图均沿着沟道的纵向方向截取。
根据本发明的第二实施例，进一步利用阱区限制SOI晶片的半导体层103的厚度。为了简明起见，在以下描述中将仅指出第二实施例的区别，而不再详述第二实施例中与第一实施例相同的步骤和相应的结构特征。
在第一实施例的图3所示的用于形成浅沟槽隔离106的步骤之后，进一步执行图15和16所示的步骤。
如图15所示，使用热磷酸去除衬垫氮化物层105。
然后，在未使用掩模的情形下进行离子注入，在SOI晶片的半导体层103中形成阱区115，如图16所示。正如本领域已知的，通过控制离子注入的参数(例如能量和剂量)，可以控制阱区115的深度和延伸范围，使得阱区115位于半导体层103的下部。阱区115的掺杂剂类型与半导体器件的源区110a和漏区110b的掺杂类型相反。然后，继续执行图4-14所示的随后步骤。
在图17中示出了与第一实施例的图14对应的半导体结构的示意图。根据第二实施例的半导体器件，不仅在半导体层103的提供沟道区的部分上方的栅极开口限定了沟道区的顶部表面，而且在半导体层103的提供沟道区的部分下方的阱区115进一步限定了沟道区的底部表面，从而进一步减小了沟道区的厚度而改善沟道控制。
此外，由于阱区115位于源区110a和漏区110b下方并且与其掺杂剂类型相反，因此阱区115还作为穿通阻止层减小源区110a和漏区110b之间经由半导体层103的漏电流。
<第三实施例>
图18-19是示出了根据本发明的方法的第三实施例制造半导体器件的一部分阶段的半导体结构的示意图，各个截面图均沿着沟道的纵向方向截取。
根据本发明的第三实施例，采用块状的半导体衬底101形成半导体器件，而不需要使用昂贵的SOI晶片。在块状的半导体衬底101中，利用阱区限定半导体层及其厚度。为了简明起见，在以下描述中将仅指出第三实施例的区别，而不再详述第三实施例中与第一实施例相同的步骤和相应的结构特征。
代替第一实施例的图1所示的步骤，执行图18所示的以下步骤。
作为初始结构的半导体结构例如是块状的半导体衬底101。在半导体衬底101上依次形成衬垫氧化物层104和衬垫氮化物层105。衬垫氧化物层104例如由氧化硅组成，厚度约为2nm-20nm。衬垫氮化物层105例如由氮化硅组成，厚度约为50nm-200nm。正如已知的那样，衬垫氧化物层104可以减轻半导体衬底101和衬垫氮化物层105之间的应力。衬底氮化物层105在随后的蚀刻步骤中用作硬掩模。
用于形成上述各层的工艺是已知的。例如，通过热氧化形成衬垫氧化物层104。例如，通过化学气相沉积形成衬垫氮化物层105。
然后，在未使用掩模的情形下进行离子注入，在半导体衬底101的预定深度形成阱区116。正如本领域已知的，通过控制离子注入的参数(例如能量和剂量)，可以控制阱区116的深度和延伸范围，使得阱区116位于半导体衬底101的下部，半导体衬底101的位于阱区116上方的部分形成半导体层103。阱区116的掺杂剂类型与半导体器件的源区110a和漏区110b的掺杂类型相反。然后，继续执行图2-14所示的随后步骤。
在图19中示出了与第一实施例的图14对应的半导体结构的示意图。根据第三实施例的半导体器件，利用阱区116在块状的半导体衬底101中限定半导体层103，不仅半导体层103的提供沟道区的部分上方的栅极开口限定了沟道区的顶部表面，而且在半导体层103的提供沟道区的部分下方的阱区116进一步限定了沟道区的底部表面，从而减小了沟道区的厚度而改善沟道控制，并且由于不需要使用SOI晶片而降低了制造成本。
此外，由于阱区116位于源区110a和漏区110b下方并且与其掺杂剂类型相反，因此阱区116还作为穿通阻止层减小源区110a和漏区110b之间经由半导体层103的漏电流。
在以上的描述中，对于各层的构图、蚀刻等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。

Claims (18)

1.一种制造半导体器件的方法，包括：
在半导体层中形成栅极开口；
在栅极开口中形成牺牲栅；
在半导体层的邻近栅极开口的部分中形成源区和漏区；
去除牺牲栅；以及
在栅极开口中形成包括替代栅介质层和替代栅导体层的栅堆叠，
其中，栅极开口用于限定半导体层的提供沟道区的部分的厚度。
2.根据权利要求1所述的方法，其中栅极开口用于限定半导体层的提供沟道区的部分的顶部表面。
3.根据权利要求1所述的方法，其中在形成栅极开口的步骤之前，还包括进一步减小半导体层的提供沟道区的部分的厚度。
4.根据权利要求3所述的方法，其中进一步减小半导体层的提供沟道区的部分的厚度包括：
对半导体层进行离子注入以在半导体层的下部形成阱区，阱区的掺杂剂类型与源区和漏区的掺杂剂类型相反。
5.根据权利要求4所述的方法，其中阱区用于限定半导体层的提供沟道区的部分的底部表面。
6.根据权利要求1所述的方法，其中在形成栅极开口和形成牺牲栅的步骤之间，还包括进一步减小半导体层的提供沟道区的部分的厚度。
7.根据权利要求6所述的方法，其中进一步减小半导体层的提供沟道区的部分的厚度包括：
进行热氧化，使得半导体层在栅极开口的底部和侧壁上的暴露部分形成氧化物；以及
相对于半导体层去除氧化物。
8.根据权利要求1所述的方法，其中在形成栅极开口和形成牺牲栅的步骤之间，还包括在栅极开口内壁上形成栅极侧墙。
9.根据权利要求1所述的方法，其中半导体层是SOI晶片的半导体层，所述SOI晶片还包括半导体衬底以及位于半导体衬底和半导体层之间的绝缘掩埋层。
10.根据权利要求1所述的方法，在形成栅极开口的步骤之前，还包括：
对块状的半导体衬底进行离子注入以形成阱区，使得半导体衬底的位于阱区上的部分形成半导体层，阱区的掺杂剂类型与源区和漏区的掺杂剂类型相反。
11.根据权利要求1所述的方法，其中在形成栅极开口和形成牺牲栅的步骤之间，还包括：
经由栅极开口对半导体层进行离子注入以调节阈值电压。
12.一种半导体器件，包括：
位于半导体层中的栅极开口；
位于栅极开口中的包括替代栅介质层和替代栅导体层的栅堆叠；以及
位于半导体层的邻近栅极开口的部分中的源区和漏区，
其中，栅极开口用于限定半导体层的提供沟道区的部分的厚度。
13.根据权利要求12所述的半导体器件，其中栅极开口用于限定半导体层的提供沟道区的部分的顶部表面。
14.根据权利要求12所述的半导体器件，还包括位于半导体层的下部的阱区，并且阱区用于限定半导体层的提供沟道区的部分的底部表面，阱区的掺杂剂类型与源区和漏区的掺杂剂类型相反。
15.根据权利要求12所述的半导体器件，其中半导体层的提供沟道区的部分的厚度在1nm-30nm的范围内。
16.根据权利要求12所述的半导体器件，还包括位于栅极开口中的栅极侧墙。
17.根据权利要求12所述的半导体器件，其中半导体层是SOI晶片的半导体层。
18.根据权利要求12所述的半导体器件，其中半导体层是块状的半导体衬底中位于阱区上方的部分，阱区的掺杂剂类型与源区和漏区的掺杂剂类型相反。
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