CN104007591A - Pixel structure and manufacturing method thereof - Google Patents
Pixel structure and manufacturing method thereof Download PDFInfo
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- CN104007591A CN104007591A CN201410274513.1A CN201410274513A CN104007591A CN 104007591 A CN104007591 A CN 104007591A CN 201410274513 A CN201410274513 A CN 201410274513A CN 104007591 A CN104007591 A CN 104007591A
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Abstract
The invention discloses a pixel structure and a manufacturing method thereof, and relates to the technical field of display. The pixel structure comprises common electrode wires around a pixel, a data line, a scanning line and a thin film transistor switching device, wherein the data line and the scanning line are criss-crossed at the center of the pixel, the thin film transistor switching device is arranged in the crossed area of the data line and the scanning line, and a contact hole of the drain electrode of a thin film transistor is connected with a transparent pixel electrode. The four boundaries of the pixel are respectively formed by a lightproof common electrode line, and the aperture opening ratio of the pixel can be greatly improved. The invention further discloses a manufacturing method of the pixel structure at the same time.
Description
Technical field
The present invention relates to display technique field, especially relate to a kind of dot structure and manufacture method thereof.
Background technology
Thin Film Transistor-LCD (TFT-LCD) is jointly to be formed by array base palte, colored filter substrate and the liquid crystal that riddles between these two substrates.Conventional pixel structure on array base palte, sweep trace and public electrode wire are arranged parallel to each other, and stride across data line simultaneously and intersect with data line.This structure imports public electrode current potential in sweep trace terminal one side and one side while of sweep trace terminal opposite to the public electrode wire in viewing area.This structure adopts the public electrode wire and the pixel electrode that are formed by first layer metal to form memory capacitance.
Based on the array base palte of conventional pixel structure, the public electrode current potential that enters sweep trace terminal one side comes from data line terminal module.This public electrode current potential is supplied with to all public electrode wires by from top to bottom striding across successively each data bundle of lines current potential with data line with the second layer metal of layer.Because this distance striding across for the second layer metal line that imports public electrode current potential is very long, make to enter public electrode wire impedance comparison before viewing area large from data line terminal portion introduces public electrode current potential.Affect the current potential supply capacity of public electrode wire.
In display unit, the memory capacitance forming between public electrode wire and pixel electrode is middle across gate insulator and passivation layer.Due to across two-layer insulation film, in order to obtain larger storage capacitance value, common way is the area that increases public electrode wire, will reduce like this aperture opening ratio of display unit.
In order to solve the defect in above-mentioned conventional pixel structure, patent of invention CN101334564A discloses a kind of impedance that can reduce public electrode wire, has utilized narrower public electrode wire to form the dot structure of memory capacitance.Technical scheme used is to allow data line and public electrode wire be arranged parallel to each other, stride across sweep trace intersects with sweep trace simultaneously, the required current potential of public electrode wire is introduced respectively in the both sides of each data line terminal module, imports respectively viewing area by opposite one side of data line terminal one side and data line terminal.The memory capacitance being formed by the first metal layer public electrode and pixel electrode in conventional pixel structure is changed into by the second metal level public electrode and pixel electrode and forms memory capacitance, reduce the distance between metal public electrode wire and pixel electrode, increased memory capacitance.So just can utilize narrower public electrode wire to realize original required storage capacitance value.
The disclosed technical scheme of patent of invention CN101334564A is mainly used in the dot structure of twisted nematic (TN) liquid crystal display pattern, and display quality is to be improved; And between pixel, need to reserve certain gap, sacrificed part aperture opening ratio.
Along with the continuous requirement to display quality, vertical orientation (Vertical Alignment, VA) display panels is more in advanced liquid crystal application, belongs to wide viewing angle panel.In numerous VA lcd technologies, UV2A technology has the advantages such as high permeability, high-contrast and quick response, and other wide viewing angle technology such as IPS, FFS of comparing have advantages of high-contrast.But, along with the requirement of panel resolution is more and more higher, technical at existing UV2A, need further to improve again transmitance.
Summary of the invention
In view of this, for deficiency of the prior art, the invention provides a kind of dot structure and preparation method thereof, dot structure of the present invention is by four border configuration public electrode wires at pixel region, it not only can play shaded effect, can also significantly improve the aperture opening ratio of pixel.
One embodiment of the invention provides a kind of dot structure, and it comprises: a substrate, is provided with on it: the first public electrode wire, has a gap; The second public electrode wire, with this first public electrode wire pixel region that surrounds arranged in a crossed manner; One data line, is arranged in the vertical direction of this pixel region, and passes this gap of this first public electrode wire; One scan line, is arranged in the horizontal direction of this pixel region, and with the setting intersected with each other of this data line; One active member, is arranged at this data line and this sweep trace intersection region; One pixel electrode, and be electrically connected by a contact hole and this active member;
Preferably, described the second public electrode wire runs through up and down, and with this first public electrode wire with layer.
Preferably, this first and second public electrode wire and this data line are with layer, and this second public electrode wire is parallel to this data line,
Preferably, more than this first public electrode wire and this data line are spaced apart 2um.
Preferably, this first and second public electrode wire is disposed at the below of this pixel electrode, and overlaps to form memory capacitance with this pixel electrode part.
Based on above-described embodiment, the present invention also provides a kind of method for making of dot structure, and it comprises the following steps:
Step a, on a substrate, forms first layer metal Thinfilm pattern, and it comprises sweep trace;
Step b, on the pattern of this first metal layer, forms gate insulator, forms semiconductor pattern above this gate insulator;
Step c, on the pattern of this semiconductor layer, forms second layer metal Thinfilm pattern, and it comprises data line, first, second public electrode wire, the source electrode of thin film transistor (TFT), drain electrode;
Steps d, on this second metal layer pattern, forms transparent protection insulation course, forms transparent organic insulating film above this protection insulation course, then forms a contact hole of thin film transistor (TFT) drain electrode top;
Step e forms pixel electrode above this organic insulating film and this contact hole.
Compared with prior art, its advantage is in the present invention: four borders of described dot structure are all surrounded and formed by the public electrode wire of shading, can significantly improve the aperture opening ratio of pixel.
Brief description of the drawings
Fig. 1 is UV of the present invention
2a dot structure schematic diagram;
Fig. 2 is a kind of dot structure of first embodiment of the invention;
Fig. 3 is the pel array schematic diagram of dot structure shown in Fig. 2 of the present invention;
Fig. 4 is the enlarged drawing of dotted line frame shown in Fig. 3 of the present invention;
Fig. 5 (a) is the planimetric map of the ground floor pattern of dot structure shown in Fig. 2 of the present invention;
Fig. 5 (b) is the sectional drawing of the ground floor pattern AA ' direction of dot structure shown in Fig. 2 of the present invention;
Fig. 6 (a) is the planimetric map of the second layer pattern of dot structure shown in Fig. 2 of the present invention;
Fig. 6 (b) is the sectional drawing of the second layer pattern AA ' direction of dot structure shown in Fig. 2 of the present invention;
Fig. 7 (a) is the planimetric map of the 3rd layer pattern of dot structure shown in Fig. 2 of the present invention;
Fig. 7 (b) is the sectional drawing of the 3rd layer pattern AA ' direction of dot structure shown in Fig. 2 of the present invention;
Fig. 8 (a) is the planimetric map of the 4th layer pattern of dot structure shown in Fig. 2 of the present invention;
Fig. 8 (b) is the sectional drawing of the 4th layer pattern AA ' direction of dot structure shown in Fig. 2 of the present invention;
Fig. 9 (a) is the planimetric map of the layer 5 pattern of dot structure shown in Fig. 2 of the present invention;
Fig. 9 (b) is the sectional drawing of the layer 5 pattern AA ' direction of dot structure shown in Fig. 2 of the present invention;
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is UV of the present invention
2a dot structure schematic diagram.As shown in the figure, the invention provides a kind of UV of wide view angle
2a dot structure, it comprises three sub-pixels, as red pixel 15, green pixel 16 and blue pixel 17, each described pixel region periphery and horizontal zone, vertical area are coated with black line, the present invention is mainly the black line region that the data line in pixel, sweep trace and public electrode wire is configured in to described sub-pixel, particularly, data line is configured in to middle longitudinal black line region 13; Horizontal black line region 14 in the middle of sweep trace is configured in; Public electrode wire is configured in to the borderline region between red pixel 15, green pixel 16 and blue pixel 17, comprise the black line of longitudinal boundary region 11 and the black line of horizontal boundary region 12, by dot structure of the present invention, four borders of described dot structure are all surrounded and are formed by the public electrode wire of shading, can significantly improve the aperture opening ratio of pixel.
Embodiment mono-
Fig. 2 is a kind of dot structure of first embodiment of the invention.As shown in Figure 2, the invention provides a substrate (not shown), on it, be provided with: the first public electrode wire 24, has a gap; The second public electrode wire 23, with this first public electrode wire 24 pixel region that surrounds arranged in a crossed manner; One data line 22, is arranged on the median vertical line of this pixel region, and passes this gap of this first public electrode wire 24; One scan line 21, is arranged on the horizontal central line of this pixel region, and with the setting intersected with each other of this data line 22; One active member, is arranged at this data line 22 and these sweep trace 21 intersection regions; One pixel electrode 20, is electrically connected by a contact hole 27 and this active member.
In concrete implementation, on this first public electrode wire 24, be furnished with gap, this gap holds this data line 22 and passes, this the second public electrode wire up/down perforation, wherein, common electrode signal, by transmission on this second public electrode wire 23, is extended this first public electrode wire 24 in left and right from this second public electrode wire 23, both sides up and down of this pixel electrode 20.In this pixel region, this second public electrode wire line 23 is parallel with this data line 22.This data line 22 is with layer structure with this first, second public electrode wire.Preferably, between this first public electrode wire 24 and this data line 22, keep spacing more than 2um.
Wherein, the region intersecting at this data line 22 and this sweep trace 21, configuration active member, as thin film transistor (TFT) (TFT) switching device.The grid of TFT connects sweep trace 21, the source electrode connection data line 22 of TFT, and the drain electrode 26 of TFT connects pixel electrode 20 by contact hole 27.
Wherein, a contact hole 27 of TFT switch left and right drain electrode 26 tops is for connecting pixel electrode 20.By the first contact hole 27 and the second contact hole 28, the drain signal of TFT switch passes to pixel electrode 20.
Wherein, pixel electrode 20 covers pixel region, and overlaps to form memory capacitance with this first and second public electrode wire, and preferably, this pixel electrode and this first and second public electrode wire exist lap more than 1um.Again preferably, this pixel electrode 20 is transparent ito thin film.
Fig. 3 is the pel array schematic diagram of dot structure shown in Fig. 2 of the present invention.As shown in Figure 3, this the second public electrode wire left and right extends to form the first public electrode wire, described first, second public electrode wire besieged city pixel region, data line through the slot placement of this first concentric line on the median vertical line of this pixel region, and with the second public electrode line parallel.Sweep trace on the horizontal central line of this pixel region, and with this first public electrode line parallel.The region intersecting at data line and sweep trace, configuration TFT switch.
As a preferred embodiment, Fig. 4 is the enlarged drawing of dotted line frame shown in Fig. 3 of the present invention.As shown in Figure 4, the interval L11 between the pixel electrode of lastrow pixel and the pixel electrode of next line pixel is more than or equal to 4um; Interval L12 between the left side pixel electrode of one row pixel and the pixel electrode of right side one row pixel is more than or equal to 4um.
On the right side of pixel, the lap L51 of pixel electrode and public electrode main line is more than or equal to 2um; In the left side of pixel, the lap L52 of pixel electrode and public electrode main line is more than or equal to 2um; At the downside of pixel, the lap L53 of pixel electrode and the first public electrode is more than or equal to 2um; At the upside of pixel, the lap L54 of pixel electrode and the first public electrode is more than or equal to 2um;
The present invention also provides the method for making of dot structure described in above-described embodiment, and it comprises following making step:
(1), on glass substrate 50, sputter forms first layer metal film.Utilize first mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 5 (a).In Fig. 5 (a), middle pattern is sweep trace 51.The section structure of corresponding diagram 5 (a) dotted line AA ' is as shown in Fig. 5 (b).
(2), on the pattern of the first metal layer, form transparent gate insulator 60 by chemical vapor deposition method.Deposited semiconductor film above gate insulator 60.Utilize second mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 6 (a).In Fig. 6 (a), the pattern of sweep trace top is semiconductor channel layer 61.The section structure of corresponding diagram 6 (a) dotted line AA ' is as shown in Fig. 6 (b).
(3), on the pattern of semiconductor layer, sputter forms second layer metal film.Utilize the 3rd mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 7 (a).In Fig. 7 (a), the middle pattern running through is up and down data line 71, and the pattern that left and right is run through is up and down public electrode wire main line 73, and what on public electrode wire main line, extended left and right is the subordinate line 74 of public electrode wire.In the overlapping region of data line 71 and sweep trace, above semiconductor layer, form TFT switch.The grid of TFT switch is sweep trace, and the source electrode of TFT switch is data line 71, the drain electrode 72 of TFT switch and the same layer of data line 71.The section structure of corresponding diagram 7 (a) dotted line AA ' is as shown in Fig. 7 (b).
(4), on the pattern of the second metal level, form transparent protection insulation course 80 by chemical vapor deposition method.Above protection insulation course 80, be coated with the organic insulating film 83 of layer of transparent.The thickness of organic insulating film 83 is 2um.Utilize the 4th mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 8 (a).In Fig. 8 (a), the contact hole 82 of drain electrode top, TFT switch left and right is for connecting pixel electrode.Be connected with pixel electrode with contact hole 82 by contact hole 81, the drain signal of TFT switch passes to pixel electrode simultaneously.The section structure of corresponding diagram 8 (a) dotted line AA ' is as shown in Fig. 8 (b).
(5), above organic film and contact hole, sputter forms ITO transparent conductive film.Utilize the 5th mask plate, the technique such as coating by photoresist, exposure, development, etching forms the pattern as shown in Fig. 9 (a).In Fig. 9 (a), ITO transparent conductive film covers the top in pixel openings district, forms pixel electrode 91 regions, exists the overlapping region of 2um to form memory capacitance at surrounding and the public electrode wire of pixel electrode 91.The section structure of corresponding diagram 9 (a) dotted line AA ' is as shown in Fig. 9 (b).
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (8)
1. a dot structure, it comprises:
One substrate, is provided with on it:
The first public electrode wire, has a gap;
The second public electrode wire, with this first public electrode wire pixel region that surrounds arranged in a crossed manner;
One data line, is arranged in the vertical direction of this pixel region, and passes this gap of this first public electrode wire;
One scan line, is arranged in the horizontal direction of this pixel region, and with the setting intersected with each other of this data line;
One active member, is arranged at this data line and this sweep trace intersection region;
One pixel electrode, and be electrically connected by a contact hole and this active member.
2. dot structure as claimed in claim 1, is characterized in that: described the second public electrode wire runs through up and down, and with this first public electrode wire with layer.
3. dot structure as claimed in claim 1, is characterized in that: this first and second public electrode wire and this data line are with layer, and this second public electrode wire is parallel to this data line.
4. dot structure as claimed in claim 1, is characterized in that: more than this first public electrode wire and this data line are spaced apart 2um.
5. dot structure as claimed in claim 1, is characterized in that: this first and second public electrode wire is disposed at the below of this pixel electrode, and overlaps to form memory capacitance with this pixel electrode part.
6. dot structure as claimed in claim 5, is characterized in that: this pixel electrode and this first and second public electrode wire exist lap more than 1um.
7. dot structure as claimed in claim 1, is characterized in that: the interval between adjacent two pixel electrodes is more than or equal to 4um.
8. a method for making for dot structure as claimed in claim 1, it comprises the following steps:
Step a, on a substrate, forms first layer metal Thinfilm pattern, and it comprises sweep trace;
Step b, on the pattern of this first metal layer, forms gate insulator, forms semiconductor pattern above this gate insulator;
Step c, on the pattern of this semiconductor layer, forms second layer metal Thinfilm pattern, and it comprises data line, first, second public electrode wire, the source electrode of thin film transistor (TFT), drain electrode;
Steps d, on this second metal layer pattern, forms transparent protection insulation course, forms transparent organic insulating film above this protection insulation course, then forms a contact hole of thin film transistor (TFT) drain electrode top;
Step e forms pixel electrode above this organic insulating film and this contact hole.
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