CN103984268A - Input and output device of signal logic controller and signal logic controller - Google Patents
Input and output device of signal logic controller and signal logic controller Download PDFInfo
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- CN103984268A CN103984268A CN201410232646.2A CN201410232646A CN103984268A CN 103984268 A CN103984268 A CN 103984268A CN 201410232646 A CN201410232646 A CN 201410232646A CN 103984268 A CN103984268 A CN 103984268A
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Abstract
The invention discloses an input and output device of a signal logic controller and the signal logic controller. The input and output device comprises an input device and/or an output device; the input device comprises N cascaded input modules; the output device comprises M cascaded output modules; each input module comprises two input sub-modules of the same structure; each input sub-module comprises a difference receiver I, a difference driver I, a difference receiver II, a shifting register I and a shifting register II; each output module comprises two output sub-modules of the same structure; each output sub-module comprises a difference receiver III, a difference driver III, a difference receiver IV, a shifting register III and a shifting register IV. According to the input and output device, expansion and modularization setting of the cascaded structure can be conveniently performed by the signal logic controller according to the IO requirement of controlled equipment, few pin sources of a central processing unit are occupied, and the use requirement for IO resources of the controlled equipment can be conveniently met.
Description
Technical field
The present invention relates to input and output control technology field, be specially a kind of input-output unit and signal logic controller of signal logic controller.
Background technology
Signal logic controller is that Crane Industry replaces PLC to realize the control electronics to input and output point information acquisition and signal controlling.At present, the input-output unit that in prior art, the signal logic controller of Crane Industry adopts is simple parallel communication structure, there are how many IO points just to connect how many parallel winding displacements, and there is no IO cascade function, make so available IO count limited, be unfavorable for field programming, take PCB fabric swatch area large simultaneously, the pin resource that takies central processor core is many, maintenance cost is high, equipment volume is large, cannot realize dexterous modular construction, and a lot of situation IO resources all can not meet user demand.
Summary of the invention
The present invention is directed to the proposition of above problem, and develop a kind of input-output unit and signal logic controller of the signal logic controller that pin resource is few, volume is little that takies central processing unit.
Technological means of the present invention is as follows:
An input-output unit for signal logic controller, described signal logic controller comprises central processing unit, and is connected with the controlled device with input port and output port, comprising:
Input media and/or output unit; Described input media one end connects controlled device output port, and the other end connects central processing unit; Described output unit one end connects central processing unit, and the other end connects controlled device input port;
Described input media comprises the load module of N cascade, and wherein N is integer;
Described output unit comprises the output module of M cascade, and wherein M is integer;
Each load module includes two input submodules that structure is identical; Described input submodule comprises:
Be used for the differential receiver I that receives difference control signal and described difference control signal is converted to single-ended control signal;
Connect differential receiver I, for the single-ended control signal of differential receiver I output being converted to the differential driver I of difference control signal;
Be used for the differential receiver II that receives differential data signals and described differential data signals is converted to single-ended data-signal;
Shift register I and shift register II that parallel input end is connected with controlled device output port; Described shift register I seals in control end with being incorporated to of shift register II and is connected with the output terminal of described differential receiver I with input end of clock; The serial input terminal of described shift register I connects the output terminal of described differential receiver II; The serial input terminal of described shift register II connects the serial output terminal of described shift register I; The serial output terminal of described shift register II connects differential driver II;
Be used for the differential driver II that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals;
Each output module includes two output sub-modules that structure is identical; Described output sub-module comprises:
Be used for the differential receiver III that receives difference control signal and described difference control signal is converted to single-ended control signal;
Connect differential receiver III, for the single-ended control signal of differential receiver III output being converted to the differential driver III of difference control signal;
Be used for the differential receiver IV that receives differential data signals and described differential data signals is converted to single-ended data-signal;
The shift register III that parallel output terminal is connected with controlled device input port and shift register IV; Described shift register III and shift register IV and go out to go here and there out control end and be connected with the output terminal of described differential receiver III with input end of clock; The serial input terminal of described shift register III connects the output terminal of described differential receiver IV; The serial input terminal of described shift register IV connects the serial output terminal of described shift register III; The serial output terminal of described shift register IV connects differential driver IV;
Be used for the differential driver IV that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals;
The input end of the differential receiver I that the input submodule of N level comprises connects described central processing unit, and the input end of the differential receiver I that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver I that next stage input submodule comprises successively; The input end of the differential receiver II that the input submodule of the first order comprises is unsettled, the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver II that upper level input submodule comprises successively, and the output terminal of the differential driver II that the input submodule of N level comprises connects described central processing unit;
The input end of the differential receiver III that the output sub-module of the first order comprises connects described central processing unit, and the input end of the differential receiver III that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver III that upper level output sub-module comprises successively; The input end of the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit, the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver IV that upper level output sub-module comprises successively, and the output terminal of the differential driver IV that the output sub-module of M level comprises is unsettled;
Further, described shift register I and shift register II adopt 74HC165 chip;
Further, described shift register III and shift register IV adopt 74HC594 chip;
Further, described differential receiver I, differential receiver II, differential receiver III and differential receiver IV adopt 26LS32 chip;
Further, described differential driver I, differential driver II, differential driver III and differential driver IV adopt 26LS31 chip;
Further, the output terminal of the differential driver II that the input submodule of N level comprises connects central processing unit by Shielded Twisted Pair, and the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises all connects the output terminal of the differential driver II that upper level input submodule comprises by Shielded Twisted Pair;
Further, the input end of the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit by Shielded Twisted Pair, and the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises all connects the output terminal of the differential driver IV that upper level output sub-module comprises by Shielded Twisted Pair;
Further, the parallel output terminal of described shift register III and shift register IV is connected with controlled device input port by outputting circuit for relay;
The output terminal of the differential driver II that further, the input submodule of N level comprises connects described central processing unit by triggering phase inverter.
A kind of signal logic controller, comprises the input-output unit described in above-mentioned any one; N 2N included input submodule of load module forms two-way input cascade structure; M 2M included output sub-module of output module forms two-way output cascade structure; Whether the data-signal that described central processing unit is also inputted cascade structure input to controlled device by two-way unanimously compares, when inconsistent described in central processing unit produce warning message.
Owing to having adopted technique scheme, the input-output unit of a kind of signal logic controller provided by the invention and signal logic controller, comprise the input media and/or the output unit that adopt cascade structure, be convenient to signal logic controller and can need to carry out according to the actual IO of controlled device expansion and the modularization setting of cascade structure, the pin resource that takies central processing unit is few, can meet easily the user demand of controlled device to IO resource, applying flexible, structure is small and exquisite, be beneficial to field programming, have more the market competitiveness, having solved the input-output unit that in prior art, signal logic controller adopts is simple parallel communication structure, and then make the available IO limited problem of counting.
Brief description of the drawings
Fig. 1 is the structured flowchart of the input-output unit of signal logic controller of the present invention;
Fig. 2 is the structured flowchart of load module of the present invention;
Fig. 3 is the structured flowchart of output module of the present invention;
Fig. 4 is the structured flowchart of signal logic controller of the present invention.
Embodiment
The input-output unit of a kind of signal logic controller as shown in Figure 1 to Figure 3, described signal logic controller comprises central processing unit, and is connected with the controlled device with input port and output port, comprising: input media and/or output unit; Described input media one end connects controlled device output port, and the other end connects central processing unit; Described output unit one end connects central processing unit, and the other end connects controlled device input port; Described input media comprises the load module of N cascade, and wherein N is integer; Described output unit comprises the output module of M cascade, and wherein M is integer; Each load module includes two input submodules that structure is identical; Described input submodule comprises: for receiving difference control signal and described difference control signal being converted to the differential receiver I of single-ended control signal; Connect differential receiver I, for the single-ended control signal of differential receiver I output being converted to the differential driver I of difference control signal; Be used for the differential receiver II that receives differential data signals and described differential data signals is converted to single-ended data-signal; Shift register I and shift register II that parallel input end is connected with controlled device output port; Described shift register I seals in control end with being incorporated to of shift register II and is connected with the output terminal of described differential receiver I with input end of clock; The serial input terminal of described shift register I connects the output terminal of described differential receiver II; The serial input terminal of described shift register II connects the serial output terminal of described shift register I; The serial output terminal of described shift register II connects differential driver II; Be used for the differential driver II that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals; Each output module includes two output sub-modules that structure is identical; Described output sub-module comprises: for receiving difference control signal and described difference control signal being converted to the differential receiver III of single-ended control signal; Connect differential receiver III, for the single-ended control signal of differential receiver III output being converted to the differential driver III of difference control signal; Be used for the differential receiver IV that receives differential data signals and described differential data signals is converted to single-ended data-signal; The shift register III that parallel output terminal is connected with controlled device input port and shift register IV; Described shift register III and shift register IV and go out to go here and there out control end and be connected with the output terminal of described differential receiver III with input end of clock; The serial input terminal of described shift register III connects the output terminal of described differential receiver IV; The serial input terminal of described shift register IV connects the serial output terminal of described shift register III; The serial output terminal of described shift register IV connects differential driver IV; Be used for the differential driver IV that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals; The input end of the differential receiver I that the input submodule of N level comprises connects described central processing unit, and the input end of the differential receiver I that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver I that next stage input submodule comprises successively; The input end of the differential receiver II that the input submodule of the first order comprises is unsettled, the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver II that upper level input submodule comprises successively, and the output terminal of the differential driver II that the input submodule of N level comprises connects described central processing unit; The input end of the differential receiver III that the output sub-module of the first order comprises connects described central processing unit, and the input end of the differential receiver III that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver III that upper level output sub-module comprises successively; The input end of the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit, the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver IV that upper level output sub-module comprises successively, and the output terminal of the differential driver IV that the output sub-module of M level comprises is unsettled; Further, described shift register I and shift register II adopt 74HC165 chip; Further, described shift register III and shift register IV adopt 74HC594 chip; Further, described differential receiver I, differential receiver II, differential receiver III and differential receiver IV adopt 26LS32 chip; Further, described differential driver I, differential driver II, differential driver III and differential driver IV adopt 26LS31 chip; Further, the output terminal of the differential driver II that the input submodule of N level comprises connects central processing unit by Shielded Twisted Pair, and the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises all connects the output terminal of the differential driver II that upper level input submodule comprises by Shielded Twisted Pair; Further, the input end of the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit by Shielded Twisted Pair, and the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises all connects the output terminal of the differential driver IV that upper level output sub-module comprises by Shielded Twisted Pair; Further, the parallel output terminal of described shift register III and shift register IV is connected with controlled device input port by outputting circuit for relay; The output terminal of the differential driver II that further, the input submodule of N level comprises connects described central processing unit by triggering phase inverter; Described triggering phase inverter adopts 74HC14 chip.
A kind of signal logic controller as shown in Figure 1 and Figure 4, comprises the input-output unit described in above-mentioned any one, N 2N included input submodule of load module forms two-way input cascade structure, M 2M included output sub-module of output module forms two-way output cascade structure, whether the data-signal that described central processing unit is also inputted cascade structure input to controlled device by two-way unanimously compares, when inconsistent described in central processing unit produce warning message, as shown in Figure 4, signal logic controller of the present invention is except comprising central processing unit, input media, outside output unit, also comprise the analog input differential receiver being connected with central processing unit, analog quantity control differential driver, scrambler input difference receiver, watchdog circuit, ferroelectric memory, peripheral storage, JTAG emulation interface, AS DLL (dynamic link library), key circuit, LCD shows and backlight lamp control circuit and PIC single-chip microcomputer, and the master station communication unit being connected with PIC single-chip microcomputer, slave station communication unit, BCD address dial-up circuit, PIC32 download interface and watchdog circuit etc.
The present invention can offer central processing unit as collection in worksite information is converted to high-speed serial data by the parallel data of controlled device output port output by described input media, the serial data that simultaneously central processing unit can be sent by described output unit is converted to parallel data control controlled device as steering order information, N load module cascade, each load module comprises two input submodules that structure is identical, and then formation two-way input cascade structure, two-way input cascade structure redundancy structure each other, M output module cascade, each output module comprises two output sub-modules that structure is identical, and then formation two-way output cascade structure, two-way output cascade structure redundancy structure each other, wherein N and M are integer, specifically can be according to actual design requirements set, described central processing unit moves completely independently input and output point scanning sequence of two covers simultaneously, and whether the data-signal that controlled device is inputted to cascade structure input by two-way unanimously compares, described in when inconsistent, central processing unit produces warning message, the data-signal sending is also two-way signal, so that through logic and operation, jointly guarantee to export correct duty, play the effect of protection system safety and increase reliability.
The present invention can be applied to Crane Industry, realizes signal high speed serial communication and cascade control between this controlled device of signal logic controller and crane system; Described shift register I is connected with the output port of controlled device by input point testing circuit with shift register II; Described shift register III is connected with the input port of controlled device by outputting circuit for relay with shift register IV.
Set input point (being connected controlled device output port) the You16 road of each load module, output point (being connected controlled device input port) the You16 road of each output module, when the IO scan period need to be controlled at 0.1ms with interior situation under, each 5 of the load module of every signal logic controller and output module, input media and output unit can be realized respectively 80 way switch amount inputs, information acquisition and the logic control function of 80 way switch amount outputs, as need the more IO input/output modules of cascade, one of every increase, the IO scan period extends and is less than 20us, be 0.02ms, further input media and output unit are realized 16*N way switch amount input signal, signals collecting and the logic control function of 16*M way switch amount output signal, signal logic controller can carry out modular arrangements to input media and output unit according to actual input and output point quantity, to meet input and output needs separately, simultaneously, the present invention carries out in the process of signal transmission at input media, output unit and central processing unit and controlled device, adopt differential signal transmission mode can reduce the various interference of site environment to signal logic controller, and then strengthen the reliability of signal transmission.
When practical application, the present invention forms between each input submodule of input cascade structure, and can adopt DB socket to be connected with plug between each output module of formation output cascade structure, use corresponding fixture to strengthen the stability of connector simultaneously, in addition for preventing wrong plug, between different load modules and can use respectively DB socket and the plug of different numbers between different output module.In the selection of transmission cable, adopt the pair cable differential signal transmission on band shielding ground.
By the structure of input media of the present invention, controlled device output port is connected with the load module of each cascade, for first order input submodule (i.e. the included arbitrary input submodule of load module 1 in figure), the parallel data of controlled device output port is converted to serial data by shift register I, and reach shift register II in the mode of serial, the parallel data that the controlled device output port that shift register II can timesharing receives its parallel input end transmits is converted to serial data and is exported by serial output terminal, and the serial data of the shift register I output that its serial input terminal is received is exported by serial output terminal, the serial data of output is transformed to corresponding differential data signals via differential driver II and transfers to second level input submodule (i.e. the included input submodule of load module 2 in figure), the parallel data that the controlled device output port that shift register I in second level input submodule to the N level input submodule all can timesharing receives its parallel input end transmits is converted to serial data and is exported by serial output terminal, and the serial data of the upper level input submodule output that its serial input terminal is received is exported by serial output terminal, and by serial data transmission to shift register II, shift register II function in second level input submodule to the N level input submodule is identical with the shift register II function in first order input submodule, after being transformed to differential data signals by differential driver II in N level input submodule, the serial data of reception is transferred to central processing unit, the input end of the differential receiver I that the input submodule of N level comprises connects described central processing unit, realize the time clock of shifting function and be incorporated to and seal in control signal for controlling shift register I and shift register II for what receive that central processing unit sends over, described be incorporated to seal in control signal for control to input parallel data or serial data be shifted, the time clock here and be incorporated to that to seal in control signal are all differential signal forms, differential receiver I seals in control signal by the time clock of differential signal form and being incorporated to and is converted to corresponding single-ended signal and is transferred to respectively shift register I, shift register II and differential driver I, shift register I and shift register II seal in control signal according to the time clock and being incorporated to receiving and complete to be incorporated to and go here and there out or seal in the shifting function of going here and there out, differential driver I seals in control signal by the time clock of single-ended signal form and being incorporated to and is converted to differential signal form and is transferred to N-1 level input submodule, the input end of the differential receiver I that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver I that next stage input submodule comprises successively, for receiving the shift control signal transmitting from central processing unit, shift register I and being incorporated to of shift register II of each input submodule seals in the output terminal that control end and input end of clock are connected differential receiver I successively, the identical two-way input cascade structure of structure being made up of respectively 2N input submodule all adopts the above-mentioned course of work.
Central processing unit of the present invention comprises MCU or FPGA, described central processing unit can use differential received chip to receive the differential data signals that input media transmits, and be converted into single-ended data-signal, meet afterwards 74HC14 and trigger phase inverter, can convert the single-ended data-signal receiving to output signal clear, non-jitter and offer FPGA or MCU Information Monitoring.
By the structure of output unit of the present invention, controlled device input port is connected with the output module of each cascade, for first order output sub-module (i.e. the included arbitrary output sub-module of output module 1 in figure), the serial data that central processing unit sends is if steering order communication is to shift register III, the serial data that described shift register III can timesharing receives serial input terminal is converted to parallel data and is transferred to controlled device input port by parallel output terminal, and the serial data of reception is reached to shift register IV by serial output terminal in the mode of serial, the serial data that shift register IV can timesharing receives its serial input terminal is converted to parallel data and is transferred to controlled device input port by parallel output terminal, and the serial data of reception is exported by serial output terminal, the serial data of output is transformed to corresponding differential data signals via differential driver IV and transfers to second level output sub-module (i.e. the included output sub-module of output module 2 in figure), the serial data that shift register I in output sub-module to the M level output sub-module of the second level all can timesharing transmits upper level output sub-module is converted to parallel data and is transferred to controlled device input port by parallel output terminal, and the serial data that upper level output sub-module is transmitted reaches shift register IV by serial output terminal in the mode of serial, shift register IV function in output sub-module to the M level output sub-module of the second level is identical with the shift register IV function in first order output sub-module, differential driver IV in M level output sub-module (output sub-module that afterbody output module is included) is not in the time needing to continue cascade, its output terminal can be unsettled, the input end of the differential receiver III that the output sub-module of the first order comprises connects described central processing unit, for receive that central processing unit sends over for control shift register III and shift register IV realize shifting function time clock and and go out to go here and there out control signal, described and go out to go here and there out control signal for exporting parallel data or serial data, the time clock here and and to go out to go here and there out control signal are all differential signal forms, differential receiver III by the time clock of differential signal form and and go out to go here and there out control signal and be converted to corresponding single-ended signal and be transferred to respectively shift register III, shift register IV and differential driver III, shift register III and shift register IV according to the time clock receiving and and go out to go here and there out control signal and complete and seal in the shifting function of going here and there out or sealing in and going out, differential driver III by the time clock of single-ended signal form and and go out to go here and there out control signal and be converted to differential signal form and be transferred to second level output sub-module, the input end of the differential receiver III that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver III that upper level output sub-module comprises successively, for receiving the shift control signal transmitting from central processing unit, the shift register III of each output sub-module and shift register IV and go out to go here and there out control end and input end of clock and be connected successively the output terminal of differential receiver III, the identical two-way output cascade structure of structure being made up of respectively 2M output sub-module all adopts the above-mentioned course of work.
The input-output unit of a kind of signal logic controller provided by the invention and signal logic controller, comprise the input media and/or the output unit that adopt cascade structure, be convenient to signal logic controller and can need to carry out according to the actual IO of controlled device expansion and the modularization setting of cascade structure, the pin resource that takies central processing unit is few, can meet easily the user demand of controlled device to IO resource, applying flexible, structure is small and exquisite, be beneficial to field programming, have more the market competitiveness, having solved the input-output unit that in prior art, signal logic controller adopts is simple parallel communication structure, and then make the available IO limited problem of counting, the present invention both can be applicable to crane machinery industry market, also the more fixing Enterprise Equipment Management System of extensive logic control and real-time communication in can be applicable to, in addition, adopt differential signal transmission mode and utilize Shielded Twisted Pair to be convenient to reduce the various interference of site environment to signal logic controller, and then strengthening the reliability of signal transmission, each load module comprises two input submodules that structure is identical, N load module forms two-way input cascade structure, each output module comprises two output sub-modules that structure is identical, N output module forms two-way output cascade structure, strengthen the security of data transmission and processing, increase system reliability.
The above; it is only preferably embodiment of the present invention; but protection scope of the present invention is not limited to this; any be familiar with those skilled in the art the present invention disclose technical scope in; be equal to replacement or changed according to technical scheme of the present invention and inventive concept thereof, within all should being encompassed in protection scope of the present invention.
Claims (10)
1. an input-output unit for signal logic controller, described signal logic controller comprises central processing unit, and is connected with the controlled device with input port and output port, it is characterized in that comprising:
Input media and/or output unit; Described input media one end connects controlled device output port, and the other end connects central processing unit; Described output unit one end connects central processing unit, and the other end connects controlled device input port;
Described input media comprises the load module of N cascade, and wherein N is integer;
Described output unit comprises the output module of M cascade, and wherein M is integer;
Each load module includes two input submodules that structure is identical; Described input submodule comprises:
Be used for the differential receiver I that receives difference control signal and described difference control signal is converted to single-ended control signal;
Connect differential receiver I, for the single-ended control signal of differential receiver I output being converted to the differential driver I of difference control signal;
Be used for the differential receiver II that receives differential data signals and described differential data signals is converted to single-ended data-signal;
Shift register I and shift register II that parallel input end is connected with controlled device output port; Described shift register I seals in control end with being incorporated to of shift register II and is connected with the output terminal of described differential receiver I with input end of clock; The serial input terminal of described shift register I connects the output terminal of described differential receiver II; The serial input terminal of described shift register II connects the serial output terminal of described shift register I; The serial output terminal of described shift register II connects differential driver II;
Be used for the differential driver II that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals;
Each output module includes two output sub-modules that structure is identical; Described output sub-module comprises:
Be used for the differential receiver III that receives difference control signal and described difference control signal is converted to single-ended control signal;
Connect differential receiver III, for the single-ended control signal of differential receiver III output being converted to the differential driver III of difference control signal;
Be used for the differential receiver IV that receives differential data signals and described differential data signals is converted to single-ended data-signal;
The shift register III that parallel output terminal is connected with controlled device input port and shift register IV; Described shift register III and shift register IV and go out to go here and there out control end and be connected with the output terminal of described differential receiver III with input end of clock; The serial input terminal of described shift register III connects the output terminal of described differential receiver IV; The serial input terminal of described shift register IV connects the serial output terminal of described shift register III; The serial output terminal of described shift register IV connects differential driver IV;
Be used for the differential driver IV that receives single-ended data-signal and described single-ended data-signal is converted to differential data signals;
The input end of the differential receiver I that the input submodule of N level comprises connects described central processing unit, and the input end of the differential receiver I that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver I that next stage input submodule comprises successively; The input end of the differential receiver II that the input submodule of the first order comprises is unsettled, the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises connects the output terminal of the differential driver II that upper level input submodule comprises successively, and the output terminal of the differential driver II that the input submodule of N level comprises connects described central processing unit;
The input end of the differential receiver III that the output sub-module of the first order comprises connects described central processing unit, and the input end of the differential receiver III that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver III that upper level output sub-module comprises successively; The input end of the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit, the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises connects the output terminal of the differential driver IV that upper level output sub-module comprises successively, and the output terminal of the differential driver IV that the output sub-module of M level comprises is unsettled.
2. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that described shift register I and shift register II adopt 74HC165 chip.
3. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that described shift register III and shift register IV adopt 74HC594 chip.
4. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that described differential receiver I, differential receiver II, differential receiver III and differential receiver IV adopt 26LS32 chip.
5. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that described differential driver I, differential driver II, differential driver III and differential driver IV adopt 26LS31 chip.
6. the input-output unit of a kind of signal logic controller according to claim 1, the output terminal that it is characterized in that the differential driver II that the input submodule of N level comprises connects central processing unit by Shielded Twisted Pair, and the input end of the differential receiver II that the input submodule of all the other N-1 levels comprises all connects the output terminal of the differential driver II that upper level input submodule comprises by Shielded Twisted Pair.
7. the input-output unit of a kind of signal logic controller according to claim 1, the input end that it is characterized in that the differential receiver IV that the output sub-module of the first order comprises connects described central processing unit by Shielded Twisted Pair, and the input end of the differential receiver IV that the output sub-module of all the other M-1 levels comprises all connects the output terminal of the differential driver IV that upper level output sub-module comprises by Shielded Twisted Pair.
8. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that the parallel output terminal of described shift register III and shift register IV is connected with controlled device input port by outputting circuit for relay.
9. the input-output unit of a kind of signal logic controller according to claim 1, is characterized in that the output terminal of the differential driver II that the input submodule of N level comprises connects described central processing unit by triggering phase inverter.
10. a signal logic controller, is characterized in that comprising the input-output unit described in claim 1 to 9 any one; N 2N included input submodule of load module forms two-way input cascade structure; M 2M included output sub-module of output module forms two-way output cascade structure; Whether the data-signal that described central processing unit is also inputted cascade structure input to controlled device by two-way unanimously compares, when inconsistent described in central processing unit produce warning message.
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| CN201410232646.2A CN103984268B (en) | 2014-05-28 | 2014-05-28 | The input/output unit of a kind of signal logic controller and signal logic controller |
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| CN201410232646.2A CN103984268B (en) | 2014-05-28 | 2014-05-28 | The input/output unit of a kind of signal logic controller and signal logic controller |
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| CN103984268A true CN103984268A (en) | 2014-08-13 |
| CN103984268B CN103984268B (en) | 2016-11-23 |
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| CN109752992A (en) * | 2018-12-06 | 2019-05-14 | 贵州航天电子科技有限公司 | A kind of FPGA+8051 system controller |
| CN110109414A (en) * | 2019-06-12 | 2019-08-09 | 盈春 | A kind of logic controller system |
| CN117155372A (en) * | 2023-09-06 | 2023-12-01 | 苏州异格技术有限公司 | Input/output driver structure, input/output control method and communication system |
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Effective date of registration: 20181206 Address after: 116023 No. 35 Torch Road, Qixianling, Dalian High-tech Industrial Park, Liaoning Province Patentee after: MH Automation Dalian Co., Ltd. Address before: 116023 No. 35 Torch Road, Qixianling, Dalian High-tech Zone, Liaoning Province Patentee before: Dalian MH Times Technology Co., Ltd. |
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