CN103973996B

CN103973996B - A kind of clock circuit standby system of many imaging band systems of space camera

Info

Publication number: CN103973996B
Application number: CN201410186855.8A
Authority: CN
Inventors: 李丙玉; 王晓东; 曲洪丰
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2014-05-05
Filing date: 2014-05-05
Publication date: 2017-06-23
Anticipated expiration: 2034-05-05
Also published as: CN103973996A

Abstract

A kind of clock circuit standby system of many imaging band systems of space camera is related to space camera reliability design field, the system increases a crystal oscillator A dedicated for communication in each imaging band, by receiving the control command that spaceborne computer sends, the cold standby of crystal oscillator B and crystal oscillator C is realized；Switching to crystal oscillator B and crystal oscillator C and status monitoring function are realized by FPGA.The clock signal that multiple imaging bands are exported using crystal oscillator B or crystal oscillator C simultaneously produces amplitude, the powerful signals such as CCD Timing drivers, the generation for avoiding high-power, amplitude periodic signal in different imaging bands comes from the situation of different crystal oscillators, so as to avoid the generation of beat frequency interference.System of the invention improves the reliability of space camera imaging system while picture quality is not reduced.

Description

A kind of clock circuit standby system of many imaging band systems of space camera

Technical field

The invention belongs to space camera reliability design field, more particularly to a kind of many imaging band systems of space camera Clock circuit standby system.

Background technology

In the space camera that detector is spliced using multi-disc TDI-CCD, one imaging of every TDI-CCD correspondence is logical Road, each imaging band includes independent imaging controller FPGA, and multiple imaging bands constitute whole imaging system.Tradition sets In meter, in order to avoid beat frequency crosstalk occurs in ccd signal between multiple imaging bands, whole imaging system shares a clock electricity Road.By taking two panels TDI-CCD as an example, its structure is as shown in Figure 1.

Scene information is projected on the TDI-CCD that multi-disc is stitched together after optical system, every CCD correspondence one into As controller FPGA, the main Timing driver generation for completing TDI-CCD, the vision signal quantified controlling of TDI-CCD outputs are simultaneously adopted Image information packing after collection quantifies is descending.

Although this circuit structure effectively avoids the appearance of beat frequency interference noise, clock circuit becomes single-point mistake Effect trouble point.And clock circuit is the basis that all clock signals and treatment logic are capable of normal work, once go wrong must Whole imaging system will be caused to fail, imaging system reliability is low.If each imaging band uses respective clock circuit, and Imaging system will be caused beat frequency interference noise, image quality decrease occur.How backup design is carried out to clock circuit, without Beat frequency interference noise is introduced to be of great practical significance.

The content of the invention

In order to reliability is not high in solving the problems, such as traditional design mode, the present invention proposes imaging more than a kind of space camera The clock circuit standby system of channel system.The system is based on beat frequency and disturbs Producing reason, is made an uproar to beat frequency will not be caused to disturb The clock circuit of sound uses Hot Spare mode, and the clock circuit to that can cause beat frequency interference noise uses cold standby mode, by Spaceborne computer sends master/backup clock select command to switch over.On the premise of beat frequency noise is not introduced, to clock circuit Backed up, improve the reliability of system.

The technical solution used in the present invention is as follows：

A kind of clock circuit standby system of many imaging band systems of space camera, including multiple crystal oscillator A, multiple imaging controls Device FPGA processed, crystal oscillator B and crystal oscillator C；A crystal oscillator A is set in each imaging band and an imaging controller FPGA, crystal oscillator A are defeated The clock signal for going out accesses the global clock input pin X of the FPGA in this imaging band；Crystal oscillator B it is identical with crystal oscillator C frequencies but Different from crystal oscillator A frequencies, crystal oscillator B and crystal oscillator C exports clock signal, crystal oscillator B outputs when respective enable pin is high level Clock signal be respectively connected to the global clock input pin Y of FPGA in each imaging band, the clock signal point of crystal oscillator C outputs The global clock input pin Z of FPGA in each imaging band is not accessed；The enable pin of FPGA and crystal oscillator B in imaging band 1 The connection of enable pin, this FPGA controls crystal oscillator B opens or closes；The enable for enabling pin and crystal oscillator C of FPGA in imaging band 2 Pin is connected, and this FPGA control crystal oscillator C's opens or closes；The communication module of FPGA uses clock X in each imaging band, FPGA's The clock selection signal that clock selection module sends according to communication module is switched over to the clock Y and clock Z of input, selects it In all the way clock export to the CCD Timing drivers module of FPGA, ccd signal processing module and transmit module；Clock selecting Module can be also monitored to the working condition of clock Y and clock Z, and monitoring state is sent into spaceborne meter by communication module Calculation machine, and ground is gone downwards to as the judgment basis for entering row clock switching.

Beneficial effects of the present invention are as follows：

1) crystal oscillator B and crystal oscillator C same frequencys, backup each other.When wherein crystal oscillator fails all the way, can be switched to by FPGA Another road crystal oscillator, it is to avoid single point failure point, improves the reliability of system.

2) in synchronization only one in work, another is output as low level to crystal oscillator B and crystal oscillator C, in the absence of beat frequency letter Number, so as to avoid the generation of beat frequency interference, it is ensured that picture quality.

3) each imaging band introduce one for communicate clock X, the communication mould of FPGA is only used for due to clock X Block, will not in circuit introduce amplitude, powerful mechanical periodicity signal, while clock X and clock Y or clock Z is (during CCD The fundamental frequency of sequence drive signal) different frequencies, therefore beat frequency interference will not be introduced.

4) clock selection module of FPGA in the control without communication module, believe by the clock of acquiescence selection crystal oscillator B outputs Number as the modules such as CCD Timing drivers clock signal, do not interfere with the normal function of system.

Brief description of the drawings

Fig. 1 is the structural representation of existing space camera imaging system.

Fig. 2 is the structural representation of the clock circuit standby system of many imaging band systems of space camera of the present invention.

Fig. 3 is the software architecture diagram of the FPGA in the present invention.

Specific embodiment

The present invention is described in further detail with reference to the accompanying drawings and examples.

As shown in Fig. 2 by taking two imaging bands as an example, the clock circuit of many imaging band systems of space camera of the present invention is standby Part system increases a crystal oscillator A in each imaging band, and clock signal of its output is introduced into FPGA global clocks in this passage Input pin X；Two crystal oscillators are placed in circuit public area, respectively crystal oscillator B and crystal oscillator C, two crystal oscillator frequencies are identical, standby each other Part, it is different from crystal oscillator A frequencies.Two crystal oscillators have enable pin, when it is high level to enable pin, crystal oscillator output clock signal； Otherwise output signal remains low level.The clock signal of crystal oscillator B outputs is introduced into imaging band 1 and imaging band 2 respectively The clock signal of global clock input pin Y, crystal oscillator the C output of FPGA is introduced into FPGA in imaging band 1 and imaging band 2 respectively Global clock input pin Z.Imaging controller FPGA in imaging band 1 controls opening or closing for crystal oscillator B by enabling pin, Imaging controller FPGA in imaging band 2 controls opening or closing for crystal oscillator C by enabling pin.

In standby system of the invention, for the imaging controller FPGA of each imaging band, three tunnels are received simultaneously Clock signal X, Y, Z.It is five modules that the imaging controller FPGA of each imaging band is divided by function, respectively：Communication Module, clock selection module, CCD Timing drivers module, ccd signal processing module and module is transmitted, its software configuration is such as Shown in Fig. 3.Communication module uses clock X, the clock selecting that clock selection module sends according to communication module in this five modules Signal is switched over to the clock Y and clock Z that are input into, and wherein clock is exported to CCD Timing drivers module, CCD letters all the way for selection Number processing module and transmit module.The clock selection module of FPGA is in the control without communication module, and acquiescence selection is brilliant The B that shakes output clock signal as the modules such as CCD Timing driver modules clock signal.Simultaneously clock selection module can pair when The working condition of clock Y and clock Z is monitored, and monitoring state is sent into spaceborne computer by communication module, and descending To ground as the judgment basis for entering row clock switching.When necessary, can be by being artificially injected the mode of switching command, during control Clock Y and clock Z are switched over.

Embodiment：Fail-safe analysis：

Assuming that the reliability that crystal oscillator works 3 years is 0.9, then the reliability of imaging system is P=in the design of Fig. 1 0.9。

After design of the invention, what imaging system failed may be desirably combined into：

Crystal oscillator A, crystal oscillator B, crystal oscillator C fail simultaneously：Probability is 0.001；

Crystal oscillator A, crystal oscillator B fail simultaneously：Probability is 0.01；

Crystal oscillator B, crystal oscillator C fail simultaneously：Probability is 0.01；

Other time system energy normal work, then after understanding to use design of the invention, the reliability of imaging system It is P=1-0.001-0.01-0.01=0.979 to spend, and substantially increases the reliability of imaging system.

The present invention realizes the clock circuit backup to many imaging band systems of space camera by rational design, On the premise of not reducing picture quality, the reliability of imaging system is improve.

Claims

1. the clock circuit standby system of many imaging band systems of a kind of space camera, it is characterised in that the clock circuit is backed up System includes multiple crystal oscillator A, multiple imaging controller FPGA, crystal oscillator B and crystal oscillator C；One crystal oscillator A is set in each imaging band With an imaging controller FPGA, the clock signal of crystal oscillator A outputs accesses the global clock input of FPGA in this imaging band Pin X；Crystal oscillator B and crystal oscillator C frequencies are identical but different from crystal oscillator A frequencies, and crystal oscillator B and crystal oscillator C is height in respective enable pin Clock signal is exported during level, the global clock that the clock signal that crystal oscillator B is exported is respectively connected to FPGA in each imaging band is defeated Enter pin Y, the clock signal of crystal oscillator C outputs is respectively connected to the global clock input pin Z of FPGA in each imaging band；It is multiple The enable pin that FPGA in imaging band 1 is selected in imaging band is connected with the enable pin of crystal oscillator B, this FPGA control crystal oscillators B Open or close；The enable pin that FPGA in imaging band 2 is selected in multiple imaging bands is connected with the enable pin of crystal oscillator C, this FPGA control crystal oscillator C's opens or closes；The communication module of FPGA uses the clock selecting mould of clock X, FPGA in each imaging band The clock selection signal that root tuber is sent according to communication module is switched over to the clock Y and clock Z that are input into, selection wherein clock all the way Export to the CCD Timing drivers module of FPGA, ccd signal processing module and transmit module；Clock selection module can also be right The working condition of clock Y and clock Z is monitored, and monitoring state is sent into spaceborne computer by communication module, and under Row is to ground as the judgment basis for entering row clock switching.