CN103973296A - Sequential-logic-based instruction synthesis method for two cabins and instruction synthetic circuit of two cabins - Google Patents
Sequential-logic-based instruction synthesis method for two cabins and instruction synthetic circuit of two cabins Download PDFInfo
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- CN103973296A CN103973296A CN201310034327.6A CN201310034327A CN103973296A CN 103973296 A CN103973296 A CN 103973296A CN 201310034327 A CN201310034327 A CN 201310034327A CN 103973296 A CN103973296 A CN 103973296A
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Abstract
The invention belongs to the technical field of digital circuits and relates to a sequential-logic-based instruction synthesis method for two cabins and an instruction synthetic circuit of the two cabins. According to the instruction synthetic circuit of the two cabins, latter instructions are effective. The circuit judges the time of transmission of instruction input (1) and instruction input (2) and uses a newly sent instruction as synthesized instruction output. Through the sequential-logic-based instruction synthesis method for the two cabins and the instruction synthetic circuit of the two cabins, instruction transmission of the front cabin and instruction transmission of the rear cabin are not limited by the instruction state of the opposite side; after the sequential logic is applied in the method, the control principle better accords with use and cognitive habits of people.
Description
Technical field
The invention belongs to digital circuit technique field, relate to a kind of two-seat cabin instruction integrated approach and circuit thereof based on sequential logic.
Background technology
The needs of flight training and day by day complicated operational environment force aircraft to occur the form of two-seat cabin, the thereupon problem with regard to having brought two-seat cabin control command how to carry out logic synthesis.Common instruction integrated logic has two kinds at present, the first is exactly on trainer aircraft, to apply general authority mask logic, this logic is given coach with the highest control authority, make coach's instruction export the instruction output that at any time can mask student, to correct student's faulty operation; The second is to apply more logic in parallel on current domestic two-seat cabin fighter plane, this logic is by realizing two simple parallel connections of instruction of forward and backward passenger cabin, but when the problem that this way is brought is exactly forward connection, exporting 1 two instructions is output as or logic, and export 0 two outputs while oppositely disconnecting, just become and logic, must two input instructions be all finally output open command of off-state, as shown in Fig. 1 and following table.
| in1 | in2 | out |
| 1 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 1 |
| 0 | 0 | 0 |
Summary of the invention
The object of the invention is: for two-seat cabin aircraft, realize a kind of rear effective two-seat cabin instruction of instruction integrated logic that arrives, thereby forward and backward passenger cabin can be sent when needed, be effectively switched on or switched off instruction, not limited by the opposing party's command status; A kind of circuit of realizing this instruction integrated logic is provided simultaneously.
Technical scheme of the present invention is: as shown in Figure 2, a kind of after to the effective two-seat cabin instruction of instruction synthetic circuit, times that this circuit judges instruction input 1 and instruction input 2 send, and using up-to-date instruction of sending as the instruction output after comprehensive.
As shown in Figure 3, described a kind of two-seat cabin instruction synthetic circuit based on sequential logic, comprise the first d type flip flop 3, the second d type flip flop 4,3d flip-flop 5, four d flip-flop 6, the first XOR gate 7, the second XOR gate 8 and or door 9; Wherein,
The input termination instruction input 1 of the first d type flip flop 3, the input of output termination the second d type flip flop 4 of the first d type flip flop 3, the first input end of the first XOR gate 7 and or door 9 first input end, the output of zero clearing termination second XOR gate 8 of the first d type flip flop 3; The second input of output termination first XOR gate 7 of the second d type flip flop 4, the output of zero clearing termination second XOR gate 8 of the second d type flip flop 4;
The input termination instruction input 2 of four d flip-flop 6, the input of output termination 3d flip-flop 5 of four d flip-flop 6, the first input end of the second XOR gate 8 and or door the second input of 9, the output of zero clearing termination first XOR gate 7 of four d flip-flop 6; The second input of output termination second XOR gate 8 of 3d flip-flop 5, the output of zero clearing termination first XOR gate 7 of 3d flip-flop 5;
Or the output of door 9 output output order 10.
A two-seat cabin instruction integrated approach based on sequential logic, comprises the following steps:
The first step, instruction input 1 is input in two bit shift register of the first d type flip flop 3 and the second d type flip flop 4 compositions, and instruction input 2 is input in two bit shift register of 3d flip-flop 5 and four d flip-flop 6 compositions;
Second step, in two bit shift register, the first d type flip flop 3 is inputted 1 previous moment State-output to the second d type flip flop 4 by instruction, hold instruction input 1 current time state output it to the first XOR gate 7, the second d type flip flops 4 input 1 previous moment state output it to the first XOR gate 7 of holding instruction;
In two bit shift register, four d flip-flop 6 is inputted 2 previous moment State-outputs to 3d flip-flop 5 by instruction, hold instruction input 2 current time states and output it to the second XOR gate 8 and or hold instruction input 2 previous moment states output it to the second XOR gate 8 of door 9, the 3d flip-flops 5;
The 3rd step, 1 previous moment state is inputted in the first 7 pairs of XOR gate instruction and current time state compares, and result is exported to the clear terminal of 3d flip-flop 5 and four d flip-flop 6;
2 previous moment states are inputted in the second 8 pairs of XOR gate instruction and current time state compares, and result are exported to the clear terminal of the first d type flip flop 3 and the second d type flip flop 4;
The 4th step, if be not cleared, the first d type flip flop 3 is given current time State-output or door 9; If be cleared, the first d type flip flop 3 outputs 0 are given or door 9;
If be not cleared, four d flip-flop 6 is given current time State-output or door 9; If be cleared, four d flip-flop 6 outputs 0 are given or door 9;
The 5th step, or 9 pairs of the first d type flip flops 3 received of door and the output of four d flip-flop 6 carries out logic OR, using result as final output.
The invention has the beneficial effects as follows:
The present invention can make the instruction transmission in forward and backward cabin not limited by the other side's command status; Control principle after this logic of application of the present invention more meets people's the cognitive custom of use.
Accompanying drawing explanation
Fig. 1 is two-seat cabin instruction integrated logic figure in parallel;
Fig. 2 is to effective logic diagram after two-seat cabin instruction sequencing;
Fig. 3 is to effective logical circuitry after sequential.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail:
After a kind of, arrive the effective two-seat cabin instruction of instruction synthetic circuit, no matter instruction input 1 and instruction input 2 inputs is to connect or open command, the time that two-seat cabin instruction synthetic circuit decision instruction input 1 and instruction input 2 send, and using up-to-date instruction of sending as the instruction output after comprehensive.
This circuit comprise the first d type flip flop 3, the second d type flip flop 4,3d flip-flop 5, four d flip-flop 6, the first XOR gate 7, the second XOR gate 8 and or door 9; Wherein,
The input termination instruction input 1 of the first d type flip flop 3, the input of output termination the second d type flip flop 4 of the first d type flip flop 3, the first input end of the first XOR gate 7 and or door 9 first input end, the output of zero clearing termination second XOR gate 8 of the first d type flip flop 3; The second input of output termination first XOR gate 7 of the second d type flip flop 4, the output of zero clearing termination second XOR gate 8 of the second d type flip flop 4;
The input termination instruction input 2 of four d flip-flop 6, the input of output termination 3d flip-flop 5 of four d flip-flop 6, the first input end of the second XOR gate 8 and or door the second input of 9, the output of zero clearing termination first XOR gate 7 of four d flip-flop 6; The second input of output termination second XOR gate 8 of 3d flip-flop 5, the output of zero clearing termination first XOR gate 7 of 3d flip-flop 5;
Or the output of door 9 output output order 10.
This circuit is the state variation of decision instruction input only, while appointing instruction input 1 and instruction input 2 one side's instruction inputs to change, the output of its shift register can make its XOR gate output 1, thereby shielding the other side's instruction input makes the output of logical circuit only follow own current value output.
With an embodiment, the present invention is described in further detail below, this method comprises the following steps:
The first step, it is in two bit shift register forming of 0 to first d type flip flop 3 and the second d type flip flop 4 that instruction input 1 input initial condition disconnects i.e. value, and instruction input 2 input initial conditions disconnect value is 0 in two bit shift register of 3d flip-flop 5 and four d flip-flop 6 compositions;
Second step, instruction is inputted 1 state and is turned on by the disconnect, in two bit shift register, the first d type flip flop 3 is inputted 1 previous moment state by instruction, and to disconnect value be 0 to export to the second d type flip flop 4, the input 1 current time state of holding instruction connect value be 1 and output it to the first XOR gate 7, the second d type flip flops 4 hold instruction input 1 previous moment state disconnection value be 0 and output it to the first XOR gate 7;
Instruction is inputted 2 states and is remained open, in two bit shift register, four d flip-flop 6 is inputted 2 previous moment states by instruction, and to disconnect value be 0 to export to 3d flip-flop 5, the input 2 current time states of holding instruction disconnect value be 0 and output it to the second XOR gate 8 and or door 9, the 3d flip-flops 5 hold instruction input 2 previous moment states disconnections value be 0 and output it to the second XOR gate 8;
The 3rd step, the first 7 pairs of XOR gate instruction input 1 previous moment state disconnect value be 0 and the connection of current time state value be 1 to compare, and result 1 is exported to the clear terminal of 3d flip-flop 5 and four d flip-flop 6;
The second 8 pairs of XOR gate instruction input 2 previous moment states disconnect value be 0 and the disconnection of current time state value be 0 to compare, and result 0 is exported to the clear terminal of the first d type flip flop 3 and the second d type flip flop 4;
The 4th step, the first d type flip flop 3 is not cleared, and the first d type flip flop 3 connects value by current time state is 1 to export to or 9;
Four d flip-flop 6 is cleared, and four d flip-flop 6 outputs 0 are given or door 9;
The 5th step, or door 9 pairs of the first d type flip flop 3 output valves 1 and four d flip-flop 6 output valves 0 of receiving carry out logic OR, using result 1 as final output.
Known through above-mentioned analysis: after sequential, to arrive the only state variation of decision instruction input of effective logical circuit, when either party's instruction input changes, the output of its shift register can make its XOR gate output 1, thereby shielding the other side's instruction input, makes the output of logical circuit only follow own current value output.
Claims (3)
1. after, to the effective two-seat cabin instruction of an instruction synthetic circuit, it is characterized in that, the time that this circuit judges instruction input (1) and instruction input (2) send, and using up-to-date instruction of sending as the instruction output after comprehensive.
2. described a kind of two-seat cabin instruction synthetic circuit based on sequential logic as claimed in claim 1, it is characterized in that, comprise the first d type flip flop (3), the second d type flip flop (4), 3d flip-flop (5), four d flip-flop (6), the first XOR gate (7), the second XOR gate (8) and or door (9); Wherein,
The input termination instruction input (1) of the first d type flip flop (3), the input of output termination second d type flip flop (4) of the first d type flip flop (3), the first input end of the first XOR gate (7) and or the first input end of door (9), the output of zero clearing termination second XOR gate (8) of the first d type flip flop (3); The second input of output termination first XOR gate (7) of the second d type flip flop (4), the output of zero clearing termination second XOR gate (8) of the second d type flip flop (4);
The input termination instruction input (2) of four d flip-flop (6), the input of the output termination 3d flip-flop (5) of four d flip-flop (6), the first input end of the second XOR gate (8) and or the second input of door (9), the output of zero clearing termination first XOR gate (7) of four d flip-flop (6); The second input of output termination second XOR gate (8) of 3d flip-flop (5), the output of zero clearing termination first XOR gate (7) of 3d flip-flop (5); Or the output of door (9) output output order (10).
3. the two-seat cabin instruction integrated approach based on sequential logic, is characterized in that, this method comprises the following steps:
The first step, instruction input (1) is input in two bit shift register of the first d type flip flop (3) and the second d type flip flop (4) composition, and instruction input (2) is input in two bit shift register of 3d flip-flop (5) and four d flip-flop (6) composition;
Second step, in two bit shift register, the first d type flip flop (3) is given the second d type flip flop (4) by instruction input (1) previous moment State-output, hold instruction input (1) current time state output it to the first XOR gate (7), hold instruction input (1) previous moment state output it to the first XOR gate (7) of the second d type flip flop (4);
In two bit shift register, four d flip-flop (6) is given 3d flip-flop (5) by instruction input (2) previous moment State-output, hold instruction input (2) current time state and output it to the second XOR gate (8) and or door (9), hold instruction input (2) previous moment state output it to the second XOR gate (8) of 3d flip-flop (5);
The 3rd step, the first XOR gate (7) compares instruction input (1) previous moment state and current time state, and result is exported to the clear terminal of 3d flip-flop (5) and four d flip-flop (6);
The second XOR gate (8) compares instruction input (2) previous moment state and current time state, and result is exported to the clear terminal of the first d type flip flop (3) and the second d type flip flop (4);
The 4th step, if be not cleared, the first d type flip flop (3) is given current time State-output or door (9); If be cleared, the first d type flip flop (3) output 0 is given or door (9);
If be not cleared, four d flip-flop (6) is given current time State-output or door (9); If be cleared, four d flip-flop (6) output 0 is given or door (9);
The 5th step, or door (9) the first d type flip flop (3) of receiving and the output of four d flip-flop (6) are carried out to logic OR, using result as final output.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307748A (en) * | 1998-05-29 | 2001-08-08 | 埃德加·丹尼·奥尔森 | Multiple-valued logic circuit arthitecture: supplementary symmetrical logic circuit structure (SUS-LOG) |
| US20040041594A1 (en) * | 2002-09-03 | 2004-03-04 | The Regents Of The University Of California | Event driven dynamic logic for reducing power consumption |
| CN1950811A (en) * | 2004-05-13 | 2007-04-18 | 松下电器产业株式会社 | An information processing apparatus, an integrated circuit, a data transfer controlling method, a data transfer controlling program, a program storage medium, a program transmission medium and a data |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307748A (en) * | 1998-05-29 | 2001-08-08 | 埃德加·丹尼·奥尔森 | Multiple-valued logic circuit arthitecture: supplementary symmetrical logic circuit structure (SUS-LOG) |
| US20040041594A1 (en) * | 2002-09-03 | 2004-03-04 | The Regents Of The University Of California | Event driven dynamic logic for reducing power consumption |
| CN1950811A (en) * | 2004-05-13 | 2007-04-18 | 松下电器产业株式会社 | An information processing apparatus, an integrated circuit, a data transfer controlling method, a data transfer controlling program, a program storage medium, a program transmission medium and a data |
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