CN103972294A - Transverse double-diffusion metal oxide semiconductor transistor and manufacture method thereof - Google Patents
Transverse double-diffusion metal oxide semiconductor transistor and manufacture method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 19
- 150000004706 metal oxides Chemical class 0.000 title abstract description 19
- 238000009792 diffusion process Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 114
- 239000012535 impurity Substances 0.000 claims abstract description 47
- 238000000059 patterning Methods 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 25
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical class CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- 230000000694 effects Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002513 implantation Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/086—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a transverse double-diffusion metal oxide semiconductor transistor. The transverse double-diffusion metal oxide semiconductor transistor comprises a substrate, a first well region, a drain region, a second well region and a source region, wherein the substrate comprises a first conductive type impurity; the first well region with a second conductive type impurity is formed in part of the substrate; the drain region is formed in the first well region; the second well region with the first conductive type impurity is formed in part of the substrate; the source region is formed in the second well region; the source region comprises a lightly-doped source region and a heavily-doped source region which extend downwards from the upper surface of the substrate; the depth of the lightly-doped source region is greater than that of the heavily-doped source region.
Description
The application is the divisional application of the application for a patent for invention that application number is 200510126971.1, the applying date is on November 29th, 2005, denomination of invention is " transverse double-diffusing metal dioxide semiconductor transistor and manufacture method thereof ".
Technical field
The present invention relates to a kind of transverse double-diffusing metal dioxide semiconductor transistor, relate in particular to a kind of transverse double-diffusing metal dioxide semiconductor transistor with dual diffusion type source region.
Background technology
When semiconductor element more do less, drain electrode and source electrode between channel length also thereupon shorten, therefore transistorized service speed will be accelerated.But metal oxide semiconductor transistor (Metal OxideSemiconductor Transistor, MOS) channel length can not unconfinedly shorten, after channel length shortens to a certain specific degrees, various because the channel length derivative problem that diminishes just can occur, one of them is hot carrier's effect (Hot Carrier Effect).
Traditionally, the method of the solution hot carrier's effect adopting for everybody widely, approach exactly the place of raceway groove in the source electrode of original MOS and drain electrode, increase one group of more original N-type source electrode of doping level and drain electrode Wei DiNXing district, this structure is referred to as ldd structure (Lightly DopedDrain) again.Its structure and manufacture method are below described in detail in detail.
Please refer to Figure 1A～1G, it illustrates according to the transistorized manufacture method of traditional transverse double diffused metal oxide emiconductor.The manufacture method of the N-type lateral double-diffused metal-oxide-semiconductor transistor (Laterally Double-Diffused Metal Oxide Semiconductor Transistor, LDNMOS) of the present embodiment comprises the following steps.
First, provide P type substrate 110, form N-type the first well region 112 in part substrate 110, and form P type the second well region 114 in part substrate 110, as shown in Figure 3A.
Then, form multiple field oxides in the upper surface of substrate 110, multiple field oxides the first field oxide 122 and the second field oxide 124 is wherein positioned at the first well region 112, multiple field oxides the 3rd field oxide 126 and the 4th field oxide 128 is wherein positioned at the second well region 114, as shown in Figure 1B.
Then, form grid 141 on part substrate 110 and part the second field oxide 124, as shown in Figure 1 C.
Then, utilize self-registered technology (self-alignment) to form drain region in the first well region 112, and form and there is ldd structure (lightly doping drain, LDD) source area is in the second well region 114, first its detailed process comprises the following steps:, utilize photomask to form patterning photoresist layer 130 on substrate 110, patterning photoresist layer 130 has opening 132, opening 132 exposes the substrate 110 between the 3rd field oxide 126 and the first field oxide 122, as shown in Fig. 1 D.Then, carry out Implantation; See through opening 132 by N-type Impurity injection substrate 110, and form according to this lightly-doped source polar region 162 and lightly mixed drain area 152 in substrate 110, as shown in Fig. 1 D.
After removing patterning photoresist layer 130, form clearance wall (spacer) 148 in the side of grid 141, form according to this grid structure 140, as shown in Fig. 1 E.Then,, as shown in Fig. 1 F, utilize the photoresist layer 134 of identical photomask formation identical patterns on substrate 110, and carry out ion implantation technology through opening 136.Taking the grid structure 140 with clearance wall 148 as mask, by the N-type impurity of high concentration, inject substrate 110, form according to this heavy-doped source polar region 164 and heavily doped drain region 154 in substrate 110.In this technique, together with lightly mixed drain area 152 overlaps completely with heavily doped drain region 154; Lightly-doped source polar region 162 not exclusively overlaps with 164 of heavy-doped source polar regions, and lightly-doped source polar region 162 can protrude from the side of heavy-doped source polar region 164, and is positioned at the below of clearance wall 148.That is to say, source area utilizes self-registered technology to form ldd structure.
Then, after removing patterning photoresist layer 134, and p type impurity is injected to substrate 110 to form p type impurity trap 170, just completed by this transverse double-diffusing metal dioxide semiconductor transistor 100, as shown in Figure 1 G.
But ldd structure cannot effectively improve hot carrier's effect problem, cause transistorized operating voltage still to need to be controlled under some strength, otherwise can produce equally electrical breakdown (ElectricalBreakdown) problem.In the time that transistor operating voltage exceedes critical value, transverse electric field in raceway groove increases, and makes to produce in raceway groove hot electron.There is high-octane hot electron and clash into drain electrode and produce many electron hole pairs, make the charge carrier quantity that approaches drain region in raceway groove increase, be called charge carrier multiplication (CarrierMultiplication) phenomenon.The electronics producing is inhaled the size of current that increases drain electrode toward drain electrode conventionally, and portions of electronics is injected in grid oxic horizon.The hole producing will flow to substrate, and produce substrate current (substratecurrent), and another part hole is collected by source electrode, strengthens NPN phenomenon, impels more charge carrier multiplication, and electrical breakdown finally occurs.
Summary of the invention
In view of this, object of the present invention is to provide a kind of transverse double diffused metal oxide emiconductor transistor exactly, and its source region adopts dual diffusion type structure, can improve hot carrier's effect, improves by this driving voltage of source electrode.
According to the present invention, a kind of transverse double-diffusing metal dioxide semiconductor transistor is provided, comprise substrate, the first well region, drain region, the second well region and source area.Substrate has the first conductive-type impurity, and first well region with the second conductive-type impurity is arranged in part substrate.Drain region is arranged in the first well region.Second well region with the first conductive-type impurity is arranged in part substrate.Source area is arranged in the second well region, and source area comprises lightly-doped source polar region and heavy-doped source polar region, all by the upper surface of substrate to downward-extension, the degree of depth of lightly-doped source polar region is greater than heavy-doped source polar region.
According to the present invention, a kind of manufacture method of lateral double-diffused metal-oxide-semiconductor transistor is also provided, comprise the following steps: that (a) provides the substrate with the first conductive-type impurity; (b) form first well region with the second conductive-type impurity in part substrate; (c) form second well region with the first conductive-type impurity in part substrate; (d) form multiple field oxides in the upper surface of substrate, multiple field oxides the first field oxide and the second field oxide is wherein positioned at the first well region, and multiple field oxides the 3rd field oxide is wherein positioned at the second well region; (e) form grid on part substrate and part the second field oxide; (f) form drain region in the first well region; And (g) form source area in the second well region, source area comprises lightly-doped source polar region and heavy-doped source polar region, all by the upper surface of substrate to downward-extension, wherein, the degree of depth of lightly-doped source polar region is greater than the degree of depth of heavy-doped source polar region.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate accompanying drawing to be described in detail below.
Brief description of the drawings
Figure 1A～1G illustrates according to the transistorized manufacture method of traditional transverse double diffused metal oxide emiconductor.
Fig. 2 is that explanation is according to the structure chart of the transverse double-diffusing metal dioxide semiconductor transistor of the embodiment of the present invention one.
Fig. 3 A～3Q is that explanation is according to the manufacture method of the lateral double-diffused metal-oxide-semiconductor transistor of the embodiment of the present invention one.
Fig. 4 is that explanation is according to the transistorized structure chart of transverse double diffused metal oxide emiconductor of the embodiment of the present invention two.
Fig. 5 A～5I is that explanation is according to the method flow diagram that forms source area and drain region in the manufacture method of the LDMOS transistor of the embodiment of the present invention two.
Fig. 6 is the grid voltage of LDMOS and the graph of a relation of substrate current of more traditional LDMOS and the present embodiment two.
Main element symbol description
100: traditional transverse double diffused metal oxide emiconductor transistor
110: substrate
112: the first well regions
114: the second well regions
120: tetraethyl orthosilicate salt deposit
121: silicon nitride layer
121a, 121b, 121c, 121d: opening
122: the first field oxides
124: the second field oxides
126: the three field oxides
128: the four field oxides
130: patterning photoresist layer
132: opening
134: patterning photoresist layer
136: opening
140: grid structure
141: grid
148: clearance wall
149: silicon dioxide layer
150: drain region
152: lightly mixed drain area
154: heavily doped drain region
160: source area
162: lightly-doped source polar region
164: heavy-doped source polar region.
170: the first impurity traps
200: transverse double diffused metal oxide emiconductor transistor
210: substrate
212: the first well regions
214: the second well regions
220: tetraethyl orthosilicate salt deposit
221: silicon nitride layer
221a, 221b, 221c, 221d: opening
222: the first field oxides
224: the second field oxides
226: the three field oxides
228: the four field oxides
230: patterning photoresist layer
232: opening
234: patterning photoresist layer
236: opening
238: patterning photoresist layer
239: opening
240: grid structure
242: grid oxic horizon
244: polysilicon layer
246: gate salicidation metal level
248: clearance wall
249: silicon dioxide layer
250: drain region
252: lightly mixed drain area
254: heavily doped drain region
260: source area
262: lightly-doped source polar region
264: heavy-doped source polar region.
270: the first impurity traps
300: transverse double diffused metal oxide emiconductor transistor
330: patterning photoresist layer
331: the first openings
334: patterning photoresist layer
335: opening
336: the second openings
350: drain region
352: lightly mixed drain area
354: heavily doped drain region
360: source area
362: lightly-doped source polar region
364: heavy-doped source polar region.
370: the first impurity traps
Embodiment
Main concept of the present invention is to provide a kind of source configuration of transverse double-diffusing metal dioxide semiconductor transistor, adopts dual diffusion type structure (Double Diffused Drain, DDD).That is to say, source electrode comprises a lightly-doped source polar region and a heavy-doped source polar region, and wherein the degree of depth of lightly-doped source polar region is greater than the degree of depth of heavy-doped source polar region.Below enumerating several groups of embodiment is that example elaborates, and still, following word and icon only, for demonstration and explanation, can't carry out limit to wish protection range of the present invention.Protection scope of the present invention is still limited with described in claim.Below taking LDNMOS as example, but those skilled in the art be when understanding, the present invention is not limited to N-type MOS, also can be applicable to PMOS, COMS.
embodiment mono-
Please refer to Fig. 2, it illustrates according to the structure chart of the transverse double-diffusing metal dioxide semiconductor transistor of embodiments of the invention one.The transverse double-diffusing metal dioxide semiconductor transistor 200 of the present embodiment comprises substrate 210, the first well region 212, the second well region 214, multiple field oxide (FieldOxide, FOX) 222,224,226 and 228, grid structure 240, drain region 250 and source area 260.Substrate 210 has the first conductive-type impurity, and taking LDNMOS as example, substrate 210 is P type substrate.The first well region 212 has the second conductive-type impurity, for example, be N-type impurity, and is arranged in part substrate 210.The second well region 214 has the first conductive-type impurity, for example, be p type impurity, and is arranged in part substrate 210.Multiple field oxides are all formed on substrate 210, and multiple field oxides the first field oxide 222 and the second field oxide 224 is wherein positioned at the first well region 212, and multiple field oxides the 3rd field oxide 226 is wherein positioned at the second well region 214.Grid structure 240 be arranged on part substrate 210 and part the second field oxide 224 on.Grid structure 240 comprises grid and clearance wall 248; Grid comprise grid oxic horizon (gate oxide) 242, polysilicon layer 244 with gate salicidation metal level 246.Grid oxic horizon 242 be formed on part substrate 210 and part the second field oxide 224 on.Polysilicon layer 244 is arranged on grid oxic horizon 242.Gate salicidation metal level 246 is arranged on polysilicon layer 244.Clearance wall (spacer) 248 is arranged at the side of grid.Drain region 250 is arranged in the first well region 212.Source area 260 is arranged in the second well region 214, and source area 260 comprises lightly-doped source polar region 262 and heavy-doped source polar region 264, all by the upper surface of substrate 210 to downward-extension, the degree of depth of lightly-doped source polar region 262 is greater than heavy-doped source polar region 264.Preferably, the width of lightly-doped source polar region 262 is greater than the width of heavy-doped source polar region 264.
Please refer to Fig. 3 A～3Q, it illustrates the transistorized manufacture method of transverse double diffused metal oxide emiconductor according to the embodiment of the present invention one.The transistorized manufacture method of transverse double diffused metal oxide emiconductor of the present embodiment, comprises the following steps.
First, provide the substrate 210 with the first conductive-type impurity, form first well region 212 with the second conductive-type impurity in part substrate 210, and form second well region 214 with the first conductive-type impurity in part substrate 210, as shown in Figure 3A.
Then, form multiple field oxides in the upper surface of substrate 210, multiple field oxides the first field oxide and the second field oxide is wherein positioned at the first well region, and multiple field oxides the 3rd field oxide is wherein positioned at the second well region.For instance, the step that forms multiple field oxides comprises: first, form tetraethyl orthosilicate salt (Tetraethylorthosilicate, TEOS) layer 220 on substrate 210.Afterwards, form silicon nitride layer (Si
3n
4) 221 on tetraethyl orthosilicate salt deposit 220, as shown in Figure 3 B.Then, patterned sin layer 220, makes silicon nitride layer 220 at least have three opening 221a, 221b and 221c, to expose tetraethyl orthosilicate salt deposit 220.Opening 221a in three openings and 221b are positioned at first remaining opening 221c of well region 212, three openings and are positioned at the second well region 214, as shown in Figure 3 C.Preferably silicon nitride layer 220 has the 4th opening 221d, is positioned at the second well region 214, as shown in Figure 3 C.Then, whole substrate 210 is sent in oxidation boiler tube, tetraethyl orthosilicate salt deposit 220 carries out the growth of field oxide in the environment that contains aqueous vapor.Afterwards, in three opening 221a, 221b and 221c, grow the first field oxide 222, the second field oxide 224 and the 3rd field oxide 226 on substrate 210, preferably comprise the 4th field oxide 228, as shown in Figure 3 D.Multiple field oxides the first field oxide 222 and the second field oxide 224 is wherein positioned at the first well region 212, and multiple field oxides the 3rd field oxide 226 and the 4th field oxide 228 is wherein positioned at the second well region 214.Finally, remove silicon nitride layer 221 and tetraethyl orthosilicate salt deposit 220, as shown in Fig. 3 E.
Then, form grid on part substrate and part the second field oxide.For instance, first the step that forms grid can comprise the following steps:, form a grid oxic horizon 242 on substrate 210 and multiple field oxide 222,224,226 and 228, then, form successively polysilicon layer 244 on grid oxic horizon 242, and form gate salicidation metal level 246 on polysilicon layer 244, as shown in Fig. 3 F.Finally, patterning grid metal silicide layer 246, polysilicon layer 244 and grid oxic horizon 242, and form according to this grid.And grid is covered on part substrate 210 and part the second field oxide 224, as shown in Fig. 3 G.
Then, form drain region in the first well region, and form source area in the second well region, source area comprises lightly-doped source polar region and heavy-doped source polar region, all by the upper surface of substrate to downward-extension, wherein, the degree of depth of lightly-doped source polar region is greater than the degree of depth of heavy-doped source polar region.Preferably, forming drain region and source area for example comprises the following steps.First, utilize photomask to form patterning photoresist layer 230 on substrate 210, patterning photoresist layer 230 has opening 232, opening 232 expose the 3rd field oxide 226 with and grid between substrate 210, as shown in Fig. 3 H.Preferably, opening 232 exposes the substrate 210 between the 3rd field oxide 226 and the first field oxide 222.Then, see through opening 232 and carry out Implantation with the first particular energy, and form according to this lightly-doped source polar region 262 in substrate 210, as shown in Fig. 3 I.Utilizing grid structure 240 and field oxide 222,224 and 226 is mask, by the second conductive-type impurity of low concentration, for example, is N-type impurity, injects substrate 210.Preferably, form lightly mixed drain area 252 in substrate 210 simultaneously.Then, remove patterning photoresist layer 230, as shown in Fig. 3 J.Then, deposit silicon dioxide layer 249, on substrate 210, as shown in Fig. 3 K, and forms clearance wall 248 in the side of grid through anisotropic etching (Anisotropic Etch) afterwards, forms according to this grid structure 240, as shown in Fig. 3 L.Then, utilize identical photomask to form patterning photoresist layer 234 on substrate 210, patterning photoresist layer 234 has opening 236, and opening 236 exposes the substrate 210 between the 3rd field oxide 226 and clearance wall 248, as shown in Fig. 3 M.Preferably, opening 236 also exposes the substrate 210 between the 3rd field oxide 226 and the first field oxide 222.Finally, see through opening 236 and carry out ion implantation technology with the second particular energy, and form according to this heavy-doped source polar region 264 in substrate 210, as shown in Fig. 3 N.Utilizing grid structure 240 and field oxide 222,224 and 226 is mask, by the second conductive-type impurity of high concentration, for example, is N-type impurity, injects substrate 210.Preferably, form heavily doped drain region 254 in substrate 210 simultaneously.Should be noted, the first particular energy is greater than the second particular energy, and by this, the degree of depth of heavy-doped source polar region 254 is less than the degree of depth of lightly-doped source polar region 252.The manufacture method of the present embodiment is only utilized photomask one, and the energy while coordinating Implantation changes, and can produce dual diffusion type drain electrode structure (Double-Diffused Drain, DDD).
Then, remove patterning photoresist layer 234, as shown in Fig. 3 O.Then, utilize another photomask to form patterning photoresist layer 238, patterning photoresist layer 238 has opening 239 to expose the substrate 210 between the 3rd field oxide 226 and the 4th field oxide 228, as shown in Fig. 3 P.Then, by the first conductive-type impurity, for example, be p type impurity, inject substrate 210 to form the first impurity trap 270.Finally remove patterning photoresist layer 238, by this, complete transverse double diffused metal oxide emiconductor transistor 200, as shown in Fig. 3 Q.
embodiment bis-
Transverse double diffused metal oxide emiconductor transistor AND gate above-described embodiment of the present embodiment difference structurally is only source area and drain region, and its process is also different.In the present embodiment, structure same as the previously described embodiments also adopts identical label.
Please refer to Fig. 4, it illustrates the transistorized structure chart of transverse double diffused metal oxide emiconductor according to embodiments of the invention two.The transverse double-diffusing metal dioxide semiconductor transistor 300 of the present embodiment comprises substrate 210, the first well region 212, the second well region 214, multiple field oxide 222,224,226 and 228, grid structure 240, drain region 350 and source area 360.Drain region 350 is arranged in the first well region 212.Source area 360 is arranged in the second well region 214, and source area 360 comprises lightly-doped source polar region 362 and heavy-doped source polar region 364, all by the upper surface of substrate 210 to downward-extension, the degree of depth of lightly-doped source polar region 362 is greater than heavy-doped source polar region 364.Preferably, the width of lightly-doped source polar region 362 is greater than the width of heavy-doped source polar region 364.
Preferably, the 3rd field oxide 226 and heavy-doped source polar region 364 spacing of being separated by.More preferably, grid structure 240 also with heavy-doped source polar region 364 spacing of being separated by.
The manufacture method of the LDMOS transistor of the present embodiment comprises many steps, is to form the step of drain region and source area with the difference of above-described embodiment.Describe for the step that forms drain region and source area below.Please refer to Fig. 5 A～5I, it illustrates according to the flow chart that forms the method for source area and drain region in the manufacture method of the LDMOS transistor of embodiments of the invention two.
First, provide substrate 210, substrate 210 has the first well region 212 and the second well region 214, the first well regions have the first field oxide 222 and the second field oxide 224, the second well regions have the 3rd field oxide 226 and the 4th field oxide 228, as shown in Figure 5A.On substrate 210, have grid, be formed on part substrate 210 and part the second field oxide 224, grid comprises grid oxic horizon 242, polysilicon layer 244 and gate pole metal silicified layer 266.
Then, utilize the first photomask to form patterning photoresist layer 330 on substrate 210, patterning photoresist layer 330 has the first opening 331, the first openings 331 and exposes the substrate 210 between the 3rd field oxide 226 and grid, as shown in Figure 5 B.
Then, seeing through the first opening 331 utilizes Implantation to form lightly-doped source polar region 362 in substrate 210, as shown in Figure 5 C.Utilizing grid and the 3rd field oxide 226 is mask, by the second conductive-type impurity of low concentration, for example, is N-type impurity, injects substrate 210.
Then, remove patterning photoresist layer 330, as shown in Figure 5 D.
Then, deposit silicon dioxide layer, on substrate 210, and through forming clearance wall 248 in the side of grid after anisotropic etching, and forms grid structure 240, as shown in Fig. 5 E according to this.
Then, utilize the second photomask to form patterning photoresist layer 334 on substrate 210, patterning photoresist layer 334 has the second opening 336, as shown in Fig. 5 F.The second opening 336 only exposes the part substrate 210 between the 3rd field oxide 226 and clearance wall 248.Preferably, patterning photoresist layer 334 also has another opening 335, exposes the substrate 210 between the first field oxide 222 and the second field oxide 224.Referring to Fig. 5 B and Fig. 5 F, the width X2 of the second opening 336 is less than the width X1 of the first opening 331.
Then, seeing through the second opening 336 utilizes Implantation to form heavy-doped source polar region 364 in substrate 210, as shown in Fig. 5 G.Utilizing patterning photoresist layer 334 for mask, by the second conductive-type impurity of high concentration, for example, is N-type impurity, injects substrate 210, to form heavy-doped source polar region 364.Preferably, see through another opening 235 utilizes Implantation to form heavily doped drain region 350 in substrate 210, as shown in Fig. 5 G simultaneously.Utilizing the first field oxide 222 and the second field oxide 224 is mask, by the second conductive-type impurity of high concentration, for example, is N-type impurity, injects substrate 210, to form heavily doped drain region 350.
Finally, as shown in Fig. 5 H, remove patterning photoresist layer 334.Should be noted, in Fig. 5 H, the degree of depth of heavy-doped source polar region 364 is less than the degree of depth of lightly-doped source polar region 362, and the width of heavy-doped source polar region 364 is less than the width of lightly-doped source polar region 362.Preferably, the 3rd field oxide 326 and heavy-doped source polar region 364 spacing of being separated by.More preferably, grid structure 240 also with heavy-doped source polar region 364 spacing of being separated by.
Follow-up is for example p type impurity through by the first conductive-type impurity, injects substrate 210 to form the first impurity trap 270.Finally remove patterning photoresist layer 238, complete by this transverse double-diffusing metal dioxide semiconductor transistor 300, as shown in Fig. 5 I.
Below for the electrical characteristic of the LDMOS of several groups of Comparison of experiment results tradition LDMOS and embodiment bis-.
test one---the graph of a relation of substrate current and grid voltage
The experiment purpose of this experiment is the useful life of test transistor, and common method of testing is the size of test substrate electric current.Betide in substrate because one of them key character of hot carrier's effect is a large amount of electric currents, and powerful substrate current is generally and reduces electrical characteristic, consume element, the main cause of reduction of service life.In this experiment, with a grid voltage (V who increases gradually
g) drive LDMOS, measure substrate current size, as the index of prediction hot carrier's effect simultaneously.Wherein, drain voltage is fixed as 22 volts, and source voltage is fixed as 0 volt, tests respectively the LDMOS of traditional LDMOS and the present embodiment two, and experimental result explanation is compared as follows.Please refer to Fig. 6, it illustrates the grid voltage of LDMOS and the graph of a relation of substrate current of more traditional LDMOS and the present embodiment two.Transverse axis is grid voltage, and the longitudinal axis is substrate current, and solid line indicates the empirical curve of embodiment bis-, and dotted line indicates the empirical curve of traditional LDMOS.As seen from the figure, traditional LDMOS can produce 1.3 × 10 at most
-4the electric current of A, and the LDMOS of the present embodiment two only produces 1.0 × 10 under same case
-4the electric current of A, can obviously improve the problem of hot carrier's effect.
Say further, just because of improved hot carrier's effect, we can increase the operating voltage of the LDMOS of the present embodiment two, the application of enlarged elements.For instance, be limited to the upper limit of operating voltage, the source terminal of traditional LDMOS connects 0 volt conventionally, as just the use of ground connection.And the voltage strength that the source terminal of the present embodiment two can utilize the distance control between heavy-doped source polar region and lightly-doped source polar region to tolerate, the spacing between heavy-doped source polar region and lightly-doped source polar region is larger, and the voltage that can tolerate is higher.Thus, the source terminal of the present embodiment two can tolerate higher voltage, is preferably greater than 12 volts, therefore can be applied to power integrated circuit (Power IC).
Disclosed transverse double diffused metal oxide emiconductor transistor (LDMOS) and the manufacture method thereof of the above embodiment of the present invention has advantages of following.Transverse double diffused metal oxide emiconductor transistor of the present invention has the drain region of two-step diffusion (Double-Diffused Drain, DDD), can effectively reduce substrate current, obviously improves the problem of hot carrier's effect.In addition, due to the improvement of electrical characteristic, the operating voltage of LDMOS of the present invention can improve, the application of enlarged elements.
In sum, although the present invention discloses as above with preferred embodiment, be not for limiting the present invention, any those skilled in the art, in the situation that not deviating from spirit and scope of the invention, can do various changes and retouching.Therefore protection scope of the present invention is when being as the criterion depending on the claim person of defining.
Claims (6)
1. a transverse double-diffusing metal dioxide semiconductor transistor, it comprises:
One substrate, has one first conductive-type impurity;
One has one first well region of the second conductive-type impurity, is arranged in this substrate of part;
One drain region, is arranged in this first well region;
There is one second well region of the first conductive-type impurity, be arranged in this substrate of part;
One source pole district, is arranged in this second well region, and this source area comprises a lightly-doped source polar region and a heavy-doped source polar region, all by a upper surface of this substrate to downward-extension, the degree of depth of this lightly-doped source polar region is greater than this heavy-doped source polar region;
Multiple field oxides, all be formed on this substrate, described multiple field oxide one first field oxide and one second field oxide is wherein positioned at this first well region, described multiple field oxide one the 3rd field oxide is wherein positioned at this second well region, wherein, this lightly-doped source polar region contacts the 3rd field oxide and separates the 3rd field oxide and this heavy-doped source polar region, and an impurity trap separates by the 3rd field oxide and this source area; And
One grid structure, is arranged on this substrate of part and on this second field oxide of part, and this grid structure comprises a grid, and this lightly-doped source polar region is positioned at outside the drop shadow spread of this grid on this substrate.
2. transverse double-diffusing metal dioxide semiconductor transistor as claimed in claim 1, wherein, the width of this lightly-doped source polar region is greater than the width of this heavy-doped source polar region.
3. transverse double-diffusing metal dioxide semiconductor transistor as claimed in claim 1, wherein, this grid structure also comprises a clearance wall, and this clearance wall is arranged at the side of this grid, and this grid comprises:
One grid oxic horizon, is formed on this substrate of this top, channel region, and on this second field oxide of part;
One polysilicon layer, is arranged on this grid oxic horizon; And
One metal silicide layer, is arranged on this polysilicon layer.
4. transverse double-diffusing metal dioxide semiconductor transistor as claimed in claim 3, wherein, this grid structure and this heavy-doped source polar region spacing of being separated by.
5. a manufacture method for transverse double-diffusing metal dioxide semiconductor transistor, comprises the following steps:
One substrate with one first conductive-type impurity is provided;
Formation has one first well region of one second conductive-type impurity in this substrate of part;
Formation has one second well region of this first conductive-type impurity in this substrate of part;
Form multiple field oxides in a upper surface of this substrate, described multiple field oxides one first field oxide and one second field oxide is wherein positioned at this first well region, and described multiple field oxides one the 3rd field oxide is wherein positioned at this second well region;
Form a grid on this substrate of part and this second field oxide of part;
Form a drain region in this first well region; And
Form one source pole district in this second well region, this source area comprises a lightly-doped source polar region and a heavy-doped source polar region, all by a upper surface of this substrate to downward-extension, wherein, this lightly-doped source polar region contacts the 3rd field oxide and separates the 3rd field oxide and this heavy-doped source polar region, the degree of depth of this lightly-doped source polar region is greater than the degree of depth of this heavy-doped source polar region, and this lightly-doped source polar region is positioned at outside the drop shadow spread of this grid on this substrate.
6. method as claimed in claim 5, wherein, the step that forms described multiple field oxides comprises:
Form a tetraethyl orthosilicate salt deposit on this substrate;
Form a silicon nitride layer on this tetraethyl orthosilicate salt deposit;
This silicon nitride layer of patterning, makes this silicon nitride layer have three openings, this three opening wherein two be positioned at this first well region, this three opening all the other one of be positioned at this second well region;
In this three opening, grow this first field oxide, this second field oxide and the 3rd field oxide on this substrate; And
Remove this silicon nitride layer and this tetraethyl orthosilicate salt deposit.
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