CN103972082A - Method for preventing pattern loss and wafer manufacturing method capable of preventing pattern loss - Google Patents
Method for preventing pattern loss and wafer manufacturing method capable of preventing pattern loss Download PDFInfo
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- CN103972082A CN103972082A CN201310036476.6A CN201310036476A CN103972082A CN 103972082 A CN103972082 A CN 103972082A CN 201310036476 A CN201310036476 A CN 201310036476A CN 103972082 A CN103972082 A CN 103972082A
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- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical Vapour Deposition (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention discloses a method for preventing pattern loss, and particularly relates to a method for preventing a mask layer from pattern loss. The method sequentially includes growing a polysilicon layer on one surface of a wafer; forming the mask layer on the surface of the polysilicon layer; forming a protecting layer of more than 4000 angstroms in thickness on the mask layer formed on the surface of the polysilicon layer; removing redundant mask layer; removing the protecting layer. The invention further provides a wafer manufacturing method capable of preventing pattern loss. The wafer manufacturing method sequentially includes growing a polysilicon layer on one surface of a wafer; forming a mask layer on the polysilicon layer; forming a protecting layer of 4000 angstroms in thickness on the mask layer; removing the mask layer on the back of the wafer; removing the protecting layer; etching the wafer to form a circuit pattern. By the method and the wafer manufacturing method, the problem of pattern loss, especially pattern loss of the mask layer, is solved scientifically and effectively while process time and production cost are not increased.
Description
Technical field
The present invention relates to semiconductor making method, relate in particular to a kind of method that prevents pattern disappearance.
Background technology
Polysilicon step is the important step of chip manufacturing proces; as shown in Figure 1; in the prior art; this process is included in the upper growing polycrystalline silicon layers 102 in wafer 101 1 surface, then diffuses to form mask layer 103,103 ', regrowth protective layer 104; remove the unwanted mask layer 103 ' of wafer rear; remove again protective layer 104, finally carry out the etching/photoetching of mask layer and polysilicon layer, form circuit pattern.As shown in Figure 1, mask layer wherein 103,103 ' is taking silicon nitride (SiN) as example, and protective layer 104 is with silica (SiO
2) describe for example.
In step S1, on a surface of wafer 101, form polysilicon layer 102, become the back side of wafer 101 with respect to the opposite side of polysilicon layer.
In step S2, adopt the method for boiler tube diffusion (Diffusion) to generate silicon nitride mask layer 103,103 ', here, the thickness of the silicon nitride of formation is 1400-1600 dust.The effect of silicon nitride mask layer is for the photoetching of polysilicon layer provides anti-reflection layer, and its part covering is not etched, and etching its do not have chlamydate part, thereby form required circuit pattern.Because the feature of boiler tube growth is all to generate silicon nitride at the front and back of wafer 101, and the silicon nitride at the back side is unwanted, can produce unnecessary stress, so need to remove.Therefore, need to form protective layer on the surface of the front of required reservation silicon nitride layer 103, more unwanted back side silicon nitride layer 103 ' is removed.
In step S3, form silicon dioxide layer of protection 104 by CVD vapour deposition process on the surface of front silicon nitride layer 103.Because CVD method can only form protective layer on a surface of wafer 101, thereby, in this step, can not form protective layer at the back side of wafer 101, and expose the silicon nitride layer 103 ' that needs removal.
In following step S4, wafer 101 is carried out to pickling, remove silicon nitride 103 '.Conventionally adopt do not react with silica and only with the phosphoric acid of silicon nitride reaction as cleaning fluid, wafer is put into phosphoric acid solution to be soaked, and can remove unwanted silicon nitride layer 103 '.As above, if the silicon nitride 103 in wafer 101 fronts does not have the protection of silica 104, can together be removed at acid pickling step, this is the effect of silica just.In step S5, then remove protective layer 104.In step S6, wafer is entered to exposure and etching, form circuit pattern.
As shown in Figure 2 A and 2B, in the prior art, because CVD growing method is very easy to produce rete endoparticle (in-filmparticle) 1100, the SiO producing in existing technique
2thickness only has 2000 dusts conventionally, and larger rete endoparticle can longitudinally run through SiO
2, and contact with SiN layer, Fig. 2 A shows and in step S3 and S4, forms the endocorpuscular wafer cross section structure of rete schematic diagram.Therefore, carrying out phosphoric acid at next step washes away except SiO
2in layer time,, phosphoric acid can erode rete endoparticle, then contacts with SiN and corrodes SiN, form pattern disappearance (pattern missing), Fig. 2 B shows the photo that this rete endoparticle causes pattern disappearance, and this rete endoparticle finally causes the corrosion of SiN, even scrapping of wafer.
Therefore provide a kind of and prevent that rete endoparticle from causing the method for pattern disappearance to have very important significance.
Summary of the invention
The object of the invention is to propose a kind of method that prevents pattern disappearance, can effectively avoid pattern disappearance (pattern missing).
For reaching this object, the present invention by the following technical solutions:
A method that prevents pattern disappearance, comprises: growing polycrystalline silicon layer on a surface of wafer successively; Form mask layer on polysilicon layer surface; On the mask layer forming on polysilicon layer surface, forming thickness is protective layers more than 4000 dusts; Remove unnecessary mask layer; Remove protective layer.Wherein, the thickness of mask layer, between 4000 dust to 6000 dusts, for example, can be 4000 dusts, 4500 dusts, 5000 dusts, 5500 dusts or 6000 dusts.Mask layer is silicon nitride (SiN) layer, can be also silicon oxynitride (SiON) layer; And protective layer is SiO
2layer.Adopt boiler tube method of diffusion all to generate mask layer at the back side of polysilicon layer surface and wafer.Adopt CVD CVD (Chemical Vapor Deposition) method to generate protective layer.Adopt chemical mechanical polishing method to remove protective layer.
The present invention also provides a kind of wafer manufacture method that prevents pattern disappearance, comprises successively: growing polycrystalline silicon layer on a surface on wafer; On polysilicon layer, form mask layer; On mask layer, form the protective layer that is greater than 4000 dusts; Remove the mask layer of wafer rear; Remove protective layer; Etching wafer forms circuit pattern.Wherein, the thickness of protective layer, between 4000 dust to 6000 dusts, for example, can be 4000 dusts, 4500 dusts, 5000 dusts, 5500 dusts or 6000 dusts.Mask layer is silicon nitride or silicon oxynitride, and described protective layer is silica.Adopt boiler tube method of diffusion to generate described mask layer.Adopt CVD vapour deposition process to generate protective layer.Wafer is immersed to the protective layer of acid solution cleaning wafer.Adopt chemical mechanical polishing method to remove described protective layer.
Method provided by the invention, the scientific and effective problem of avoiding pattern disappearance, the especially problem of mask layer pattern disappearance, and can not increase process time and production cost.
Brief description of the drawings
Fig. 1 is the schematic diagram of wafer fabrication processes in prior art.
Fig. 2 A is that in prior art processing wafer process, step S3, S4 produce the endocorpuscular schematic diagram of rete.
Fig. 2 B is the wafer photo that produces pattern disappearance in prior art.
Fig. 3 is the process chart that prevents pattern deletion method provided by the invention.
Fig. 4 is the wafer cross section structure schematic diagram that adopts the every step of technique of Fig. 3 to obtain.
Fig. 5 is the wafer manufacture method flow chart that prevents pattern disappearance provided by the invention.
The technical characterictic that Reference numeral in figure refers to is respectively:
101, wafer; 102, polysilicon layer; 103, wafer frontside mask layer; 103 ', wafer rear mask layer; 104, protective layer; 1100, rete endoparticle;
201, wafer; 202, polysilicon layer; 203, wafer frontside mask layer; 203 ', wafer rear mask layer; 204, protective layer.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, in accompanying drawing, only show part related to the present invention but not entire infrastructure.
The invention provides a kind of method that prevents pattern disappearance, as shown in Figure 3, the method comprises the following steps successively:
S101: growing polycrystalline silicon layer on a surface of wafer;
S102: form mask layer on polysilicon layer surface;
S103: forming thickness on the described mask layer forming on polysilicon layer surface is protective layers more than 4000 dusts;
S104: remove unnecessary mask layer;
S105: remove protective layer.
Wherein, the protective layer forming is between 4000 dust to 6000 dusts; for example; can be 4000 dusts, 4500 dusts, 5000 dusts, 5500 dusts or 6000 dusts; make like this thickness of diaphragm be greater than the rete endoparticle size of formation, reach the effect that prevents acid solution contact mask layer in acid cleaning process and lose pattern.Be understandable that; the thickness of this protective layer can be outside above-mentioned scope; be greater than formed rete endoparticle size as long as can reach its thickness, the effect of losing pattern to prevent acid solution contact mask layer in acid cleaning process, just all belongs to invention spirit of the present invention.
Below in conjunction with Fig. 4, the method that this prevents pattern disappearance is described in detail.
Specifically, in step S101, on a surface of wafer 201, form polysilicon layer 202, this surface is the front of wafer 201, becomes the back side of wafer 201 with respect to the opposite side of polysilicon layer.
In step S102, generate wafer frontside silicon nitride mask layer 203 and wafer rear silicon nitride mask layer 203 '.Here to adopt the method for boiler tube diffusion (Diffusion) as example, all form silicon nitride layer at the front and back of wafer 201, its thickness is 1400-1600 dust.Also can adopt other materials, for example silicon oxynitride.Its thickness can be also any thickness between 1400-1600 dust, as 1500 dusts.
In step S103, form silicon dioxide layer of protection 204 by CVD vapour deposition process on the surface of front silicon nitride layer 203.The thickness of silicon dioxide layer of protection 204 is increased to 4000-6000 dust, makes like this SiO
2thickness is considerably beyond the endocorpuscular size of rete, and in follow-up phosphoric acid acid pickling step, phosphoric acid has no chance to touch rete endoparticle, more cannot touch silicon nitride layer, therefore can corroding silicon nitride, avoid SiN layer pattern disappearance.In order to reach such effect, the thickness of silicon dioxide layer of protection can also be selected other numerical value, for example 4000 dusts, 4500 dusts, 5000 dusts, 5500 dusts or 6000 dusts etc.
In following step S104, wafer 201 is carried out to pickling, remove the silicon nitride 203 ' of wafer rear.Here adopt phosphoric acid as cleaning fluid, wafer is put into phosphoric acid solution and soak, can remove unwanted silicon nitride layer 203 '.As mentioned above, mask layer can adopt other materials to make, and for example silicon oxynitride, in the time using silicon oxynitride as mask material, equally also uses phosphoric acid as cleaning fluid.
In step S105, remove the silicon oxide layer on wafer 201 surfaces, namely protective layer 204.Conventionally can adopt the mode of pickling to clean.For cleaning process and the solution used of protective layer, belong to those skilled in the art's common technology means, therefore repeat no more.But, because silicon oxide layer is thickened, if therefore adopt the process time that the mode of this pickling need to be longer.As preferably, can also adopt the mode of chemico-mechanical polishing (CMP) to remove SiO here
2, namely protective layer 204.Utilize SiO
2protective layer 204 is different with the emissivity to light with the grinding stress of SiN mask layer 203; CMP equipment can identify the variation of rete, and in the time that silica polishes, board can stop grinding automatically; thereby CMP can, by the mode of by-endpoint, grind off SiO
2after, pass through the variation of detected signal, automatically stop at SiN mask layer 203 surfaces.Thereby greatly reduce the process time.Eliminate like this and thickened protective layer SiO
2the caused defect that increases the acid cleaning process time of layer.
As shown in Figure 5, the present invention also provides a kind of method that adopts said method processing wafer.Comprise the following steps successively:
S201: growing polycrystalline silicon layer on the surface on wafer;
S202: form mask layer on polysilicon layer;
S203: forming thickness on described mask layer is protective layers more than 4000 dusts;
S204: the mask layer of removing described wafer rear;
S205: remove described protective layer;
S206: etching wafer forms circuit pattern.
The thickness of the protective layer that wherein formed, between 4000 dust to 6000 dusts, can be 4000 dusts, 4500 dusts, 5000 dusts, 5500 dusts or 6000 dusts.
Specifically, in the time that S203 generates silica protective layer 204, make its thickness thicken the endocorpuscular size of rete likely forming to being greater than, reach and prevent acid solution contact particle in acid cleaning process, and and then the effect of contact SiN.Then, removing in the step of protective layer, adopt equally the mode of acid cleaning or CMP chemico-mechanical polishing to SiO
2layer cleans.Complete after said process, the step such as shadow, etching after wafer is carried out, forms needed circuit pattern, finally completes the manufacturing process of wafer.Wherein mask layer can also be silicon oxynitride layer.
Technical solutions according to the invention can effectively be avoided the generation in pattern disappearance (pattern missing), especially prevent the generation of mask layer pattern disappearance, due to protective layer SiO
2rete endoparticle is a kind of very general defect, often causes the corrosion of SiN and scrapping of wafer, thereby methodological science provided by the present invention avoided the problem of mask layer pattern disappearance effectively, and can not increase process time and production cost.
As mentioned above; those skilled in the art should understand; in an embodiment only taking silicon nitride, describe as mask layer and protective layer as example respectively when silica and silica; other materials can be used in the process of wafer manufacturing equally, and its generation type is also not limited only to the mode such as above-mentioned CVD, boiler tube diffusion.In the above-described embodiments, to the cleaning method of wafer also only taking acid clean, CMP optical-mechanical polishing mode cleans as example and describes, and do not get rid of the cleaning of other modes.In the situation that not deviating from connotation of the present invention and protection range, can carry out multiple improvement to said method and process.
Claims (10)
1. a method that prevents pattern disappearance, is characterized in that, the method comprises the following steps successively:
Growing polycrystalline silicon layer on a surface of wafer;
Form mask layer on described polysilicon layer surface;
On the described mask layer forming on described polysilicon layer surface, forming thickness is protective layers more than 4000 dusts;
Remove unnecessary mask layer;
Remove protective layer.
2. method according to claim 1, is characterized in that, described mask layer thickness is between 4000 to 6000 dusts.
3. method according to claim 1 and 2, is characterized in that, described mask layer is SiN layer or SiON layer, and described protective layer is SiO
2layer.
4. method according to claim 1, is characterized in that, described wafer is immersed to acid solution and remove described mask layer.
5. method according to claim 1, is characterized in that, adopts chemical mechanical polishing method to remove described protective layer.
6. a wafer manufacture method that prevents pattern disappearance, is characterized in that, described method comprises the following steps successively:
Growing polycrystalline silicon layer on a surface on wafer;
On polysilicon layer, form mask layer;
On described mask layer, forming thickness is protective layers more than 4000 dusts;
Remove the mask layer of described wafer rear;
Remove described protective layer;
Etching wafer forms circuit pattern.
7. method according to claim 6, is characterized in that, described mask layer thickness is between 4000 dust to 6000 dusts.
8. according to the method described in claim 6 or 7, it is characterized in that, described mask layer is silicon nitride or silicon oxynitride, and described protective layer is silica.
9. according to the method described in claim 6 or 7, it is characterized in that, adopt immersion acid ablution to remove described mask layer.
10. according to the method described in claim 6 or 7, it is characterized in that, adopt chemical mechanical polishing method to remove described protective layer.
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| CN103972082B CN103972082B (en) | 2017-02-08 |
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Cited By (4)
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| CN106558486A (en) * | 2015-09-30 | 2017-04-05 | 无锡华润上华科技有限公司 | The method for removing semiconductor chip mask layer |
| CN108091608A (en) * | 2017-11-30 | 2018-05-29 | 上海华力微电子有限公司 | The manufacturing method of shallow trench isolation |
| CN108110043A (en) * | 2017-12-15 | 2018-06-01 | 德淮半导体有限公司 | The optimization method of wafer bow |
| CN111367003A (en) * | 2018-12-26 | 2020-07-03 | 中芯集成电路（宁波）有限公司 | Optical device manufacturing method |
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| CN103972082B (en) | 2017-02-08 |
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