CN103970939A - Layering and reconfigurable on-chip network modeling and simulation system - Google Patents
Layering and reconfigurable on-chip network modeling and simulation system Download PDFInfo
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Abstract
The invention discloses a layering and reconfigurable on-chip network modeling and simulation system. The system comprises a test layer, a main body layer and an operation layer. The core of the test layer is a reconfigurable rout unit and a network interface unit, and the test layer can change network structure parameters dynamically. The main body layer is mainly composed of a resource node unit, is provided with a universal OCP interface which is connected with the route unit through the network interface unit and integrates a flow generation mechanism unit, a receiving mechanism unit and a performance analysis logic unit. The operation layer is composed of a software configuration module, provides a good person-to-person interaction interface, and is used for flexible configuration and structure generation of the on-chip network structure feature parameters and communication modes. The layering and reconfigurable on-chip network modeling and simulation system can conduct modeling on an on-chip network architecture structure utilizing different topological structures, network sizes, routing algorithms, buffer area depths and the like, conduct network performance simulation under different communication models and communication loads, and provide a basis for the on-chip network architecture design under different application demands.
Description
Technical field
The invention belongs to network-on-a-chip technical field, be specifically related to the reconfigurable network-on-chip modeling and simulation of a kind of stratification system.
Background technology
Along with the fast development of integrated circuit and semiconductor process techniques, the scale of SOC (system on a chip) is increasing.Network-on-chip (Network-on-Chip, NoC), as the new method that solves global communication problem in extensive SOC (system on a chip), has significantly improved the performance of system, is considered to the inevitable direction of following SOC (system on a chip) multi-core technology development.NoC design comprises that topological structure is selected, routing algorithm is determined and the link such as basic module design, there is huge difference in the design proposal that each link is different, thereby a general restructural network-on-a-chip modeling and simulation system of structure seems particularly important in performance.
Existing NoC emulation platform can be divided into two large classes, one class adopts higher level lanquage design, can be to NoC modeling and performance evaluation rapidly, but because abstraction hierarchy is higher, ignore the impact of Physical layer on performance, can cause assessment result and actual conditions to have relatively large deviation; Another kind of is directly to adopt hardware description language to simulate NoC system, but this method very flexible, simulation velocity are slow, cannot accurately at length study network-on-chip design details (as topological structure, flow rate mode etc.).Although and above-mentioned network-on-chip Evaluating Models or simulator differ from one another, all lacked the ability of test environment being carried out to dynamic-configuration.
Summary of the invention
The object of the invention is the deficiency for current network-on-chip analogue system, the reconfigurable network-on-chip modeling and simulation of a kind of stratification system is provided.This system is supported the network-on-chip architecture parameters such as different topology structure, network size, routing algorithm, buffer depth, and the flexible dynamic-configuration of multiple communication flows pattern, to realize rapid modeling and the performance simulation of multiple on-chip network structure under different communication modes and traffic load.
Realize technical scheme of the present invention as follows:
The reconfigurable network-on-chip modeling and simulation of a kind of stratification system, is characterized in that: this system comprises following level:
A) test layer, is made up of reconfigurable routing unit and network interface unit, and capable of dynamic changes network-on-chip structural characteristic parameter, to support multiple network-on-chip structure;
B) body layer, formed by the resource node with OCP interface, be connected with routing unit by OCP interface, resource node is inner integrated flow generation, reception and performance evaluation module, to support plurality of communication schemes and traffic load, and communication data statistical study;
C) operation layer, is made up of software configuration module, and good human-computer interaction interface is provided, for flexible configuration and the network-on-chip structural generation of network-on-chip structural characteristic parameter and communication pattern.
The present invention compared with prior art, has following technique effect:
The present invention is directed to and adopt higher level lanquage and the hardware description language quality of design and simulation platform respectively, build the NoC emulation platform of stratification, comprise the operation layer with the software configuration module composition of higher level lanquage design, and with the network-on-chip communication node of hardware description language design and test layer and the body layer of resource node composition.Wherein, network-on-chip communication node and resource node have reconfigurability, can carry out dynamic-configuration to NoC system architecture and the communication pattern etc. of emulation.The present invention also further applies to open core agreement OCP in NoC analogue system, design has the NoC resource node of OCP interface, communicate by OCP agreement and NoC routing unit, to improve the versatility of model, and flow generation mechanism, reception mechanism and performance evaluation logical block are integrated in to resource node inside, make that evaluation model level is simple, clear in structure, can flexible configuration.The present invention can realize rapid modeling and the performance simulation of different framework network-on-chips under different communication modes and traffic load, NoC architecture based on various different parameters designs is carried out accurately to performance evaluation all sidedly, for the NoC design alternative best interconnect architecture towards concrete application provides foundation.
Brief description of the drawings
Fig. 1 is the reconfigurable network-on-chip emulate system architecture of stratification figure;
Fig. 2 is restructural routing unit structural drawing;
Fig. 3 is routing unit load module structural drawing;
Fig. 4 is that cycle control mode generates configurable input port code structure figure;
Fig. 5 is routing unit routing calculation module structural drawing;
Fig. 6 is routing unit arbitration modules structural drawing;
Fig. 7 is exchanges data switch module reconfigurable structures figure in routing unit;
Fig. 8 is routing unit output module structural drawing;
Fig. 9 is network interface structural drawing;
Figure 10 is OCP agreement fixed data packet format;
Figure 11 is data microplate form;
Figure 12 is resource node structural drawing;
Figure 13 is flow generation module structural drawing in resource node;
Figure 14 is that in resource node, flow receives and performance evaluation modular structure figure;
Figure 15 is the network-on-chip communication structure figure based on OCP interface;
Figure 16 is based on operation layer software building NoC model process flow diagram.
Embodiment
Below in conjunction with accompanying drawing, describe the present invention by embodiment.
The reconfigurable network-on-chip analogue system of stratification of the present invention comprises operation layer, body layer and three levels of test layer, and for network-on-chip key characteristic being carried out to modeling and performance index statistical study, its structure as shown in Figure 1.Function composition and the relation of every one deck are described as follows.
(1) operation layer, this layer is Simulation-Oriented platform user directly, user is undertaken alternately by software configuration module and realistic model, the customization network-on-chip structures such as network topology structure, network size, routing algorithm are set according to application demand, and select distributed model, data handbag length, network input rate, flit size of test traffic etc., be convenient to test the property indices of network-on-chip under different communication modes and traffic load, the results of property of test also shows by software configuration module.
(2) body layer, this layer is made up of the resource node S with OCP interface, be used for simulating the various function IP kernels of network-on-a-chip (as, the combination of dedicated hardware resources, embedded microprocessor, self-defining reconfigurable hardware or above-mentioned various resources) communication task, comprise according to configured room and time and distribute and produce corresponding communication flows injection network, and carry out performance evaluation according to the communication conditions of network, calculate various performance index.In addition, user can, according to the number of the scale resource allocation node S of network, be that the NoC of the 2D Mesh structure to 4 × 4 sizes carries out performance evaluation as shown in Figure 1, has distributed 16 resource nodes corresponding with routing unit.Severally when signal intelligence on fixed route, can only configure the resource node that need to transmit and receive data, the effective like this scale of controlling body layer to node when only testing.
(3) test layer, places the network-on-chip example for testing, and its core component is reconfigurable routing unit R and network interface unit NI.Configuration information reconstruct routing unit according to user at operation layer, at the NoC example of test layer formation specified structure characteristic parameter (comprising topological structure, exchanging policy, routing policy, buffer size, port number etc.).If the NoC using in Fig. 1 is the 2D Mesh network of 4 × 4, each routing unit R and adjacent routing unit communicate, and communicate by network interface unit and resource node.
As described above, three of above-mentioned analogue system levels are made up of software configuration module, the resource node with OCP interface, restructural routing unit and these cores of network interface unit respectively.Thereby the key issue the present invention relates to is the design of these core components, describe concrete structure and the method for designing of core component below in detail.
Routing unit is the core of network-on-chip communication, is mainly responsible for reception, the storage of data, and gives next routing unit or resource node according to specific routing algorithm protocol forward.The minimum unit of its transmission information is microplate, has comprised control information and load data in microplate.Control information is mainly used to identify microplate type, indicates the state of microplate; Load data is the data content of microplate transmission.In order to improve the efficiency of transmission, the present invention has designed a kind of twin-channel restructural routing unit, the transmission of control signal and load data is separated, and its structured flowchart as shown in Figure 2, is mainly made up of load module, arbitration modules, alteration switch module and output module.Each several part practical function and structure are as follows respectively:
(1) load module
This module is resolved the microplate data that receive, and separation control signal and load data, and routing algorithm agreement according to the rules, deposit respectively it in corresponding data buffer, and sends request signal to arbitration modules transmission.Its structure as shown in Figure 3, comprises input port module, routing calculation module and data cache module.
Load module receives the microplate that upper level routing unit sends over, and through the parsing of input port, control signal ctr_in and load data Data_in is separated, and delivers to respectively corresponding data cache module.By obtaining microplate Type Control position in ctrl_in, judge microplate type, if a microplate will be delivered to load data routing calculation module and carry out route, route results is given cache controller.Data cache module is in the time receiving microplate data, can trigger cache controller and initiate request command to arbitration modules, allow after signal in the transmission that receives arbitration modules, cache controller control data FIFO and control signal, data cache module sends packet to corresponding alteration switch module.
For different NoC topological structures, the number of the input/output port of routing unit and being not quite similar with the number of be connected resource node.Thereby the present invention adopts the mode of cycle control to generate the interface circuit of configurable port number.To generate 8 ports as example, as shown in Figure 4, in code, defined parameter num_ports is 8 to its code structure, adopts for loop statement, makes load module input_module instantiation 8 times.
In addition, in load module, routing iinformation in routing calculation module Receiver microplate, carries out route according to certain routing mechanism to routing iinformation, obtains the routing direction of packet.For embodying reconfigurability, routing mechanism can be according to network topology structure option and installment.Routing calculation module structure as shown in Figure 5, has comprised multiple routing algorithm submodule and the routing algorithm submodule can customize.
Calculate in interface module and configure parameters in route, as routing algorithm Type Control parameter router_type, routing iinformation bit wide parameter router_info_width, Output rusults bit wide parameter router_out_width etc., select to specify the submodule of routing algorithm, realize the routing mode of this algorithm.If realize XY routing algorithm, only type parameter need be configured to ROUTING_TYPE_XY, routing iinformation bit wide is configured to 8bit, and Output rusults bit wide is configured to 5bit, and selects XY routing algorithm submodule.If the routing algorithm that the network topology structure of institute's emulation adopts is not realized in existing routing algorithm submodule storehouse, Configuration Type parameter is ROUTING_TYPE_DEFAULT and other parameter values accordingly, by extendible self-defined routing algorithm interface, add self-defined routing algorithm submodule to routing calculation module code engineering, realize the expansion of routing algorithm.
The Output rusults of routing algorithm is port numbering, and for different network topologies, the port numbering of routing unit is also different.As the routing unit port numbering 0 ~ 3 of grid network represents respectively the port of four corners of the world four direction, and the 4th port represents local connectivity port, routing unit port 0 ~ 3 port distribution of tree network is following at routing unit, be responsible for connexon node, 4 ~ 7 port distribution, in routing unit top, are responsible for connecting father node.Different topology structural system, in the time of connection route unit, need connect according to port numbering.
(2) arbitration modules
This module, receiving after the request signal of each load module transmission, is made corresponding response according to arbitration agreement, and is controlled alteration switch module and carry out exchanges data.Its reconfigurability is mainly reflected in the alternative of arbitration algorithm and sends request number changeability.For improving transfer efficiency, the present invention has adopted Virtual Channel technology in routing unit, and therefore, the Forward-reques sending for each port also needs to have a point Virtual Channel arbitration function, arbitration modules one is divided into two-stage and carries out data arbitration distribution, is divided into output port application and the application of output Virtual Channel.This modular circuit structure as shown in Figure 6.
In figure, p0 is routing unit port number, and v is Virtual Channel number in each port.The first order, to the Virtual Channel of output port application forwarding data, needs the moderator of p0 v:1.The second level is the moderator of the pi:1 of each output port, echo port output request.The input signal bit wide parameter arbiter_width of arbitration modules changes with the change of moderator example positions, in the time that the first order is arbitrated, arbiter_width bit wide is num_vcs, be Virtual Channel number, and be num_ports while arbitrating in the second level, be i.e. port number.With routing algorithm module class seemingly, the reconstruct of arbitration modules is also mainly the selection that realizes different arbitration algorithms.The selection of arbitration algorithm is selected the different arbitration algorithm of instantiation by case statement.In the time adopting self-defined arbitration algorithm, the self-defined arbitration algorithm module that has defined input and output signal is carried out to secondary development.
(3) alteration switch module
This module is divided into load data Switching Module and control signal Switching Module, by arbitration modules control realize data by load module the physical transfer to output module.Taking exchanges data switch module as example, its circuit structure diagram as shown in Figure 7.
Module input signal is made up of data signal line data_in_ip and cross-port control signal ctrl_in_op_ip, and the bit wide of data signal line is num_ports*data_width, and total bit wide and routing unit port number are proportional, realizes reconstruct configuration.Control signal wire be num_ports*num_ports, the connection status of distribution control inputs port and output port.Switch_type is exchanging array connection type control parameter, be divided into tri-kinds of CROSSBAR_TYPE_TRISTATE, CROSSBAR_TYPE_MUX, CROSSBAR_TYPE_DIST_MUX, realize respectively the exchange connected mode of tri-state matrix switch, full connection matrix and part connection matrix.
(4) output module
This module receives load data and control signal, according to arbitration result control MUX, selects corresponding port data to export, and exports to next routing unit or object resource node.This modular circuit structural drawing as shown in Figure 8, is mainly made up of MUX and o controller, and the restructural mode of its port number is consistent with load module.
Another core component of test layer is reconfigurable network interface unit NI, and it is responsible for realizing resource node and is connected with the data between routing unit.Data in resource node send data to network interface unit NI with fixed data packet format, and network interface unit NI need re-group package packet according to different network topologies, to adapt to different topological structures.Reconfigurable network interface unit structural drawing as shown in Figure 9, comprise with resource node interface, data group bag and unpack, input control and output control, these four modules of data buffer storage.Each several part practical function and structure are as follows respectively:
(1) with resource node interface module: adopt OCP agreement to communicate by letter with the resource node in NoC system, to improve versatility;
(2) data group bag and parse module: data group bag module is converted to set form packet the data microplate that adapts to current network-on-chip structural transmission, be the key modules that realizes reconstruct in network interface unit, composition, the bit wide etc. of data microplate all changes with the variation of reconstruction parameter; Unpacking is the reverse process of group bag, and data parse module becomes to meet the data packet format of OCP protocol communication by the data microplate format conversion sending from network-on-chip.
(3) input control and output control module: realize the scheduling of data microplate transmission, the transmission of allotment data between resource node and routing unit;
(4) data cache module: press microplate form storage packet, its degree of depth is configurable.
Wherein, the OCP agreement fixed data packet format of definition as shown in figure 10.Route_trans_cnt wraps in the hop count of Internet Transmission for statistics, packet is every through a routing unit, and this zone bit counting adds 1, for link hop count statistical study; Packet_length is that data handbag is long, for calculating the number that packet is divided into microplate; Source_ID is the source address of Packet Generation, is resource node coded address; Destination_ID is the destination address of Packet Generation, is resource node coded address equally; Reserved is reserved word; Time_cnt is record data bag sends to data receiver time delay from data, for the delay performance of statistical study network topology transmission.
Reconfigurable network interface unit provided by the invention, has the packet of set form is converted to the data microplate under reconstruction property, and composition, the bit wide etc. of data microplate all changes with the variation of reconstruction parameter.According to the analysis to data packet format, data microplate can be defined as to form type as shown in figure 11.In Figure 11, Ctrl part is microplate control signal, the useful signal mark V that has comprised microplate, microplate place Virtual Channel numbering VC, microplate type code H(sheet end to end, and T(tail microplate Header), Tail), and Data is data microplate part, in the time of sheet end to end, in Data, comprise routing iinformation Router_info, microplate length L, reserved word R.In different network topologies, by configuring the bit wide parameter of these signals, just can realize the data microplate of different bit wides.As, the network-on-chip of the 2D Mesh structure of definition 4 × 4, Virtual Channel number is 4, data handbag length is 127 to the maximum, the control signal bit wide of data microplate is 5, and data-signal bit wide is at least 11 (routing iinformation two-dimensional address width is 4, and packet microplate length bit wide is 7).
The core component of body layer is the resource node with OCP interface.The modular method for designing of the inner employing of resource node, has encapsulated the generation of network-on-chip flow, receiver module, performance evaluation module and interface module, and inner structure as shown in figure 12.Each module can be carried out respectively independent amendment in the time of design, only need to revise accordingly flow generation module, and other modules are not exerted an influence as needs while adding certain flow distribution model, is convenient to the upgrading of emulation platform.Simulate the IP kernel of network-on-chip communicates by letter with resource node, make platform configuration more flexible, its dirigibility is mainly manifested in following two aspects: the number of nodes that can communicate by letter as required on the one hand carrys out resource allocation node, for not needing the node that carries out data input and data output not configure resource node, can reduce like this scale of main platform body layer; On the other hand, the communication node that only sends data or receive only data for some, can also be as required flow generation module or the flow receiver module in resource allocation node only, further save Resources on Chip.Introduce in detail the each module practical function of resource node and structure below.
(1) flow generation module
It is the source of whole performance evaluation work that flow generates, and the flow generation module structure in the present invention as shown in figure 13, comprises random module, Time interval module, Addr_gen module and Inject module.
Between random module is used for producing and meets 0 to 1, equally distributed random number is for time distributed control module and space distribution control module.
Time distributed control module Time interval is for controlling the origination interval of network traffics on time dimension, it the is inner integrated arithmetic logic of various flow rate distributed model, choice for use during for test.Various times of supporting in platform distribute (as, Poisson distribution, self similarity distribute, Fixed Time Interval) the random number that uses of the time interval provided by random module, other parameters all can configure.When clock period counter is in the time arriving the time interval calculating, output signal WR_en is set to high level by Time interval module, and notice Inject module, to injecting data in network, is set to low level automatically at next clock period WR_en.The ON-OFF model that continues to send data for needs, in Burst Period, WR_en remains high level, in idling cycle, WR_en remains low level.
Space distribution control module Addr_gen is responsible for determining the correspondence of network traffics on Spatial Dimension, according to user's configuration, the multiple spatial distribution model arithmetic logic that Addr_gen inside modules is integrated, calculate to meet and specify the destination address of distribution results as present node communication, the space distribution of supporting in platform to comprise to be uniformly distributed, to fall probability distribution, constant transmissions path profile.The address number that Inject module produces according to Addr_gen module in the time that each generation flow injects is as the destination address of this communication, complete after communication, Addr_gen module just, at once by calculating scheduler numbering, specifies for communication next time provides to meet the destination address distributing.
Inject module reads the configuration file transmitting from operation layer, selects flow distribution model setting that Time interval module and Addr_gen module should generate to specify the parameters distributing according to configuration information.The microplate length that Inject module is specified according to user produces packet to be sent, the address of the obedience specific distribution producing taking Addr_gen module, as communication target, sends data and address to network interface unit module in the time that signal WR_en is high level simultaneously.
(2) flow receives and performance evaluation module
Flow in resource node receives with performance evaluation module and comprises Receiver module and Access module, and its structure as shown in figure 14.
Receiver module is test data receiver module, the data that transmit for storing network-on-chip.Often receive a packet, the time arriving with regard to record data bag, and the parameter information such as transmitting time, data packet length and link hop count to packet in data packet head microplate adds up, then these parameters are passed to performance evaluation modules A ccess and carried out analyzing and processing.
The information that need to add up while calculating according to network performance index (comprising average delay, handling capacity, link utilization etc.), necessary information during in conjunction with data transmission, can determine the packet package head format of test traffic, data microplate length in platform is 32, and a microplate form is as follows.
| Data bit | 31-27 | 26-22 | 21-17 | 16-12 | 11-0 |
| Data content | Hop count | Data packet length | Destination address | Source address | Transmitting time |
Data in microplate by the flow generation module of platform in the time that data produce in write head microplate, the time that wherein transmitting time is imported network-on-chip into for record data bag, be used from the calculating of network average time index with the packet time of reception one of Receiver module records; Source address and target address information provide foundation for routing unit calculates transmission path; Data packet length information can provide important parameter for the calculating of network throughput and link utilization; Hop count has recorded the number of links experiencing in transmission of data packets, for the calculating to link utilization and network power consumption, its initial value is 0, often just adds an operation through a routing forwarding, only has the value of hop count to revise in the data message of a microplate.
Access module is performance Index Calculation module, its inner integrated algorithm logic of property indices formula.In addition, in Access module, also comprise a global clock counter, for computing platform working time, the network power consumption parameter transmitting in conjunction with every terms of information and the operation layer of Receiver module statistics, for algoritic module provides performance Index Calculation needed various parameters, final calculation result gathers by body layer and waits for and handle reading of layer.
(3) OCP interface module
This module is responsible for realizing resource node and is communicated by letter with chip-on communication is internetwork, comprises host interface and slave interface two parts.Host interface is connected with flow generation module, order and data is sent to it to the routing unit in adjacent chip-on communication network, and receive the feedback signal of routing unit; Slave interface is connected with flow receptivity analysis module, receives according to OCP sequential the data that routing unit is sent, and sends data the preservation of to performance evaluation module, sends and feeds back signal to data receiver simultaneously.Network-on-chip communication structure based on OCP interface as shown in figure 15.
The component units of operation layer is software configuration module.This module provides good interpersonal interactive interface, and extracted network characterization parameter display, on software interface, is generated to the various NoC models for Simulation Evaluation for user's option and installment; According to configured communication flows mode parameter, call the basic module (resource node module) of body layer, according to parameters such as configured topological structure, routing algorithm, Virtual Channel quantity, buffer depth, call the basic module (restructural routing unit and network interface unit) of test layer, and extendible custom block (self-defining routing algorithm, arbitration algorithm etc.), build NoC system architecture with this; By generate NoC project file (comprising system architecture code and emulation testing data TestBench) input to EDA emulation tool (as, Modelsim), the performance datas such as statistics NoC network node transceiving data, time delay, and data are stored in a text; Finally read the statistics of eda tool feedback, and to this data analysis, produce network performance evaluation report.Describe according to above-mentioned functions, software configuration module Further Division in the present invention is that network topology structure configuration, the configuration of routing unit structure, network interface unit configuration, flow parameter configuration and EDA emulated data are analyzed this five modules, each several part practical function is as follows respectively, and the flow process based on this structure NoC realistic model as shown in figure 16.
(1) network topology structure configuration module: mainly realize the configuration of topological structure parameter (topological structure, network size, resource node etc.), and set up network node connection according to configuration parameter, form NoC network object, this object is carried out to the performance parameters such as network diameter, mean distance, network node route shortest path and calculate;
(2) routing unit structure configuration module: in conjunction with the topological structure parameter having configured, further route cellular construction parameter is configured.Configurable parameter has routing algorithm type parameter, Virtual Channel number, buffer depth, microplate bit wide, exchanged form type parameter, arbitration type parameter, congestion control type parameter etc.
(3) network interface configuration module: the annexation of Configuration network node and resource node; According to network topology structure parameter and routing unit structural parameters, configuring network interface unit correlation parameter, is converted to by set form packet the data microplate form that adapts to current topological structure network system to realize.
(4) flow parameter configuration module: parameter that the raw space distribution of configuration flow volume production and time distribute, data packet length, resource node number etc., generation EDA simulation test platform data and TestBench etc.
(5) EDA emulated data is analyzed: to the NoC performance parameter data analysis of EDA emulation tool statistics, produce NoC performance assessment report etc.
Application said method can form the reconfigurable network-on-chip modeling and simulation of stratification system, realize the network-on-chip architecture with features such as different topology structure, network size, routing algorithm, buffer depth is carried out to correct rapid modeling, and under different communication modes and traffic load, carry out network performance emulation, assess the impact of various structural characteristic parameters for network performance, for the on-chip network structure design under different application demand provides important evidence.
Claims (5)
1. the reconfigurable network-on-chip modeling and simulation of a stratification system, is characterized in that: this system comprises following level:
A) test layer, is made up of reconfigurable routing unit and network interface unit, and capable of dynamic changes network-on-chip structural characteristic parameter, to support multiple network-on-chip structure;
B) body layer, formed by the resource node with OCP interface, be connected with routing unit by OCP interface, resource node is inner integrated flow generation, reception and performance evaluation module, to support plurality of communication schemes and traffic load, and communication data statistical study;
C) operation layer, is made up of software configuration module, and good human-computer interaction interface is provided, for flexible configuration and the network-on-chip structural generation of network-on-chip structural characteristic parameter and communication pattern.
2. the reconfigurable network-on-chip modeling and simulation of stratification according to claim 1 system, is characterized in that: described routing unit comprises following part:
A1) load module: the interface circuit that comprises the configurable input port number generating in cycle control mode, separate and extendible routing algorithm submodule, and the data cache module of variable depth; For the microplate data that receive are resolved, separation control signal and load data, and routing algorithm agreement according to the rules, deposit respectively it in corresponding data buffer, and send request signal to arbitration modules transmission;
A2) arbitration modules: comprise configurable input request port and arbitration algorithm module; Make corresponding response for the request signal each load module being sent according to arbitration agreement, and control alteration switch module and carry out exchanges data;
A3) alteration switch module: comprise multiple exchange connected mode; For realize data by load module the physical transfer to output module;
A4) output module, is made up of MUX and o controller, and its output port number can be reconstructed configuration, for receiving load data and control signal, according to arbitration result control MUX, selects corresponding port data to export.
3. the reconfigurable network-on-chip modeling and simulation of stratification according to claim 1 system, is characterized in that: described network interface unit is responsible for realizing resource node and is connected with the data between routing unit, comprises following part:
1) with resource node interface module: adopt OCP agreement to communicate by letter with the resource node in network-on-a-chip, to improve versatility;
2) data group bag and parse module: data group bag module is converted to set form packet the data microplate that adapts to current network-on-chip structural transmission, be the key modules that realizes reconstruct in network interface unit, composition, the bit wide of data microplate all change with the variation of reconstruction parameter; Unpacking is the reverse process of group bag, and data parse module becomes to meet the data packet format of OCP protocol communication by the data microplate format conversion sending from network-on-chip;
3) input control and output control module: realize the scheduling of data microplate transmission, the transmission of allotment data between resource node and routing unit;
4) data cache module: press microplate form storage packet, its degree of depth is configurable.
4. the reconfigurable network-on-chip modeling and simulation of stratification according to claim 1 system, is characterized in that: described resource node comprises following part:
B1) flow generation module: produce and meet the test traffic that certain space distributes and the time distributes;
B2) flow receives and performance evaluation module: receive and store the data that network-on-chip transmits, the time that record data bag arrives simultaneously, packet parameter information in the microplate of statistics packet header, by respective formula computational grid performance index;
B3) OCP interface module: be responsible for realizing communicating by letter between resource node and network-on-chip, comprise host interface and slave interface two parts, host interface is connected with flow generation module, order and data are sent to the routing unit in adjacent with it network-on-chip, and receive the feedback signal of routing unit; Slave interface receives and is connected with performance evaluation module with flow, receives according to OCP sequential the data that routing unit is sent, and sends data the preservation of to performance evaluation module, sends and feeds back signal to data receiver simultaneously.
5. the reconfigurable network-on-chip modeling and simulation of stratification according to claim 1 system, is characterized in that: described software configuration module comprises following part:
C1) network topology structure configuration module: realize the configuration of network topology structure parameter, and set up network node connection according to configuration parameter, form network-on-chip object, this object is carried out to performance parameter calculating;
C2) routing unit structure configuration module: in conjunction with the topological structure parameter having configured, further route cellular construction parameter is configured;
C3) network interface configuration module: the annexation of Configuration network node and resource node; According to network topology structure parameter and routing unit structural parameters, configuring network interface unit correlation parameter, is converted to by set form packet the data microplate form that adapts to current topological structure network system to realize;
C4) flow parameter configuration module: parameter, data packet length, resource node number that the space distribution that configuration flow volume production is raw and time distribute, generate EDA simulation test platform data and TestBench;
C5) EDA emulated data is analyzed: to the network-on-chip performance parameter data analysis of EDA emulation tool statistics, produce network-on-chip performance assessment report.
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105391576A (en) * | 2015-11-02 | 2016-03-09 | 电子科技大学 | Network on chip operation process reproduction method and system |
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| CN107003691A (en) * | 2014-12-27 | 2017-08-01 | 英特尔公司 | Technology for synchronizing sampling to counter based on global clock |
| CN107196792A (en) * | 2017-05-17 | 2017-09-22 | 南京大学 | The Reconfigurable Computation Configuration network system of expansible support partially dynamical reconfiguration |
| CN107450899A (en) * | 2016-06-01 | 2017-12-08 | 深圳市信锐网科技术有限公司 | The generation method and device of terminal control script |
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| CN109670268A (en) * | 2018-12-29 | 2019-04-23 | 京微齐力(北京)科技有限公司 | A kind of multiple IP and the connection method of the port EFPGA |
| CN110958177A (en) * | 2019-11-07 | 2020-04-03 | 浪潮电子信息产业股份有限公司 | Network-on-chip route optimization method, device, equipment and readable storage medium |
| CN111104775A (en) * | 2019-11-22 | 2020-05-05 | 核芯互联科技(青岛)有限公司 | Network-on-chip topological structure and implementation method thereof |
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| CN112311701A (en) * | 2019-07-29 | 2021-02-02 | 奥塔索克技术有限公司 | Analog broadcasting in network on chip |
| CN113055219A (en) * | 2019-12-27 | 2021-06-29 | 阿特里斯公司 | Physically aware topology synthesis of networks |
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| CN115348181A (en) * | 2022-10-18 | 2022-11-15 | 苏州浪潮智能科技有限公司 | Data transmission modeling method, system, equipment and storage medium |
| CN115643167A (en) * | 2022-12-14 | 2023-01-24 | 摩尔线程智能科技(北京)有限责任公司 | Network-on-chip configuration method and device, and storage medium |
| CN115665041A (en) * | 2022-11-18 | 2023-01-31 | 北京红山微电子技术有限公司 | Network-on-chip structure, data transmission method, electronic device, and storage medium |
-
2014
- 2014-04-22 CN CN201410164158.2A patent/CN103970939A/en active Pending
Non-Patent Citations (4)
| Title |
|---|
| 周阳: "面向多种拓扑结构的可重构片上网络建模与仿真", 《万方数据学位论文库》 * |
| 罗丹 等: "基于OCP接口的片上网络性能评估平台", 《万方数据库》 * |
| 葛芬 等: "基于网络监控器的专用片上网络动态容错路由", 《电子学报》 * |
| 陈延仓 等: "面向性能优化的可重构片上网络技术研究", 《微电子学》 * |
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