CN103956133B - shift register circuit and shift register - Google Patents
shift register circuit and shift register Download PDFInfo
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- CN103956133B CN103956133B CN201410196024.9A CN201410196024A CN103956133B CN 103956133 B CN103956133 B CN 103956133B CN 201410196024 A CN201410196024 A CN 201410196024A CN 103956133 B CN103956133 B CN 103956133B
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- 230000005611 electricity Effects 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 18
- 230000001808 coupling effect Effects 0.000 abstract description 14
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- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 68
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- 238000007667 floating Methods 0.000 description 3
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Abstract
The invention discloses a shift register circuit which is provided with a plurality of shift registers. Each shift register has at least four input terminals, a pull-up circuit, a first switch, a first pull-down circuit and a second pull-down circuit. The control end of the first switch is coupled to the node. The pull-up circuit pulls up the potential of the node. The first pull-down circuit is used for pulling down the electric potential of the output end of the shift register. The second pull-down circuit is used for pulling down the potential of the node. The four input ends respectively receive different clock pulse signals to inhibit the surge generated at the node due to the coupling effect of the parasitic capacitance of the first switch and avoid the positive bias stress effect generated by the two transistors of the first pull-down circuit and the second pull-down circuit.
Description
Technical field
The present invention is about a kind of shift scratch circuit and shift registor, a kind of parasitic capacitance alleviating transistor
Coupling effect (coupling effect) and positive bias stress (positive bias stress；PBS) displacement of effect is temporary
Deposit circuit and shift registor.
Background technology
It is said that in general, display floater includes multiple pixel, gate driver circuit and source electrode drive circuit.Raster data model
Circuit comprises stages shift buffer, is used for providing multiple gate drive signal, to control the open and close of pixel.Source electrode drives
Galvanic electricity road is then in order to write data signal to the pixel being unlocked.Additionally, display floater is frequently with gate driver circuit base at present
Plate technique (gate driver on array；GOA), to provide the gate drive signal needed for pixel.Drive with traditional grid
Dynamic device is different, and its processing procedure of circuit because of employing GOA can be incorporated in the thin film transistor (TFT) array (TFT array) of display floater
Processing procedure, therefore the production cost of panel can be reduced.
Refer to Fig. 1 and Fig. 2.Fig. 1 is the circuit diagram of the shift registor 100 of prior art.Fig. 2 is that the displacement of Fig. 1 is temporary
The sequential chart of storage 100.Shift registor 100 comprises four switch T1a to T1d.Wherein, switch T1a and T1c receives defeated respectively
Enter signal GN-1And GN+1, and wherein input signal GN-1And GN+1Come from previous stage and the outfan of rear stage shift registor.
First end of switch T1b receives clock signal CK, and the control end of switch T1b is coupled to node QN, and switch the second end coupling of T1b
It is connected to the outfan of shift registor 100 with output signal output GN.First end of switch T1c and T1d is respectively coupled to node QN
And the outfan of shift registor 100, and the second end switching T1c and T1d is both coupled to system voltage end VSS.Wherein system
The current potential of voltage end VSS can be identical with grid electronegative potential VGL.Additionally, input signal GN+1It is sent to switch the control of T1c and T1d
End processed, to control the opening and closing of switch T1c and T1d.Additionally, another clock signal XCK is in order to control previous stage and rear
The operation of level shift registor, and clock signal XCK and clock signal CK can be at grid high potential VGH and grid electronegative potential VGL
Between switch.
At period TAPeriod, switch T1a is because of input signal GN-1It is in grid high potential VGH and is unlocked, and cause node
QNCurrent potential be pulled to grid high potential VGH, and cause the unlatching switching T1b.Additionally, switch T1c and T1d is because of input signal
GN+1It is in grid electronegative potential VGL and is closed.It is unlocked because of switch T1b and clock signal CK is in grid electronegative potential VGL, therefore
Output signal G that the outfan of shift registor 100 is exportedNGrid electronegative potential VGL can be in.
At period TBPeriod, switch T1a, T1c and T1d are because of input signal GN-1And GN+1All in grid electronegative potential VGL
It is closed, and causes node QNIt is in floating.Additionally, due to the current potential of clock signal CK is grid high potential VGH, and by
In the coupling effect of the parasitic capacitance of switch T1b, and make node QNCurrent potential be promoted to the VGH of about twice, and make defeated
Go out signal GNCurrent potential be grid high potential VGH.
At period TCPeriod, switch T1a is because of input signal GN-1It is in grid electronegative potential VGL and is closed, and switch T1c
And T1d is because of input signal GN+1It is in grid high potential VGH and is unlocked.Node QNCurrent potential because switch T1c be unlocked and by under
It is pulled to grid electronegative potential VGL, and output signal GNCurrent potential be then unlocked also be pulled down to grid electronegative potential VGL because of switch T1d.
But, because of the coupling effect (coupling of the parasitic capacitance (parasitic capacitor) of switch T1b
Effect), input signal G exported at the outfan of previous stage shift registorN-1The most again by grid electronegative potential
Before VGL is pulled to grid high potential VGH, owing to the current potential of clock signal CK still can be low at grid high potential VGH and grid
Switch between current potential VGL, therefore easily at node QNProduce surging (glitch), and and then cause shift registor 100
Output signal GNWaveform incorrect.Additionally, because switch T1c and T1d is using grid electronegative potential VGL as its low level signal, therefore
Switch T1c and T1d easily produces positive bias stress (positive bias stress；PBS) effect, and make switch T1c and
T1d its critical voltage after operation for a long time can produce positive offset, and cause switching T1c and T1d driving force and decline.
Summary of the invention
One embodiment of the invention provides a kind of shift registor.Described shift registor comprises signal end, first defeated
Enter end, the second input, the 3rd input, four-input terminal, outfan, pull-up circuit, first switch, the first pull-down circuit with
And second pull-down circuit.Signal end receives input signal.First input end receives the first clock signal.Second input receives the
Two clock signals.3rd input receives the 3rd clock signal.Four-input terminal receives the 4th clock signal.Pull-up circuit and letter
Number end and first input end couple, and in order to according to the first clock signal, the electric connection between control signal end and node.The
One switch couples with the second input, node and outfan, and in order to the current potential according to node, controls the second input and output
Electric connection between end.First pull-down circuit and the 3rd input, outfan and four-input terminal couple, and in order to according to the
Three clock signals, the electric connection between control output end and four-input terminal.Second pull-down circuit and node and the first input
End couples, and in order to according to the 4th clock signal or the 5th clock signal, to control electrically connecting between node and first input end
Connect.
One embodiment of the invention provides a kind of shift scratch circuit.It is temporary that described shift scratch circuit comprises multiple displacement
Storage.Each shift registor signal end, first input end, the second input, the 3rd input, four-input terminal, outfan,
Pull-up circuit, the first switch, the first pull-down circuit, the second pull-down circuit and the 3rd pull-down circuit.Pull-up circuit and signal end,
Node and first input end couple, and in order to the current potential according to first input end, electrically connecting between control signal end and node
Connect.First switch couples with the second input, node and outfan, and in order to the current potential according to node, controls the second input
And the electric connection between outfan.First pull-down circuit and the 3rd input, outfan and four-input terminal couple, and in order to
According to the current potential of the 3rd input, the electric connection between control output end and four-input terminal.Second pull-down circuit and node,
First input end and four-input terminal couple, and in order to according to the current potential of four-input terminal, control node and first input end it
Between electric connection.3rd pull-down circuit couples with node, the 3rd input and four-input terminal, and in order to according to the 3rd input
The current potential of end, controls the electric connection between node and four-input terminal.Wherein first input end, the second input, the 3rd defeated
Enter end and four-input terminal receives different clock signals respectively.
One embodiment of the invention provides a kind of shift scratch circuit.It is temporary that described shift scratch circuit comprises multiple displacement
Storage.Each shift registor signal end, first input end, the second input, the 3rd input, four-input terminal, the 5th defeated
Enter end, outfan, pull-up circuit, the first switch, the first pull-down circuit and the second pull-down circuit.Pull-up circuit and signal end,
Node and first input end couple, and in order to the current potential according to first input end, electrically connecting between control signal end and node
Connect.First switch couples with the second input, node and outfan, and in order to the current potential according to node, controls the second input
And the electric connection between outfan.First pull-down circuit and the 3rd input, outfan and four-input terminal couple, and in order to
According to the current potential of the 3rd input, the electric connection between control output end and four-input terminal.Second pull-down circuit and node,
First input end and the 5th input couple, and in order to according to the current potential of the 5th input, control node and first input end it
Between electric connection.Wherein first input end, the second input, the 3rd input, four-input terminal and the 5th input are respectively
Receive different clock signals.
By the shift registor of the embodiment of the present invention, owing to the switch of each pull-down circuit is all low using clock signal as it
Level signal, therefore can be affected by positive bias stress (PBS) effect because operating for a long time at the switch of each pull-down circuit
Under, the switch of pull-down circuit is imposed periodic reverse blas stress (NBS) effect, restores so that critical voltage (Vth) is produced
Effect, improves driving force and declines problem.Additionally, the switch of the second pull-down circuit can be opened the most slightly or fully open
Open, therefore can suppress to result from the surging controlling end of the first switch because of the coupling effect of the parasitic capacitance of the first switch.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the shift registor of prior art；
Fig. 2 is the sequential chart of the shift registor of Fig. 1；
Fig. 3 is the circuit diagram of the shift registor of one embodiment of the invention；
Fig. 4 is the schematic diagram of the shift scratch circuit of one embodiment of the invention；
Fig. 5 is the sequential chart of the shift scratch circuit of Fig. 4；
Fig. 6 is the circuit diagram of the shift registor of another embodiment of the present invention；
Fig. 7 is the schematic diagram of the shift scratch circuit of another embodiment of the present invention.
Wherein, reference；
100,300,300_5,500_5 shift registor
300_1,500_1 shift registor, the first shift registor
300_2,500_2 shift registor, the second shift registor
300_3,500_3 shift registor, the 3rd shift registor
300_4,500_4 shift registor, the 4th shift registor
310 pull-up circuits
320 first switches
330 first pull-down circuits
340,540 second pull-down circuit
350 the 3rd pull-down circuits
400,700 shift scratch circuit
C1 electric capacity, the first electric capacity
C2 electric capacity, the second electric capacity
CK, XCK clock signal
CK1 clock signal, the second clock signal
CK_1 clock signal, the 6th clock signal
CK2 clock signal, the 5th clock signal
CK_2 clock signal, the 3rd clock signal
CK3 clock signal, the 4th clock signal
CK_3 clock signal, the 7th clock signal
CK4 clock signal, the 8th clock signal
CK_4 clock signal, the first clock signal
GNOutput signal
GN-1、G1To G5Input signal
GN+1Input signal, output signal
IN signal end
IN1 first input end
IN2 the second input
IN3 the 3rd input
IN4 four-input terminal
IN5 the 5th input
QNNode
QN+1The node of rear stage shift registor
Out outfan
SP initial signal
T1a, T1e switch
T1b switch, the first switch
T1c switch, the 3rd switch
T1d switch, second switch
T1 period, the first period
T2、T4、T6、TA、TB、TCPeriod
T3 period, the second period
T5 period, the 3rd period
T7 period, the 4th period
TPCycle
VGH grid high potential
The grid high potential of 2VGH twice
VGL grid electronegative potential
VGL1 first grid electronegative potential
VGL2 second grid electronegative potential
VSS system voltage end
Detailed description of the invention
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Refer to the circuit diagram of the shift registor 300 that Fig. 3, Fig. 3 are one embodiment of the invention.Shift registor 300 wraps
Containing signal end IN, first input end IN1, the second input IN2, the 3rd input IN3, four-input terminal IN4, outfan Out,
Pull-up circuit 310, switch T1b, the first pull-down circuit the 330, second pull-down circuit 340 and the 3rd pull-down circuit 350.First is defeated
Enter to hold IN1, the second input IN2, the 3rd input IN3 and four-input terminal IN4 receive respectively different clock signal CK_4,
CK1, CK_2 and CK3, and input signal G that signal end IN is exported in order to the outfan receiving previous stage shift registorN-1。
Pull-up circuit 310 and signal end IN, node QNAnd first input end IN1 couples, and in order to according to first input end
The current potential of IN1, control signal end IN and node QNBetween electric connection.Switch T1b and the second input IN2, node QNAnd it is defeated
Go out and hold Out to couple, and in order to according to node QNCurrent potential, control electrically connecting between the second input IN2 and outfan Out
Connect.First pull-down circuit 330 couples with the 3rd input IN3, outfan Out and four-input terminal IN4, and in order to according to the 3rd
The current potential of input IN3, the electric connection between control output end Out and four-input terminal IN4.Second pull-down circuit 340 with
Node QN, first input end IN1 and four-input terminal IN4 couples, and in order to according to the current potential of four-input terminal IN4, controls joint
Point QNAnd the electric connection between first input end IN1.3rd pull-down circuit 350 and node QN, the 3rd input IN3 and the 4th
Input IN4 couples, and in order to the current potential according to the 3rd input IN3, controls node QNAnd the electricity between four-input terminal IN4
Property connect.Wherein first input end IN1, the second input IN2, the 3rd input IN3 and four-input terminal IN4 receive not respectively
Same clock signal CK_4, CK1, CK_2 and CK3.
In an embodiment of the present invention, pull-up circuit 310 comprises switch T1a, and first end of its breaker in middle T1a is coupled to letter
Number end IN, switch T1a the second end be coupled to node QN, and the control end switching T1a is coupled to first input end IN1.Switch
T1a is according to clock signal CK_4, control signal end IN and node QNBetween electric connection.Furthermore, the first pull-down circuit 330 can
Comprising electric capacity C1 and switch T1d, wherein electric capacity C1 is coupled to node QNAnd between outfan Out.First end of switch T1d couples
To outfan Out, second end of switch T1d is coupled to four-input terminal IN4, and the control end switching T1d to be coupled to the 3rd defeated
Enter to hold IN3.Switch T1d is according to clock signal CK_2, the electric connection between control output end Out and four-input terminal IN4.Separately
Outward, the second pull-down circuit 340 comprises switch T1e, and first end of its breaker in middle T1e is coupled to node QN, second end of switch T1e
It is coupled to first input end IN1, and the control end switching T1e is coupled to four-input terminal IN4.Switch T1e is according to clock signal
CK3, controls node QNAnd the electric connection between first input end IN1.Additionally, the 3rd pull-down circuit 350 can comprise electric capacity C2
And switch T1c, wherein electric capacity C2 is coupled to node QNAnd the 3rd between input IN3.First end of switch T1c is coupled to node
QN, second end of switch T1c is coupled to input IN4 when the 4th, and the control end switching T1c is coupled to the 3rd input IN3.
T1c, according to clock signal CK_2, controls node QNAnd the electric connection between four-input terminal IN4.Due to switch T1c and T1d
Using clock signal CK3 as its low level signal, and switch T1e is using clock signal CK_4 as its low level signal, therefore can be
Switch T1c, T1d and T1e because of long operation by positive bias stress (positive bias stress；PBS) effect
Under the influence of, switch T1c, T1d and T1e are imposed periodic reverse blas stress (negative bias stress；NBS) effect
Should, therefore the critical voltage of switch T1c, T1d and T1e has reply effect, the most therefore switchs the driving force of T1c, T1d and T1e
Can be enhanced.
Shift registor 300 can be used for the gate drivers of display floater, and gate driver circuit can comprise multistage shifting
Position buffer 300, is used for providing multiple signal, to control the open and close of the pixel of display floater.Refer to Fig. 4 and
Fig. 5.Fig. 4 is the schematic diagram of the shift scratch circuit 400 of one embodiment of the invention, and the shift scratch circuit 400 that Fig. 5 is Fig. 4
Sequential chart.Shift scratch circuit 400 includes multiple shift registor (such as 300_1 to 300_5).Wherein, each displacement is temporary
The circuit framework of storage 300_1 to 300_5 is identical with shift registor 300 circuit framework of Fig. 3.Shift registor 300_1 is extremely
300_5 can respectively by outfan Out by output signal G1To G5Output is to corresponding gate line (or claiming scan line), with in order
Open the pixel coupled from the different gate lines of display floater.The signal end IN of shift registor 300_2 to 300_5 can connect respectively
Receive output signal G of its previous stage shift registor 300_1 to 300_41To G4, the signal end IN of shift registor 300_1 is then
It is to receive initial signal SP.Additionally, it is the first input end IN1 of shift registor 300_1 and shift registor 300_5, second defeated
Enter to hold IN2, the 3rd input IN3 and four-input terminal IN4 to receive clock signal CK_4, CK1, CK_2 and CK3 respectively；Displacement is temporarily
When the first input end IN1 of storage 300_2, the second input IN2, the 3rd input IN3 and four-input terminal IN4 receive respectively
Arteries and veins signal CK_1, CK2, CK_3 and CK4；The first input end IN1 of shift registor 300_3, the second input IN2, the 3rd defeated
Enter to hold IN3 and four-input terminal IN4 to receive clock signal CK_2, CK3, CK_4 and CK1 respectively；And shift registor 300_4
First input end IN1, the second input IN2, the 3rd input IN3 and four-input terminal IN4 receive respectively clock signal CK_3,
CK4, CK_1 and CK2.Wherein the current potential of clock signal CK1, CK2, CK3 and CK4 can be extremely low at grid high potential VGH and the first grid
Switching between current potential VGL1, the current potential of clock signal CK_1, CK_2, CK_3 and CK_4 can be at grid high potential VGH and second gate
Switch between Very Low Potential VGL2, and second grid electronegative potential VGL2 can be less than first grid electronegative potential VGL1.In the present invention one
In embodiment, grid high potential VGH is positive 20 volts, and first grid electronegative potential VGL1 is negative 10 volts, and the extremely low electricity of second gate
Position VGL2 is negative 13 volts, but the present invention is not limited thereto.
Additionally, each clock signal CK1 to CK4 can be every a cycle TPElevated by first grid electronegative potential VGL1
To grid high potential VGH, and each clock signal CK_1 to CK_4 can be every a cycle TPBy second grid electronegative potential
VGL2 is promoted to grid high potential VGH.Clock signal CK1 to CK_1 has similar sequential, and clock signal CK2 Yu CK_2 has
Similar sequential, clock signal CK3 to CK_3 is had to have a similar sequential, and when clock signal CK4 to CK_4 has similar
Sequence.In detail, clock signal CK1 by first grid electronegative potential VGL1 be promoted to grid high potential VGH time point and by
Grid high potential VGH is reduced to the time point of first grid electronegative potential VGL1, can be with clock signal CK_1 by the extremely low electricity of second gate
Position VGL2 is promoted to the time point of grid high potential VGH and is reduced to second grid electronegative potential by grid high potential VGH
The time point of VGL2 is consistent.Similarly, clock signal CK2 is promoted to grid high potential VGH by first grid electronegative potential VGL1
Time point and be reduced to the time point of first grid electronegative potential VGL1 by grid high potential VGH, can and clock signal CK_2
It is promoted to the time point of grid high potential VGH by second grid electronegative potential VGL2 and is reduced to by grid high potential VGH
The time point of two grid electronegative potential VGL2 is consistent.Clock signal CK3 is promoted to grid height electricity by first grid electronegative potential VGL1
The time point of position VGH and be reduced to the time point of first grid electronegative potential VGL1 by grid high potential VGH, meeting and clock signal
CK_3 is promoted to the time point of grid high potential VGH by second grid electronegative potential VGL2 and is dropped by grid high potential VGH
Consistent to the time point of second grid electronegative potential VGL2.Clock signal CK4 is promoted to grid by first grid electronegative potential VGL1
The time point of high potential VGH and be reduced to the time point of first grid electronegative potential VGL1 by grid high potential VGH, meeting and seasonal pulse
Signal CK_4 is promoted to the time point of grid high potential VGH and by grid high potential VGH by second grid electronegative potential VGL2
The time point being reduced to second grid electronegative potential VGL2 is consistent.
Furthermore, it is grid high potential VGH during clock signal CK1 to CK4 difference, and during clock signal CK1 to CK4 difference is
Grid high potential VGH.As a example by Fig. 5, clock signal CK4, CK1, CK2 and CK3 are respectively at period T1, T3, T5 and T7 in order
For grid high potential VGH, and clock signal CK_4, CK_1, CK_2 and CK_3 at period T1, T3, T5 and T7 are respectively in order
Grid high potential VGH.
Further, since shift scratch circuit 400 operates according to eight clock signal CK1 to CK4 and CK_1 to CK_4,
Therefore shift scratch circuit 400 can be described as eight phases (eight phase) shift scratch circuit.The n-th of shift scratch circuit 400 is moved
The clock signal that four input IN1 to IN4 of position buffer are received, can be defeated with four of (N+4) individual shift registor
Entering the clock signal holding IN1 to IN4 to be received identical, wherein N is positive integer.Such as, the of first shift registor 300_1
One input IN1, the second input IN2, the 3rd input IN3 and four-input terminal IN4 receive respectively clock signal CK_4,
CK1, CK_2 and CK3, and the first input end IN1 of the 5th shift registor 300_5, the second input IN2, the 3rd input
The clock signal that IN3 and four-input terminal IN4 is received also can be clock signal CK_4, CK1, CK_2 and CK3.
For characteristic and the advantage of shift registor 300 can be clearly demonstrated, refer again to Fig. 3 and Fig. 5.In phase period T1
Between, input signal G that shift registor 300 is receivedN-1It is grid high potential VGH with clock signal CK_4, and makes pull-up electricity
The switch T1a on road 310 is unlocked, and causes node QNCurrent potential be grid high potential VGH.Additionally, because of clock signal CK3 and
CK_2 is respectively at first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and clock signal CK_4 is grid high potential
VGH, and make to switch T1e, T1c and T1d and be closed.Additionally, due to clock signal CK1 is in first grid electronegative potential VGL1,
And switch T1b is unlocked, therefore output signal GNCurrent potential can be first grid electronegative potential VGL1.Additionally, because clock signal CK3 is
First grid electronegative potential VGL1, and clock signal CK_4 is grid high potential VGH, therefore the pressure between the gate-to-source of switch T1e
Difference can be great negative value, and make to switch T1e and can be tightly shut off.
During period T2, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK3 and CK_2 is respectively at first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and make to switch T1e,
T1c and T1d is closed.Therefore, node QNCurrent potential can be because of node QNIt is in suspension joint (floating) state and maintains grid height
Current potential VGH.Additionally, because the current potential of clock signal CK1 is still first grid electronegative potential VGL1, therefore output signal GNCurrent potential can tie up
Hold at first grid electronegative potential VGL1.
During period T3, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK_2 is in second grid electronegative potential VGL2, and makes to switch T1c and T1d and be closed.Furthermore, because of clock signal CK1
It is in grid high potential VGH, and switch T1b is unlocked, and make output signal GNCurrent potential be promoted to grid high potential
VGH.It addition, node QNCurrent potential because of the coupling effect of parasitic capacitance of switch T1b and the coupling effect of electric capacity C1, and carried
Rise to the twice (i.e. 2VGH) of grid high potential VGH.Additionally, because clock signal CK3 is first grid electronegative potential VGL1, and seasonal pulse
Signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (about 3 volts),
And because of node QNCurrent potential be 2VGH, therefore switch T1e can be opened slightly, and has electric current from node QNFlow through switch T1e
To first input end IN1.
During period T4, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK_2 is second grid electronegative potential VGL2, and makes to switch T1c and T1d and be closed.It addition, because of clock signal
CK1 is pulled down to first grid electronegative potential VGL1, and makes node QNCurrent potential because of the coupling effect of parasitic capacitance of switch T1b
And it is pulled down to grid high potential VGH from the grid high potential 2VGH of twice.Furthermore, because of clock signal CK1, to be in the first grid extremely low
Current potential VGL1, and node QNCurrent potential be grid high potential VGH, therefore switch T1b can be unlocked, and makes output signal GNElectricity
Position is pulled down to first grid electronegative potential VGL1.It addition, because clock signal CK3 is first grid electronegative potential VGL1, and seasonal pulse letter
Number CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (about 3 volts), and
Because of node QNCurrent potential be VGH, therefore switch T1e can be opened slightly, and has electric current from node QNIt flow to through switch T1e
First input end IN1.
During period T5, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK_2 is grid high potential VGH, and makes to switch T1c and T1d and be unlocked, and makes node QNCurrent potential quilt
It is pulled down to first grid electronegative potential VGL1, and makes output signal GNCurrent potential maintain first grid electronegative potential VGL1.Furthermore, because of
Node QNCurrent potential be first grid electronegative potential VGL1, therefore switch T1b can be closed.It addition, because clock signal CK3 is the first grid
Very Low Potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure between the gate-to-source of switch T1e
Difference can be on the occasion of (about 3 volts), therefore switch T1e can be opened slightly.Again because of node QNCurrent potential be first grid electronegative potential
VGL1 is higher than the second grid electronegative potential VGL2 of first input end IN1, and has the slightest electric current from node QNThrough switch T1e
And it flow to first input end IN1.
During period T6, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK_2 is second grid electronegative potential VGL2, and makes to switch T1c and T1d and be closed.It addition, because of clock signal
The current potential of CK_2 is pulled down to second grid electronegative potential VGL2 from grid high potential VGH, therefore node QNCurrent potential can be because of electric capacity C2
Coupling effect and decline slightly.Switch T1b is then because of node QNCurrent potential less than first grid electronegative potential VGL1 and be closed,
And output signal GNCurrent potential be still maintained at first grid electronegative potential VGL1.It addition, because clock signal CK3 is the extremely low electricity of the first grid
Position VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be
On the occasion of (about 3 volts), and make to switch T1e and can be opened slightly.
During period T7, input signal G that shift registor 300 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK_2 is in second grid electronegative potential VGL2, and makes to switch T1c and T1d and be closed.Furthermore, because of clock signal CK3
It is in grid high potential VGH, therefore switch T1e can fully be opened, and make node QNCurrent potential can be pulled down to second gate
Very Low Potential VGL2.Output signal GNCurrent potential be then still maintained at first grid electronegative potential VGL1.Additionally, rear stage shift register
The node Q of deviceN+1The waveform of current potential and output signal GN+1Waveform can respectively with node QNThe waveform of current potential and output
Signal GNWaveform be similar to, i.e. repeat no more at this.
As shown in the above description, the switch T1e in the period of period T3 to T6, shift registor 300 can be by slightly
Open, and in the period of period T7, switch T1e can fully be opened.Therefore, in the outfan institute of previous stage shift registor
Input signal G of outputN-1Before being the most again pulled to grid high potential VGH by first grid electronegative potential VGL1, although
Clock signal CK1 still can switch between grid high potential VGH and first grid electronegative potential VGL1, but because of switch T1e's
Effect, and the node Q of shift registor 300 can be effectively prevented fromNThe surging at place, therefore can ensure that shift registor 300 can export
There is output signal G of precision waveformN。
In an embodiment of the present invention, the 3rd pull-down circuit 350 of shift registor 300 can be omitted, and second is drop-down
The control end of the switch T1e of circuit 340 changes to receive clock signal CK2.Refer to Fig. 6, Fig. 6 is another embodiment of the present invention
The circuit diagram of shift registor 500.Shift registor 500 comprise signal end IN, first input end IN1, the second input IN2,
3rd input IN3, four-input terminal IN4, the 5th input IN5, outfan Out, pull-up circuit 310, switch T1b, first
Pull-down circuit 330 and the second pull-down circuit 540.First input end IN1, the second input IN2, the 3rd input IN3, the 4th
Input IN4 and the 5th input IN5 receives different clock signal CK_4, CK1, CK_2, CK3 and CK2 respectively, and signal end
Input signal G that IN is exported in order to the outfan receiving previous stage shift registorN-1。
The pull-up circuit 310 of shift registor 500, switch T1b and the function of the first pull-down circuit 330 and mode of operation with
The pull-up circuit 310 of shift registor 300, switch T1b and the first pull-down circuit 330 are identical, therefore repeat no more.Additionally, displacement
Second pull-down circuit 540 of buffer 500 and node QN, first input end IN1 and the 5th input IN5 couples, and in order to depend on
According to the current potential of the 5th input IN5, control node QNAnd the electric connection between first input end IN1.Implement in the present invention one
In example, the second pull-down circuit 540 comprises switch T1e.First end of switch T1e is coupled to node QN, the second end coupling of switch T1e
It is connected to first input end IN1, and the control end switching T1e is coupled to the 5th input IN5.Switch T1e is according to clock signal
CK2, controls node QNAnd the electric connection between first input end IN1.Owing to switch T1d and T1e is respectively with clock signal CK3
With CK_4 as its low level signal, therefore T1d and T1e can switched because of long operation by positive bias stress (PBS)
Under the influence of effect, switch T1d and T1e is imposed periodic reverse blas stress (NBS) effect, therefore switchs facing of T1d and T1e
Boundary's voltage has reply effect, and the most therefore the driving force of switch T1d and T1e can be enhanced.
Shift registor 500 can be used for the gate drivers of display floater, and gate driver circuit can comprise multistage shifting
Position buffer 500, is used for providing multiple signal, to control the open and close of the pixel of display floater.Refer to Fig. 7 and
Fig. 5.Fig. 7 is the schematic diagram of the shift scratch circuit 700 of one embodiment of the invention.Shift scratch circuit 700 includes multiple shifting
Position buffer (such as 500_1 to 500_5).Wherein, the circuit framework of each shift registor 500_1 to 500_5 and the displacement of Fig. 6
Buffer 500 circuit framework is identical.Shift registor 500_1 to 500_5 can respectively by outfan Out by output signal G1To G5
Output is to corresponding gate line (or claiming scan line), the pixel coupled with the different gate lines opened in order from display floater.
The signal end IN of shift registor 500_2 to 500_5 can receive the defeated of its previous stage shift registor 500_1 to 500_4 respectively
Go out signal G1To G4, the signal end IN of shift registor 500_1 is then to receive initial signal SP.Additionally, shift registor 500_
The first input end IN1 of 1 and shift registor 500_5, the second input IN2, the 3rd input IN3, four-input terminal IN4 and
5th input IN5 receives clock signal CK_4, CK1, CK_2, CK3 and CK2 respectively.First input of shift registor 500_2
End IN1, the second input IN2, the 3rd input IN3, four-input terminal IN4 and the 5th input IN5 receive seasonal pulse letter respectively
Number CK_1, CK2, CK_3, CK4 and CK3.The first input end IN1 of shift registor 500_3, the second input IN2, the 3rd defeated
Enter to hold IN3, four-input terminal IN4 and the 5th input IN5 to receive clock signal CK_2, CK3, CK_4, CK1 and CK4 respectively.Move
Position the first input end IN1 of buffer 500_4, the second input IN2, the 3rd input IN3, four-input terminal IN4 and the 5th
Input IN5 receives clock signal CK_3, CK4, CK_1, CK2 and CK1 respectively.
Owing to shift scratch circuit 700 operates according to eight clock signal CK1 to CK4 and CK_1 to CK_4, therefore move
Position buffering circuit 700 is also a kind of eight phase shift buffering circuits.Five of the n-th shift registor of shift scratch circuit 700
The clock signal that input IN1 to IN5 is received, can be with five input IN1 to IN5 institutes of (N+4) individual shift registor
The clock signal received is identical, and wherein N is positive integer.Such as, the first input end IN1 of first shift registor 500_1,
Two input IN2, the 3rd input IN3, four-input terminal IN4 and the 5th input IN5 receive respectively clock signal CK_4,
CK1, CK_2, CK3 and CK2, and the first input end IN1 of the 5th shift registor 500_5, the second input IN2, the 3rd defeated
The clock signal entering to hold IN3, four-input terminal IN4 and the 5th input IN5 to be received also can be clock signal CK_4, CK1,
CK_2, CK3 and CK2.
Refer again to Fig. 6 and Fig. 5.During period T1, input signal G that shift registor 500 is receivedN-1And seasonal pulse
Signal CK_4 is grid high potential VGH, and the switch T1a of pull-up circuit 310 is unlocked, and causes node QNCurrent potential be
Grid high potential VGH.Additionally, be respectively at first grid electronegative potential VGL1 because of clock signal CK3 and CK_2 and second gate is extremely low
Current potential VGL2, and make to switch T1d and be closed.Furthermore, because clock signal CK_4 is grid high potential VGH, and clock signal CK2
Current potential be first grid electronegative potential VGL1, therefore the pressure reduction between the gate-to-source of switch T1e can be great negative value, and makes
T1e must be switched can be tightly shut off.Additionally, due to clock signal CK1 is in first grid electronegative potential VGL1, and switch T1b
It is unlocked, therefore output signal GNCurrent potential can be first grid electronegative potential VGL1.
During period T2, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK3 and CK_2 is respectively at first grid electronegative potential VGL1 and second grid electronegative potential VGL2, and makes to switch T1d quilt
Close.Furthermore, because the current potential of clock signal CK2 is first grid electronegative potential VGL1, therefore switch T1e can be closed.Therefore, node
QNCurrent potential can be because of node QNIt is in floating and maintains grid high potential VGH.Additionally, because of clock signal CK1 current potential still
For first grid electronegative potential VGL1, therefore output signal GNCurrent potential can maintain first grid electronegative potential VGL1.
During period T3, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK_2 is in second grid electronegative potential VGL2, and makes to switch T1d and be closed.Furthermore, because clock signal CK1 is in grid
High current potential VGH, and switch T1b is unlocked, and makes output signal GNCurrent potential be promoted to grid high potential VGH.It addition,
Node QNCurrent potential because of the coupling effect of parasitic capacitance of switch T1b and the coupling effect of electric capacity C1, and be promoted to grid
The twice (i.e. 2VGH) of high potential VGH.Additionally, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_4
For second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (about 3 volts), and because of node
QNCurrent potential be 2VGH, therefore switch T1e can be opened slightly, and has electric current from node QNIt flow to first defeated through switch T1e
Enter to hold IN1.
During period T4, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK_2 is second grid electronegative potential VGL2, and makes to switch T1d and be closed.It addition, because of clock signal CK1 quilt
It is pulled down to first grid electronegative potential VGL1, and makes node QNCurrent potential because switch T1b parasitic capacitance coupling effect and from
The grid high potential 2VGH of twice is pulled down to grid high potential VGH.Furthermore, because clock signal CK1 is in first grid electronegative potential
VGL1, and node QNCurrent potential be grid high potential VGH, therefore switch T1b can be unlocked, and makes output signal GNCurrent potential quilt
It is pulled down to first grid electronegative potential VGL1.It addition, because clock signal CK2 is first grid electronegative potential VGL1, and clock signal CK_
4 is second grid electronegative potential VGL2, therefore the pressure reduction between the gate-to-source of switch T1e can be on the occasion of (about 3 volts), and because of joint
Point QNCurrent potential be VGH, therefore switch T1e can be opened slightly, and has electric current from node QNIt flow to first through switch T1e
Input IN1.
During period T5, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK and CK_2 is grid high potential VGH, and makes to switch T1d and T1e and be unlocked, and makes node QNElectricity
Position is pulled down to second grid electronegative potential VGL2, and makes output signal GNCurrent potential to maintain first grid electronegative potential VGL1 attached
Closely.Furthermore, because of node QNCurrent potential be second grid electronegative potential VGL2, therefore switch T1b can be closed.
During period T6, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
The current potential of arteries and veins signal CK_2 is second grid electronegative potential VGL2, and makes to switch T1d and be closed.It addition, because clock signal CK2 is
First grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, thus the gate-to-source of switch T1e it
Between pressure reduction can be on the occasion of (about 3 volts), and make to switch T1e and can be opened slightly, and make node QNCurrent potential maintain
In second grid electronegative potential VGL2, output signal GNCurrent potential then maintain near first grid electronegative potential VGL1.
During period T7, input signal G that shift registor 500 is receivedN-1It is respectively first with clock signal CK_4
Grid electronegative potential VGL1 and second grid electronegative potential VGL2, and the switch T1a of pull-up circuit 310 is closed.Additionally, because of time
Arteries and veins signal CK_2 is in second grid electronegative potential VGL2, and makes to switch T1d and be closed.Furthermore, because clock signal CK2 is first
Grid electronegative potential VGL1, and clock signal CK_4 is second grid electronegative potential VGL2, therefore between the gate-to-source of switch T1e
Pressure reduction can be on the occasion of (about 3 volts), and make to switch T1e and can be opened slightly, and makes node QNCurrent potential maintain
Two grid electronegative potential VGL2, output signal GNCurrent potential then maintain near first grid electronegative potential VGL1.Additionally, rear stage moves
The node Q of position bufferN+1The waveform of current potential and output signal GN+1Waveform can respectively with node QNThe waveform of current potential
And output signal GNWaveform be similar to, i.e. repeat no more at this.
As shown in the above description, the switch T1e in the period of period T3, T4, T6 and T7, shift registor 500 can quilt
Open slightly, and in the period of period T5, switch T1e can fully be opened.Therefore, defeated at previous stage shift registor
Go out input signal G that end is exportedN-1The most again by first grid electronegative potential VGL1 be pulled to grid high potential VGH it
Before, although clock signal CK1 still can switch between grid high potential VGH and first grid electronegative potential VGL1, but because opening
Close the effect of T1e, and the node Q of shift registor 500 can be effectively prevented fromNThe surging at place, therefore can ensure that shift registor 500
Output signal G with precision waveform can be exportedN。
Additionally, in the above description, clock signal CK1, CK_1, CK2, CK_2, CK3, CK_3, CK4, CK_4 also can distinguish
It is referred to as the second clock signal, the 6th clock signal, the 5th clock signal, the 3rd clock signal, the 4th clock signal, the 7th seasonal pulse
Signal, the 8th clock signal and the first clock signal.Shift registor 300_1 and 500_1 is also referred to as the first shift registor.
Shift registor 300_2 and 500_2 is also referred to as the second shift registor.Shift registor 300_3 and 500_3 is also referred to as
Three shift registors.Shift registor 300_4 and 500_4 is also referred to as the 4th shift registor.Electric capacity C1 is also referred to as first
Electric capacity, and electric capacity C2 is also referred to as the second electric capacity.Switch T1b, T1c and T1d also can be called the first switch, the 3rd switch and
Second switch.During additionally, period T1, T3, T5 and T7 also can be called the first period, the second period, the 3rd period and the 4th
Section.It addition, the G in graphicN+1Refer to " input signal " of shift registor 100 in the prior art, and in the embodiment of the present invention
In then refer to " output signal " of rear stage shift registor, spy is explained.
In sum, by the shift registor of the embodiment of the present invention, owing to the switch of each pull-down circuit is all believed with seasonal pulse
Number as its low level signal, thus can at the switch of each pull-down circuit because of operation for a long time by positive bias stress (PBS)
Under the influence of effect, the switch of pull-down circuit is imposed periodic reverse blas stress (NBS) effect, with to critical voltage
(Vth) produce recovery effect, improve driving force and decline problem.Additionally, the switch of the second pull-down circuit can the most slightly
Open or fully open, therefore can suppress to result from the control of the first switch because of the coupling effect of the parasitic capacitance of the first switch
The surging of end.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent with
Modify, all should belong to the covering scope of the present invention.
Claims (13)
1. a shift registor, it is characterised in that comprise:
One signal end, receives an input signal；
One first input end, receives one first clock signal；
One second input, receives one second clock signal；
One the 3rd input, receives one the 3rd clock signal；
One four-input terminal, receives one the 4th clock signal；
One outfan；
One pull-up circuit, couples with this signal end and this first input end, and in order to according to this first clock signal, to control this letter
Number end with a node between electric connection；
One first switch, couples with this second input, this node and this outfan, and in order to the current potential according to this node, control
Make the electric connection between this second input and this outfan；
One first pull-down circuit, couples with the 3rd input, this outfan and this four-input terminal, and in order to according to the 3rd
Clock signal, controls the electric connection between this outfan and this four-input terminal；And
One second pull-down circuit, couples with this node and this first input end, and in order to according to the 4th clock signal or one
Five clock signals, control the electric connection between this node and this first input end；
This first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are respectively one first
Period, one second period, one the 3rd period and one the 4th period are a grid high potential, and this first period, this second period,
3rd period and the 4th period order on a timeline are sequentially this first period, this second period, the 3rd period
And the 4th period, and this first clock signal, this second clock signal, the 3rd clock signal and the 4th clock signal are not
It it is this grid high potential simultaneously.
Shift registor the most according to claim 1, it is characterised in that this first pull-down circuit comprises:
One first electric capacity, is coupled between this node and this outfan；And
One second switch, one first end of this second switch couples this outfan, and one second end of this second switch is coupled to this
Four-input terminal, and the one of this second switch control end couples the 3rd input.
Shift registor the most according to claim 1, it is characterised in that this second pull-down circuit is according to this four clock signal
Control the electric connection between this node and this first input end.
Shift registor the most according to claim 3, it is characterised in that additionally comprise:
One the 3rd pull-down circuit, couples with this node, the 3rd input and this four-input terminal, and in order to during according to the 3rd
Arteries and veins signal, controls the electric connection between this node and this four-input terminal.
Shift registor the most according to claim 4, it is characterised in that the 3rd pull-down circuit comprises:
One second electric capacity, is coupled between this node and the 3rd input；And
One the 3rd switch, one first end of the 3rd switch couples this node, and one second end of the 3rd switch couples the 4th
Input, and a control end of the 3rd switch couples the 3rd input.
Shift registor the most according to claim 1, it is characterised in that further include one the 5th input, in order to receive this
Five clock signals, wherein this second pull-down circuit is separately coupled to the 5th input, to control this joint according to this five clock signal
Electric connection between point and this first input end, and the 5th clock signal is this grid high potential in the 3rd period.
7. according to the shift registor described in claim 1 or 6, it is characterised in that this second clock signal and the 4th seasonal pulse
Signal switches between this grid high potential and a first grid electronegative potential, and this first clock signal and the 3rd clock signal exist
Switch between this grid high potential and a second grid electronegative potential, and this first grid electronegative potential is higher than the extremely low electricity of this second gate
Position.
8. a shift scratch circuit, comprises multiple shift registor, it is characterised in that each shift registor comprises:
One signal end；
One first input end；
One second input；
One the 3rd input；
One four-input terminal；
One outfan；
One pull-up circuit, couples with this signal end, a node and this first input end, and in order to the electricity according to this first input end
Position, controls the electric connection between this signal end and this node；
One first switch, couples with this second input, this node and this outfan, and in order to the current potential according to this node, control
Make the electric connection between this second input and this outfan；
One first pull-down circuit, couples with the 3rd input, this outfan and this four-input terminal, and in order to according to the 3rd
The current potential of input, controls the electric connection between this outfan and this four-input terminal；
One second pull-down circuit, couples with this node, this first input end and this four-input terminal, and in order to defeated according to the 4th
Enter the current potential of end, control the electric connection between this node and this first input end；And
One the 3rd pull-down circuit, couples with this node, the 3rd input and this four-input terminal, and in order to defeated according to the 3rd
Enter the current potential of end, control the electric connection between this node and this four-input terminal；
When wherein this first input end, this second input, the 3rd input and this four-input terminal receive different respectively
Arteries and veins signal；
Those shift registors comprise one first shift registor, one second shift registor, one the 3rd shift registor and
4th shift registor；
Wherein this signal end of this first shift registor receives an initial signal, this first input of this first shift registor
End receives one first clock signal, and this second input of this first shift registor receives one second clock signal, and this is first years old
3rd input of shift registor receives one the 3rd clock signal, and this four-input terminal of this first shift registor connects
Receive one the 4th clock signal；
Wherein this signal end of this second shift registor couples this outfan of this first shift registor, and this second displacement is temporarily
This first input end of storage receives one the 6th clock signal, and this second input of this second shift registor receives one the 5th
Clock signal, the 3rd input reception one the 7th clock signal of this second shift registor, and this second shift registor
This four-input terminal receive one the 8th clock signal；
Wherein this signal end of the 3rd shift registor couples this outfan of this second shift registor, and the 3rd displacement is temporarily
This first input end of storage receives the 3rd clock signal, and this second input of the 3rd shift registor receives the 4th
Clock signal, the 3rd input of the 3rd shift registor receives this first clock signal, and the 3rd shift registor
This four-input terminal receive this second clock signal；And
Wherein this signal end of the 4th shift registor couples this outfan of the 3rd shift registor, and the 4th displacement is temporarily
This first input end of storage receives the 7th clock signal, and this second input of the 4th shift registor receives the 8th
Clock signal, the 3rd input of the 4th shift registor receives the 6th clock signal, and the 4th shift registor
This four-input terminal receive the 5th clock signal.
Shift scratch circuit the most according to claim 8, it is characterised in that the 3rd pull-down circuit comprises:
One second electric capacity, is coupled between this node and the 3rd input；And
One the 3rd switch, one first end of the 3rd switch couples this node, and one second end of the 3rd switch couples the 4th
Input, and a control end of the 3rd switch couples the 3rd input.
10. a shift scratch circuit, comprises multiple shift registor, it is characterised in that and each shift registor comprises:
One signal end；
One first input end；
One second input；
One the 3rd input；
One four-input terminal；
One the 5th input；
One outfan；
One pull-up circuit, couples with this signal end, a node and this first input end, and in order to the electricity according to this first input end
Position, controls the electric connection between this signal end and this node；
One first switch, couples with this second input, this node and this outfan, and in order to the current potential according to this node, control
Make the electric connection between this second input and this outfan；
One first pull-down circuit, couples with the 3rd input, this outfan and this four-input terminal, and in order to according to the 3rd
The current potential of input, controls the electric connection between this outfan and this four-input terminal；And
One second pull-down circuit, couples with this node, this first input end and the 5th input, and in order to defeated according to the 5th
Enter the current potential of end, control the electric connection between this node and this first input end；
Wherein this first input end, this second input, the 3rd input, this four-input terminal and the 5th input are respectively
Receive different clock signals；
Those shift registors comprise one first shift registor, one second shift registor, one the 3rd shift registor and
4th shift registor；
Wherein this signal end of this first shift registor receives an initial signal, this first input of this first shift registor
End receives one first clock signal, and this second input of this first shift registor receives one second clock signal, and this is first years old
3rd input of shift registor receives one the 3rd clock signal, and this four-input terminal of this first shift registor receives
One the 4th clock signal, and the 5th input of this first shift registor receives one the 5th clock signal；
Wherein this signal end of this second shift registor couples this outfan of this first shift registor, and this second displacement is temporarily
This first input end of storage receives one the 6th clock signal, and this second input of this second shift registor receives the 5th
Clock signal, the 3rd input of this second shift registor receives one the 7th clock signal, this second shift registor
This four-input terminal receives one the 8th clock signal, and the 5th input of this second shift registor receives the 4th seasonal pulse
Signal；
Wherein this signal end of the 3rd shift registor couples this outfan of this second shift registor, and the 3rd displacement is temporarily
This first input end of storage receives the 3rd clock signal, and this second input of the 3rd shift registor receives the 4th
Clock signal, the 3rd input of the 3rd shift registor receives this first clock signal, the 3rd shift registor
This four-input terminal receives this second clock signal, and the 5th input of the 3rd shift registor receives the 8th seasonal pulse
Signal；And
Wherein this signal end of the 4th shift registor couples this outfan of the 3rd shift registor, and the 4th displacement is temporarily
This first input end of storage receives the 7th clock signal, and this second input of the 4th shift registor receives the 8th
Clock signal, the 3rd input of the 4th shift registor receives the 6th clock signal, the 4th shift registor
This four-input terminal receives the 5th clock signal, and the 5th input of the 4th shift registor receives this second seasonal pulse
Signal.
11. shift scratch circuits according to claim 10, it is characterised in that this first pull-down circuit comprises:
One first electric capacity, is coupled between this node and this outfan；And
One second switch, one first end of this second switch couples this outfan, and one second end of this second switch is coupled to this
Four-input terminal, and the one of this second switch control end couples the 3rd input.
12. shift scratch circuits according to claim 10, it is characterised in that this first clock signal, this second seasonal pulse
Signal, the 3rd clock signal and the 4th clock signal are respectively in one first period, one second period, one the 3rd period and one
4th period was a grid high potential, when the 8th clock signal, the 6th clock signal, the 5th clock signal and the 7th
Arteries and veins signal is this grid high potential in this first period, this second period, the 3rd period and the 4th period respectively, and this
One period, this second period, the 3rd period and the 4th period order on a timeline be sequentially this first period, this
Two periods, the 3rd period and the 4th period, this first clock signal, this second clock signal, the 3rd clock signal and
It is this grid high potential during the 4th clock signal difference, and the 5th clock signal, the 6th clock signal, the 7th seasonal pulse
It it is this grid high potential when signal and the 8th clock signal difference.
13. shift scratch circuits according to claim 12, it is characterised in that this second clock signal, the 4th seasonal pulse
Signal, the 5th clock signal and the 8th clock signal switch between this grid high potential and a first grid electronegative potential,
This first clock signal, the 3rd clock signal, the 6th clock signal and the 7th clock signal at this grid high potential and
Switch between one second grid electronegative potential, and this first grid electronegative potential is higher than this second grid electronegative potential.
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| TW103104773 | 2014-02-13 | ||
| TW103104773A TWI505276B (en) | 2014-02-13 | 2014-02-13 | Shift register circuit and shift register |
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| TWI544491B (en) * | 2014-09-10 | 2016-08-01 | 友達光電股份有限公司 | Shift register circuit |
| CN104575436B (en) | 2015-02-06 | 2017-04-05 | 京东方科技集团股份有限公司 | Shift register cell, gate driver circuit and display device |
| CN104751816B (en) * | 2015-03-31 | 2017-08-15 | 深圳市华星光电技术有限公司 | Shift-register circuit |
| CN104715733A (en) * | 2015-04-09 | 2015-06-17 | 京东方科技集团股份有限公司 | Shifting register unit, driving circuit, method, array substrate and display device |
| CN105161134B (en) * | 2015-10-09 | 2018-10-23 | 京东方科技集团股份有限公司 | Shift register cell and its operating method, shift register |
| CN105741745A (en) * | 2016-05-12 | 2016-07-06 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit and display panel |
| CN106448606A (en) * | 2016-11-23 | 2017-02-22 | 深圳市华星光电技术有限公司 | GOA (gate driver on array) driving circuit |
| TWI606438B (en) * | 2017-02-16 | 2017-11-21 | 友達光電股份有限公司 | Shift register circuit |
| CN113936585B (en) * | 2021-11-08 | 2023-05-02 | 福建华佳彩有限公司 | GIP circuit for reducing display abnormality and method thereof |
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| CN103956133A (en) | 2014-07-30 |
| TWI505276B (en) | 2015-10-21 |
| TW201532058A (en) | 2015-08-16 |
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