CN103944568B - A kind of sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit - Google Patents
A kind of sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit Download PDFInfo
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Abstract
Circuit is produced the present invention relates to a kind of sampling clock for the time-interleaved analog-digital converter of multichannel, it is made up of multiphase clock generation module, duty ratio recovery circuit and channel selecting module, multi-phase clock signal wherein needed for multiphase clock generation module generation multichannel digital analog converter, the phase error to multi-phase clock signal is compensated simultaneously, it is ensured that the accuracy of the sampling clock of analog-digital converter interchannel；The multiphase clock that multiphase clock generation module is produced is carried out edge adjustment operation by duty ratio recovery circuit, that is, carry out dutycycle recovery, the multi-phase clock signal of output as sampling hold circuit sampled clock signal；Channel selecting module receives the control code of outside serial ports write-in, judge the inner passage number for needing, and control being switched on and off for inner passage, while leggy pulse module inside multiphase clock is selected according to control code, to generate with realizing different channel selecting down-sampling clocks.
Description
Technical field
Circuit is produced the present invention relates to a kind of sampling clock for the time-interleaved analog-digital converter of multichannel, belongs to integrated
Circuit mixed-signal designs field, is mainly used in the error of reduction sampling clock in the time-interleaved converter of multichannel, improves
The performance of converter.
Background technology
Black in 1980 and Hodges propose the time-interleaved ADC technologies of multichannel for the first time, and the technology is by multiple low samplings
The sub- ADC concurrent workings of rate, are interweaved by sampling clock and same input signal are sampled so as to improve sampling rate, and the technology exists
The requirement of each sub- ADC is reduced in the case of realizing identical sample rate so that it obtains more next in high-speed, high precision converter
More applications.
It is corresponding also due to interchannel mismatch although the time-interleaved analog-digital converter of multichannel can improve sample rate
Producing the error of error, interchannel mainly includes three kinds：Sampling clock error, gain error and mismatch error, other documents are also
The bandwidth error of interchannel is increased, but wherein first three is main error source.With the time-interleaved technology of multichannel
Occur, the collimation technique to these three errors is also constantly suggested, and it is broadly divided into Foreground calibration technology and background calibration techniques
Two classes, Foreground calibration needs to refer to input signal, and the result after analog-digital converter is changed is obtained compared with reference result
The result of compensation is needed, then is fed back to actually enter, the advantage of the method is fairly simple calibration structure, but have the disadvantage
Need to interrupt the normal work of converter, and real time calibration can not be realized.Background calibration can be calibrated in real time, Er Qieke
Carried out with when converter works, but need the extraction error from unknown input often more difficult, it is general main by statistics
Mode obtain error and then compensating again.Due in order to ensure the continuity and agility of system application, background calibration skill
Art application it is more extensive.
In general, mismatch error is a kind of DC error, can be regarded as systematic error, and most is to be based on
Random copped wave（chopping）Method, by being modulated to input signal after remove signal DC component, by cumulative system
Meter obtains offset error, then elimination error is compensated to it, and its DC component, the party are recovered after finally output is demodulated
Method can be very good to eliminate the influence of mismatch error, but should be noted to introduce after chopping switches to speed and precision
Influence.For eliminating gain error, it mainly also has Foreground calibration technology and a background calibration techniques, but background calibration side
Method is on the basis of hardware costs is increased, and its improvement to performance is not obvious, often more sides using Foreground calibration
Formula eliminates the error.
With the fast development of high-speed, high precision converter, the sample rate of GSPS is realized using the time-interleaved technology of multichannel
More and more generally, the requirement therefore to the sampling clock error of interchannel is harsher, often as ultrahigh speed converter
The bottleneck of design.Likewise, being also classified into Foreground calibration and background calibration for the calibration of sampling clock error, Foreground calibration needs
Reference-input signal, this reference signal can be ramp signal, triangular signal or sinusoidal signal, but this is in frequency applications
Situation significantly increase the cost of hardware, and the method inherently has great defect, it is impossible to enough according to environmental change
Calibrated.Background calibration method mainly has following four mode：Global sampling hold circuit, global sampling clock, clock
Mismatch compensation and delay-locked loop（DLL）Technology.Global sampling hold circuit has been inherently eliminated the multichannel time
Sampling clock error between intertexture converter channel is, it is necessary to the sampling hold circuit of high-speed, high precision, but it and time-interleaved skill
The basic thought of art is runed counter to, and is not the performance that converter is improved simply by the mode for increasing power consumption, is significantly increased
The difficulty of design, in actual design not in this way；Global sampling clock technology passes through global clock signal and leads to
Sampled after road sampled clock signal synchronization, but global sampling switch introduced so in sampling process and precision is have impact on,
Clock feedthrough and the channel charge injection of sampling switch bring new error；Clock mismatch compensation technique is using complicated filtering
Device group structure reduces interchannel sampling clock error, and in addition to improving hardware costs, the nonlinearity erron of system itself do not have
There is method to eliminate；Delay-locked loop（DLL）Technology is that a kind of application at present is relatively more extensive eliminates interchannel sampling clock error
Structure, but to obtain precision higher needs more controllable time delay line units, which limits speed, so will basis
It is required that trading off treatment between speed and precision.
Fig. 1 describes the principle of global sampling clock technology, as the clock CLKi of each passage（I=1,2 ..., M）And the overall situation
When sampling clock CLK is simultaneously high, input signal is sampled, the single channel sampling clock sampling time is global sampling clock
The half in cycle, the always ability step-down after global sampling clock CLK is low level per channel clock CLKi, due to the sampling time by
The trailing edge decision of global sampling clock CLK, eliminates the phase error of interchannel sampling clock CLKi.Adopted due to introducing the overall situation
Sample switch can also produce new error：Global sampling switch introduces parasitic capacitance, when single channel clock CLKi disconnects, parasitic electricity
The electric charge of appearance can be lost, and influence the precision of setting up of holding phase, and the mismatch to cause in multipath A/D converter output
Imbalance is spuious, and then reduces signal to noise ratio, and because clock feedthrough and channel charge injection also can during global sampling switch disconnection
The imbalance of influence single channel analog-digital converter, gain and nonlinearity erron, bring the decline of analog-digital converter dynamic property.
Fig. 2 gives a kind of implementation of clock mismatch compensation technique, and the structure of the implementation includes input point
Solution wave filter 201, sub- ADC202, interpolation filter 203, digital filter 204 and reconfiguration unit 205.Input signal enters divides
Solution wave filter 201 decomposed in different frequency bands, resolution filter 201 both can be continuous time filter can also be from
Termporal filter is dissipated, is needed in the case that working frequency is higher using simulated time wave filter.Then the signal after decomposing enters
Enter each sub- ADC202 to be changed, the data signal for obtaining carries out digital interpolative computing into interpolation filter 203, and its result is entered
Enter digital filter 204 to be filtered, eventually enter into reconfiguration unit 205 and be reconstructed output signal, filter is decomposed using input
Ripple device 201 and digital filter 204 can be averaged to sampling clock error so as to realize compensation.But due to introducing mould
Intend wave filter, increased hardware costs and power consumption, and cause that design difficulty is further increased.
Fig. 3 gives the method that multi-channel sampling clocking error is eliminated based on delay-locked loop.Skill is compensated with clock mismatch
Art except that, the method not by carrying out error extraction and compensation to converter output result, but being adopted between multichannel
Sample clocking error is calibrated.The delay-locked loop includes phase discriminator 301, charge pump 302, low pass filter 303, controllable prolongs
When line 304 and clock distributing network 305.Phase discriminator 301 receives the feedback clock of input clock signal and clock distributing network 305
Signal, enters line phase and compares operation, and the result for comparing operation is input into charge pump 302, by controlling charge pump 302
The time being switched on and off adjusts the output voltage of low pass filter 303, and the output voltage after the adjustment is input to controllable
In delay line 305, the phase of output clock is adjusted by closed-loop control.Delay-locked loop can set controllable time delay line 304
The quantity of internal delay units come obtain out of phase difference precision equiphase clock signal, but delay-locked loop is for reality
Now lock, it is desirable to which the difference of input clock signal and feedback clock signal is zero, that is to say, that when feedback clock signal is input
The clock signal delay integer clock cycle obtains, and this design just to whole loop increased difficulty, in order to ensure phase high
Position calibration accuracy, the quantity of delay unit can be a lot, realized then according to digital method it is difficult to ensure that it is in high-frequency work, if
Realize then needing to ensure that delay unit has good noise inhibiting ability using analogy method, any electricity when converter works
Source, the noise of substrate coupling can all influence the precision of its phase alignment, and in clock distributing network 305 during each multi-channel sampling
The mismatch of the clock distribution path of clock will further increase the error of multi-channel sampling clock.
In the time-interleaved A/D converter with high speed and high precision of multichannel, the gain error of interchannel, offset error and adopt
Sample clocking error can influence the static state and dynamic property of converter, reduce conversion accuracy, it is necessary to be calibrated for error to it, and lead to
Sampling clock error between road has become the bottleneck of Ultrahigh speed data converter design, and converter output data is counted
The method for extracting interchannel sampling clock error and compensation is difficult to obtain good effect, therefore, how preferably to be led to more
Road sampling clock just turns into a kind of trend of current circuit design.
The content of the invention
Above-mentioned deficiency it is an object of the invention to overcome prior art, there is provided one kind is used for the time-interleaved modulus of multichannel
The sampling clock of converter produces circuit, the sampling clock produce circuit can produce multipath A/D converter needed for multichannel
Equiphase sampling clock, has carried out calibration design, it is ensured that can be obtained under high-frequency clock to interchannel clocking error in addition
To equiphase multi-channel sampling clock signal, the sampling precision of sampling hold circuit in analog-digital converter is improved.
What above-mentioned purpose of the invention was mainly achieved by following technical solution：
A kind of sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, including multiphase clock to produce
Module, duty ratio recovery circuit and channel selecting module, the multiphase clock generation module include two phase clock module and many
Phase impulse module, wherein：
Two phase clock module：By the global clock signal of outside input carry out it is anti-phase after obtain anti-phase global clock signal,
Carry out phase difference calibration to the global clock signal and anti-phase global clock signal, and by the global clock signal after calibration and
Anti-phase global clock signal output gives leggy pulse module；
Leggy pulse module：The control signal 2 of receiving channel selecting module output and the school of two phase clock module output
Global clock signal and anti-phase global clock signal after standard, by global clock signal and inverting clock signal after the calibration
Enter the partite transport of line phase two respectively by internal several multiphase clock generation units to calculate, and two for calculating the partite transport of phase two respectively
Individual result carries out phase difference calibration, a series of pulse signal of equiphase differences is obtained, by the output of pulse signal to dutycycle
Restoring circuit；
Duty ratio recovery circuit：The pulse signal received from leggy pulse module is carried out into dutycycle recovery, and is exported
Sampled clock signal gives outside multipath A/D converter；
Channel selecting module：The control signal 1 of outside serial ports write-in is received, is judged in needs according to the control signal
Portion's port number, and being switched on and off for inner passage is controlled, while being selected in leggy pulse module according to the control signal 1
The quantity of portion's multiphase clock generation unit, and selection result is exported as control signal 2 give leggy pulse module.
In the above-mentioned sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, two phase clock module bag
Include unilateral along phase discriminator, the first wave filter, difference amplifier and controllable time delay line, wherein unilateral receive outside input along phase discriminator
Global clock signal and controllable time delay line output anti-phase global clock signal, carry out phase demodulation operation, obtain two prescription ripples letter
Number, export to the first wave filter；First wave filter receives two groups of square-wave signals, extracts DC component, and by two groups of direct currents
Component is exported to difference amplifier；Difference amplifier seeks difference operation to two groups of DC component signals, and difference operation result will be asked to make
For control signal 3 is input to controllable time delay line, controllable time delay line receives global clock signal and the amplifier output of outside input
Control signal 3, adjust global clock signal phase obtain reverse global clock signal, when reverse global clock phase with
When the phase of global clock signal differs 180 °, phase alignment is completed, during by the global clock signal after calibration and the reverse overall situation
Clock signal output gives leggy pulse module, while the reverse global clock signal output after by calibration is to unilateral along phase discriminator.
In the above-mentioned sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, leggy pulse module
By multistage there is mutually isostructural multiphase clock generation unit to constitute, every grade of multiphase clock generation unit includes pulses generation
Circuit and several phase calibration circuitries, wherein：The control signal 2 and two of pulse-generating circuit receiving channel selecting module output
Global clock signal and anti-phase global clock signal after the calibration of phase clock module output, select according to the control signal 2
The quantity of internal multiphase clock generation unit, obtains after global clock signal and anti-phase global clock signal are carried out into phase operation
To pulse signal, by the output of pulse signal to phase calibration circuitry；Several phase calibration circuitries are by the pulse signal
Enter the calculation of the partite transport of line phase two respectively, and two results to the calculation of the partite transport of phase two carry out phase difference calibration respectively, obtain a series of
The pulse signal of equiphase difference, by the output of pulse signal to duty ratio recovery circuit.
In the above-mentioned sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, each phase alignment electricity
Road include it is bilateral along phase discriminator, charge pump, the second wave filter and delay line, wherein bilateral receive pulse-generating circuit along phase-sensitive detector
The pulse signal of pulse signal and the delay line output of output, and phase demodulation operation is carried out to two pulse signals, obtain two prescriptions
Ripple signal, exports to charge pump；Charge pump receives two groups of square-wave signals, by the output electricity of square-wave signal adjustment charge pump
Pressure, and voltage signal after output adjustment gives the second wave filter；Second wave filter is filtered to the voltage signal after adjustment, carries
Cut-off flow component is input to delay line as control signal 4；Delay line receives the pulse signal and the of pulse-generating circuit output
The control signal 4 of two wave filters output, enters the pulse signal calculation of the partite transport of line phase two and obtains two pulse signals, when described
The phase difference of two pulse signals be input pulse signal rising edge to the trailing edge time difference half when, completion phase school
Standard, and the pulse signal after calibration is exported to the bilateral pulse along phase discriminator and next stage multiphase clock generation unit simultaneously
Produce circuit.
In the above-mentioned sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, duty ratio recovery circuit
Including edge adjustment circuit, buffer circuit, the 3rd wave filter and difference amplifier, wherein edge adjustment circuit receives differential amplification
The control signal 5 of device output and the pulse signal of leggy pulse module output, to the pulse signal rising edge and trailing edge
The time difference for going out current moment is adjusted, and the pulse signal after adjustment is exported to buffer circuit and the 3rd wave filter simultaneously,
3rd wave filter pulse signals are integrated computing, the common-mode voltage of pulse signal are extracted, by the common-mode voltage of pulse signal
Export to difference amplifier；The common-mode voltage and target voltage are carried out seeking difference operation by difference difference amplifier, will seek poor fortune
Calculation result is exported as control signal 5 gives edge adjustment circuit；After the pulse signal that buffer circuit is received after adjustment enters row buffering
Output clock signal is obtained to export to outside multipath A/D converter；When pulse signal rising edge is arrived down in edge adjustment circuit
Drop along go out time difference that the time difference of current moment and the trailing edge go out current moment to next rising edge it is equal when, edge is adjusted
Circuit completes adjustment process, and the dutycycle of pulse signal is constant 50%, and tool is exported after entering row buffering eventually through buffer circuit
There is the clock signal of 50% constant duty ratio.
In the above-mentioned sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, when integral operation result
When equal with target voltage, edge adjustment no longer changes, and has 50% constant duty ratio eventually through buffer circuit output
Clock signal.
Compared with the prior art, the invention has the advantages that：
（1）, a kind of sampling clock for the time-interleaved analog-digital converter of multichannel proposed by the present invention produce circuit, no
Depend on input reference signal, it is possible to achieve the elimination sampling clock error between multichannel, do not interfere with analog-digital converter
Normal work；
（2）, a kind of sampling clock for the time-interleaved analog-digital converter of multichannel proposed by the present invention produce circuit, no
The first technology needs to introduce global sampling clock switch and have impact on the precision for calibrating for error in being same as background technology, the present invention
Produce the clock signal of equiphase difference step by step by the way of phase dichotomy, and the clock signal poor to adjacent phase carries out school
Standard, can be completely eliminated sampling clock error；
（3）, a kind of sampling clock for the time-interleaved analog-digital converter of multichannel proposed by the present invention produce circuit, no
Second technology extracts sampling clock error using the output of converter in being same as background technology, it is not necessary to complicated wave filter
Group, while the sampling clock error of interchannel can be extracted accurately, the error of interchannel is eliminated when sampling clock is generated, and is reduced
The cost of hardware, reduces cost, while improve the precision of calibration；
（4）, a kind of sampling clock for the time-interleaved analog-digital converter of multichannel proposed by the present invention produce circuit, no
The third technology generates the sampled clock signal of equiphase difference while calibrated channel using delay-locked loop in being same as background technology
Between error method, it is not necessary to by input clock and by the feedback clock of clock distributing network enter line period align, thus
In the absence of compromise in speed and precision, the rigors to interchannel sampling clock error in high-speed applications can be met；
（5）, sampling clock of the present invention produce circuit in the case of the working condition for not changing high-speed AD converter, it is right
The error of multi-channel sampling clock is calibrated；The circuit can carry out structure expansion, enable to the work of analog-digital converter
Pattern is more flexible, it is possible to achieve the switching of different channel selecting down-sampling clock generations, is produced successively by the way of dichotomy
It is raw that there is equiphase clock signal, the calibration of inter-channel phase is realized without the need for complicated filter construction, make modulus
Converter can take into account the precision of sampling clock error calibration in the case of high speed operation.
Brief description of the drawings
Fig. 1 is the schematic diagram of global sampling clock technology；
Fig. 2 is the schematic diagram of clock mismatch compensation technique；
Fig. 3 is the schematic diagram of delay locked loop technique；
Fig. 4 is the structural representation that sampling clock of the present invention produces circuit；
Fig. 5 is the structure chart of two phase clock module of the present invention；
Fig. 6 is a kind of circuit theory diagrams of two phase clock module of the present invention；
Fig. 7 is the structural representation of leggy pulse module of the present invention；
Fig. 8 is the structural representation of multiphase clock generation unit in leggy pulse module of the present invention；
Fig. 9 is the bilateral circuit theory diagrams along phase discriminator in leggy pulse module of the present invention；
Figure 10 is the structural representation of duty ratio recovery circuit of the present invention；
Figure 11 is the circuit theory diagrams of duty ratio recovery circuit of the present invention；
Figure 12 is the timing diagram of duty ratio recovery circuit work of the present invention.
Specific embodiment
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
The structural representation that sampling clock of the present invention produces circuit is illustrated in figure 4, as seen from the figure sampling clock of the present invention
Circuit is produced to be made up of multiphase clock generation module 400, duty ratio recovery circuit 410, channel selecting module 420.It is wherein many
Multi-phase clock signal needed for the generation multichannel digital analog converter of phase clock generation module 400, while to multiphase clock
The phase error of signal is compensated, it is ensured that the accuracy of the sampling clock of digital analog converter interchannel.Duty ratio recovery circuit
410 multiphase clocks for being used for producing multiphase clock generation module carry out edge synchronization behaviour with input global clock signal
Make, the pulse signal that will be received from leggy pulse module carries out dutycycle recovery, the multi-phase clock signal of its output is made
It is the sampled clock signal of outside multipath A/D converter sampling hold circuit.Channel selecting module 420 receives outside serial ports
（SPI）The control code of write-in（Control signal 1）, according to the inner passage number that the control signal judges to need, and control inside
Passage is switched on and off, while leggy pulse module inside multiphase clock is selected according to the control signal 1, to realize
The generation of different channel selecting down-sampling clock ground.
Multiphase clock generation module 400 is made up of two phase clock module 401 and leggy pulse module 402.Wherein two
Phase clock module 401 by the global clock signal of outside input carry out it is anti-phase after obtain anti-phase global clock signal, during to the overall situation
Clock signal and anti-phase global clock signal carry out phase difference calibration, and by the global clock signal and anti-phase global clock after calibration
Signal output gives leggy pulse module.The control signal 2 and two of the receiving channel selecting module of leggy pulse module 402 output
Global clock signal and anti-phase global clock signal after the calibration of phase clock module output, by the global clock signal after calibration
Pass through internal several multiphase clock generation units with inverting clock signal carries out the partite transport of phase two calculation step by step respectively, and respectively
Phase difference calibration is carried out to two results that the partite transport of phase two is calculated, a series of pulse signal of equiphase differences is obtained, pulse is believed
Number export to duty ratio recovery circuit, have between leggy pulse signal is ensured in the case of not introducing labyrinth equal
Phase difference.
The structure chart of two phase clock module of the present invention is illustrated in figure 5, two phase clock module 401 includes unilateral as seen from the figure
Along phase discriminator 501, the first wave filter 502, difference amplifier 503 and controllable time delay line 504, wherein unilateral connect along phase discriminator 501
The anti-phase global clock signal of global clock signal and controllable time delay the line output of outside input is received, phase demodulation operation is carried out, obtained
Two groups of square-wave signals, export to the first wave filter 502.Specially：The unilateral rising that input signal is mainly realized along phase discriminator 501
The phase bit comparison on edge, the i.e. time to the rising edge of input signal are compared, and output obtains one group of square-wave signal, one of them
The moment that the rising edge that the width of the high level of square-wave signal 505 has reacted input clock signal occurs is to exporting clock signal
The time width at the moment that rising edge occurs, the width of the high level of another square-wave signal 506 has reacted output clock signal
Rising edge occur moment to input clock signal next cycle rising edge appearance moment time width.This group
Square-wave signal is input in the first wave filter 502.
First wave filter 502 receives two groups of square-wave signals, extracts DC component, and two groups of DC components are exported to difference
Amplifier 503.Two groups of DC component signals of difference amplifier 503 pair seek difference operation, and difference operation result will be asked to believe as control
Numbers 3 are input to controllable time delay line 504.Controllable time delay line 504 receives global clock signal and the amplifier output of outside input
Control signal 3, adjust global clock signal phase obtain reverse global clock signal, when reverse global clock phase with it is complete
When the phase of office clock signal differs 180 °, phase alignment is completed, by global clock signal and reverse global clock after calibration
Signal output is to leggy pulse module 402, while the reverse global clock signal output after by calibration is to unilateral along phase discriminator
501。
Because output clock signal is the time delay version of input clock signal（Phase is essentially consistent with time delay
's）, can be described by following relation：The cycle of input clock signal is T, the moment that first rising edge occurs
It is t0, then the moment for exporting first rising edge appearance of clock is t1, note t1=t0+ Δs t1（Δt1>0）, then first square wave letter
Number high level width Delta t1, then the moment that second rising edge of input clock signal occurs is t0+T, remembers t0+T=t1+ Δ t2,
Then second high level width Delta t2 of square-wave signal, as Δ t1=Δ t2, completes time delay adjustment process, then have t1=t0+T/
2, the rising edge that analysis sets input clock from phase is 0 ° of phase, then next rising edge is 360 ° of phases, output clock
Rising edge is 180 ° of phases, it may also be said to respectively obtained same phase by two phase clock module（0 ° of phase）With it is anti-phase（180 ° of phases
Position）Clock signal.When due to influence of noise causes that above-mentioned equation is invalid when, then circuit to the error will calibrate straight
To error concealment.
A kind of circuit theory diagrams of two phase clock module of the present invention are illustrated in figure 6, it is as seen from the figure, unilateral along phase discriminator
600 are made up of 6 metal-oxide-semiconductors, wherein M1, M2 for input to pipe, M3~M6 constitute a cross coupling inverter, it be one just
Feedback arrangement, can be rapidly completed input signal phase demodulation.First wave filter 610 is integrated extraction direct current point to identified result
Amount, as the input of difference difference amplifier 620, difference difference amplifier 620 is compared to the two DC quantities, will
Residual quantity is exported in controllable time delay line 640, and it is made up of a current control phase inverter, can be to charging current and discharge current
It is controlled, so as to the time that the edge for realizing control input clock signal occurs, i.e. the phase to clock signal is modulated,
Finally when the phase of input and output clock signal is same phase（0 ° of phase）With it is anti-phase（180 ° of phases）Relation when, wave filter
The DC quantity of 610 outputs is identical, and the residual quantity of difference difference amplifier 630 is output as 0, then the discharge and recharge electricity of controllable time delay line 640
Stream is equal, and when phase difference relation changes, the module can be calibrated to phase error, until phase difference returns to dynamic
Poised state.When phase difference is more than 180 °, there is residual quantity in difference amplifier, obtain control signal adjustment controllable time delay line 630
Electric current, and charging current is more than discharge current, then export the moment that the trailing edge of clock signal occurs and postpone backward, and rises
Can be advanced along the moment for occurring, it is final to reduce phase difference until realizing dynamic equilibrium equal to 180 °；Conversely, when phase difference is less than
At 180 °, there is residual quantity in difference amplifier, obtain the electric current of control signal adjustment controllable time delay line 630, and charging current is less than
Discharge current, then the moment for exporting the trailing edge appearance of clock signal can be advanced, and the moment that rising edge occurs can postpone backward,
It is final to reduce phase difference until realizing dynamic equilibrium equal to 180 °.
The structural representation of leggy pulse module of the present invention is illustrated in figure 7, as seen from the figure leggy pulse module 402
By multistage there is mutually isostructural multiphase clock generation unit to constitute, for producing multichannel to adopt the sampling clock institute for protecting circuit
The pulse signal for needing, with being incremented by for series, the pulse number of generation is exponentially incremented by.If one is total M grades, M grades
Output produces 2（M）It is individual poor with equiphase（For rising edge）Pulse signal, the first order 700, second level in such as Fig. 7
710…….Every grade of multiphase clock generation unit includes pulse-generating circuit and several phase calibration circuitries, wherein：Pulse
Produce the global clock letter after the control signal 2 of circuit receiving channel selecting module output and the calibration of two phase clock module output
Number and anti-phase global clock signal, the quantity of internal multiphase clock generation unit is selected according to control signal 2, by global clock
Signal and anti-phase global clock signal obtain pulse signal after carrying out phase operation, and phase alignment electricity is given by the output of pulse signal
Road；The pulse signal is entered the partite transport of line phase two and calculated by several phase calibration circuitries respectively, and the partite transport of phase two is calculated respectively
Two results carry out phase difference calibration, obtain a series of pulse signal of equiphase differences, and the pulse signal of equiphase difference is defeated
Go out to duty ratio recovery circuit.
If required series M=2, in addition to two phase clock module works, there is one-level in leggy pulse module（Two groups）It is many
Phase clock generation unit is worked, and pulse-generating circuit 701 is received with phase and inverting clock signal, produces two pulse signals,
It is respectively that pulse signal P1 and pulse signal P2, P1 high level width are moment for occurring of in-phase clock rising edge to inversion clock
Rising edge goes out the time width of current moment, and P2 high level width goes out current moment to in-phase clock rising edge for inversion clock rising edge
Go out the time width of current moment, then into calibration delay cell 702 in, the pulse signal of input is carried out into delay process
Two pulse signals are obtained simultaneously, is respectively the pulse signal of former pulse signal and time delay version, the time that its rising edge occurs
It is the half of former pulse signal rising edge to the time width of trailing edge, from the point of view of in phase, the phase of former pulse signal is 0 °,
Then the phase of trailing edge is 180 °, and the time that the rising edge of the pulse signal of time delay version occurs is then 90 ° from the point of view of in phase,
Similarly, input inversion clock signal exports the pulse signal of former pulse signal and time delay version, and the phase of former pulse signal is
180 °, then the phase of trailing edge is 180 °, and time delay version pulse signal is 270 °, defeated altogether by first order leggy generation unit
Go out 4 pulse signals of equiphase difference, phase is respectively 0 °, 90 °, 180 ° and 270 °.
If required series M=3, in addition to two phase clock module works, there is two-stage in leggy pulse module（Six groups）It is many
Phase clock generation unit works, the pulse signal input of 4 equiphases difference that first order multiphase clock generation unit is obtained
To in second level leggy generation unit 710, after being input to second level multiphase clock generation unit, four group pulses are produced respectively
Signal, be respectively（P1, P3）、（P3, P2）、（P2, P4）With（P4, P1）, corresponding phase relation is（0 °, 90 °）、（90 °,
180°）、（180 °, 270 °）With（270 °, 360 °）, four group pulse high level width for the rising edge of input pulse signal occur when
Between difference width.These pulses by obtaining the pulse signal of former pulse signal and time delay after correcting time delay unit 712, from phase
For upper, four pulse signals of input are respectively 0 °, 90 °, 180 ° and 270 °, then export the phase point of the pulse signal of time delay
Not Wei 45 °, 135 °, 225 ° and 315 °, the pulse signals of 8 equiphases difference are obtained.Produced by controlling the leggy of more stages
The working condition of raw unit, then can obtain the pulse signal of more equiphase differences.
It is illustrated in figure 8 the structural representation of multiphase clock generation unit in leggy pulse module of the present invention, multiphase
Bit clock generation unit is made up of pulse-generating circuit 800 and phase calibration circuitry 810.Pulse-generating circuit 800 is by a letter
Single synchronizer 801 and phase inverter are constituted, and input signal CLK1 and CLK2 are input pulse signal, and the rising edge of CLK2 is lagged behind
CLK1, by obtaining required pulse signal after synchronizer 801 and phase inverter, its high level width is upper for input pulse signal
Rise the time difference on edge.
Phase calibration circuitry 810 realized by a delay-locked loop, including bilateral along phase discriminator 811, charge pump 812,
Two wave filters 813, delay line 814, wherein bilateral receive pulse signal and the time delay that pulse-generating circuit is exported along phase-sensitive detector 811
The pulse signal of line output, and phase demodulation operation is carried out to two pulse signals, two groups of square-wave signals are obtained, export to charge pump.
It is bilateral simultaneously to be differentiated that it can use Fig. 9 institutes with the phase of pulse signals rising edge and trailing edge along phase discriminator 811
The circuit realiration for showing（Fig. 9 is the bilateral circuit theory diagrams along phase discriminator in leggy pulse module of the present invention）；Itself and above-mentioned arteries and veins
Punching produces the implementation of circuit to be similar to, and input signal CLK1 and CLK2 are input pulse signal, and the rising edge of CLK2 is lagged behind
CLK1, export pulse P1 and P2 high level width then reacted CLK1 rising edges respectively to the time difference of CLK2 rising edges and
Time difference of the CLK2 rising edges to CLK1 trailing edges.It should be noted that the matching except ensureing synchronizer unit 901 and 911
In addition, also to cause that phase inverter 902 and transmission gate 913 will keep strict conformance on gate delay.
Charge pump 812 receives two groups of square-wave signals, and the output voltage of charge pump 812 is adjusted by square-wave signal, and exports tune
Voltage signal after whole gives the second wave filter 813；Voltage signal after the adjustment of second 813 pairs, wave filter is filtered, and extracts straight
Flow component is input to delay line 814 as control signal 4；Delay line 814 receive pulse-generating circuit output pulse signal and
The control signal 4 of the second wave filter output, enters the pulse signal calculation of the partite transport of line phase two and obtains two pulse signals, works as institute
State two phase differences of pulse signal（The time difference that i.e. rising edge occurs）For input pulse signal rising edge to trailing edge when
Between difference half when, complete phase alignment, and by the pulse signal after calibration simultaneously export to bilateral along phase discriminator 811 and next
The pulse-generating circuit of level multiphase clock generation unit.
The pulse signal of multiple equiphases difference of generation is smaller due to width, can be due to directly as sampled clock signal
It is switched fast and reduces sampling precision, the present invention is reverted to 50% duty pulse signal using duty ratio recovery circuit
The clock signal of ratio, its structure is as shown in Figure 10（Figure 10 is the structural representation of duty ratio recovery circuit of the present invention）, dutycycle
Restoring circuit 1000 includes edge adjustment circuit 1001, buffer circuit 1002, the 3rd wave filter 1003 and difference amplifier 1004,
Wherein edge adjustment circuit 1001 receives the control signal 5 of the output of difference amplifier 1004 and the arteries and veins of leggy pulse module output
Signal is rushed, going out the time difference of current moment to the pulse signal rising edge and trailing edge is adjusted, and by the pulse after adjustment
Signal is exported simultaneously gives the wave filter 1003 of buffer circuit 1002 and the 3rd, and the pulse signals of the 3rd wave filter 1003 are integrated fortune
Calculate, extract the common-mode voltage of pulse signal, the common-mode voltage of pulse signal is exported to difference amplifier 1004；Difference difference is put
The common-mode voltage and target voltage are carried out seeking difference operation by big device 1004, and difference operation result will be asked to be exported as control signal 5
To edge adjustment circuit 1001；The pulse signal that buffer circuit 1002 is received after adjustment obtains exporting clock signal after entering row buffering
Export to outside multipath A/D converter.When pulse signal rising edge goes out current moment to trailing edge in edge adjustment circuit
Between difference it is equal with the time difference that the trailing edge goes out current moment to next rising edge when（I.e. when common-mode voltage is equal with target voltage
When）, edge adjustment circuit completion adjustment process, the dutycycle of pulse signal is constant 50%, eventually through buffer circuit 1002
Enter clock signal of the output with 50% constant duty ratio after row buffering.
It is as shown in figure 11 the circuit theory diagrams of duty ratio recovery circuit of the present invention, Figure 11 is the one of duty ratio recovery circuit
Plant circuit implementations.Edge adjustment circuit 1100 is made up of a current adjustment unit, to charging current and can be put respectively
Electric current is controlled.Wave filter 1120 can use simple RC circuit realirations.And difference difference amplifier can use a letter
Single realizations of the difference Cascode with common-mode feedback, the voltage of Vmid is typically set to the half of working power voltage.Tool
Body running sequential referring to Figure 12 explanation（Figure 12 is the timing diagram of duty ratio recovery circuit work of the present invention）.When the common mode extracted
Component is more than Vmid, illustrates to export the dutycycle of pulse more than 50%, and electric capacity C3 charges, electric capacity C4 electric discharges, then edge adjustment circuit
1100 discharge currents are more than charging current, then the time for exporting the appearance of pulse falling edge can be advanced, and dutycycle can then be reduced；Instead
It, when the common mode component for extracting is less than Vmid, illustrates to export the dutycycle of pulse less than 50%, and electric capacity C3 electric discharges, electric capacity C4 fills
Electricity, then less than charging current, then the time for exporting the rising edge appearance of pulse can be advanced for the discharge current of edge adjustment circuit 1100,
Dutycycle can then increase, and finally, when the dutycycle for exporting pulse is equal to 50%, charging and discharging currents are constant, so that dutycycle is not yet
Change again.
The above, optimal specific embodiment only of the invention, but protection scope of the present invention is not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can be readily occurred in,
Should all be included within the scope of the present invention.
The content not being described in detail in description of the invention belongs to the known technology of professional and technical personnel in the field.
Claims (6)
1. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel produces circuit, it is characterised in that：Including multiphase
Bit clock generation module, duty ratio recovery circuit and channel selecting module, when the multiphase clock generation module includes two-phase
Clock module and leggy pulse module, wherein：
Two phase clock module：By the global clock signal of outside input carry out it is anti-phase after obtain anti-phase global clock signal, to institute
State global clock signal and anti-phase global clock signal carries out phase difference calibration, and by the global clock signal after calibration and anti-phase
Global clock signal output gives leggy pulse module；
Leggy pulse module：After the control signal 2 of receiving channel selecting module output and the calibration of two phase clock module output
Global clock signal and anti-phase global clock signal, by the global clock signal after the calibration and anti-phase global clock signal
Enter the partite transport of line phase two respectively by internal several multiphase clock generation units to calculate, and two for calculating the partite transport of phase two respectively
Individual result carries out phase difference calibration, a series of pulse signal of equiphase differences is obtained, by the output of pulse signal to dutycycle
Restoring circuit；
Duty ratio recovery circuit：The pulse signal received from leggy pulse module is carried out into dutycycle recovery, and exports sampling
Clock signal gives outside multipath A/D converter；
Channel selecting module：The control signal 1 of outside serial ports write-in is received, according to the inside that the control signal 1 judges to need
Port number, and being switched on and off for inner passage is controlled, while being selected inside leggy pulse module according to the control signal 1
The quantity of multiphase clock generation unit, and selection result is exported as control signal 2 give leggy pulse module.
2. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel according to claim 1 produces circuit,
It is characterized in that：The two phase clock module includes unilateral along phase discriminator, the first wave filter, difference amplifier and controllable time delay
Line, wherein the anti-phase global clock that the unilateral global clock signal and controllable time delay line for receiving outside input along phase discriminator is exported is believed
Number, phase demodulation operation is carried out, two groups of square-wave signals are obtained, export to the first wave filter；First wave filter receives the two prescriptions ripple
Signal, extracts DC component, and two groups of DC components are exported to difference amplifier；Difference amplifier is believed two groups of DC components
Number difference operation is sought, difference operation result will be asked to be input to controllable time delay line as control signal 3, controllable time delay line receives outside defeated
The control signal 3 of global clock signal and the amplifier output for entering, when the phase for adjusting global clock signal obtains anti-phase global
Clock signal, when the phase of anti-phase global clock signal differs 180 ° with the phase of global clock signal, completes phase alignment, will
Global clock signal and anti-phase global clock signal output after calibration give leggy pulse module, while anti-phase after by calibration
Global clock signal output is to unilateral along phase discriminator.
3. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel according to claim 1 produces circuit,
It is characterized in that：The leggy pulse module by multistage there is mutually isostructural multiphase clock generation unit to constitute, every grade
Multiphase clock generation unit includes pulse-generating circuit and several phase calibration circuitries, wherein：Pulse-generating circuit is received
Global clock signal and the anti-phase overall situation after the control signal 2 of channel selecting module output and the calibration of two phase clock module output
Clock signal, the quantity of internal multiphase clock generation unit is selected according to the control signal 2, by global clock signal and instead
Phase global clock signal obtains pulse signal after carrying out phase operation, by the output of pulse signal to phase calibration circuitry；If
The pulse signal is entered the partite transport of line phase two and calculated by dry phase calibration circuitry respectively, and two for calculating the partite transport of phase two respectively
Result carries out phase difference calibration, obtains a series of pulse signal of equiphase differences, and the output of pulse signal is extensive to dutycycle
Compound circuit.
4. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel according to claim 3 produces circuit,
It is characterized in that：Described each phase calibration circuitry include it is bilateral along phase discriminator, charge pump, the second wave filter and delay line, its
In it is bilateral receive the pulse signal that pulse-generating circuit exports and the pulse signal that delay line is exported along phase-sensitive detector, and to two arteries and veins
Rushing signal carries out phase demodulation operation, obtains two groups of square-wave signals, exports to charge pump；Charge pump receives two groups of square-wave signals,
The output voltage of charge pump is adjusted by square-wave signal, and voltage signal after output adjustment gives the second wave filter；Second wave filter
Voltage signal after adjustment is filtered, DC component is extracted and is input to delay line as control signal 4；Delay line receives arteries and veins
Punching produces the control signal 4 of pulse signal and the second wave filter output of circuit output, and the pulse signal is entered into line phase two
Partite transport is calculated and obtains two pulse signals, when the pulse signal rising edge that the phase difference of described two pulse signals is input to decline
Along the time difference half when, complete phase alignment, and by the pulse signal after calibration simultaneously export to it is bilateral along phase discriminator and under
The pulse-generating circuit of one-level multiphase clock generation unit.
5. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel according to claim 1 produces circuit,
It is characterized in that：The duty ratio recovery circuit includes edge adjustment circuit, buffer circuit, the 3rd wave filter and differential amplification
Device, wherein edge adjustment circuit receive the control signal 5 of difference amplifier output and the pulse letter of leggy pulse module output
Number, going out the time difference of current moment to the pulse signal rising edge and trailing edge is adjusted, and by the pulse signal after adjustment
Export to buffer circuit and the 3rd wave filter simultaneously, the 3rd wave filter pulse signals are integrated computing, extract pulse signal
Common-mode voltage, the common-mode voltage of pulse signal is exported to difference amplifier；Difference difference amplifier is by the common-mode voltage
Carry out seeking difference operation with target voltage, difference operation result will be asked to be exported as control signal 5 and give edge adjustment circuit；Buffer circuit
Receive the pulse signal after adjustment and enter after row buffering to obtain output clock signal and export to outside multipath A/D converter；Work as side
Pulse signal rising edge goes out time difference and the trailing edge to next rising edge of current moment to trailing edge along adjustment circuit
Go out current moment time difference it is equal when, edge adjustment circuit complete adjustment process, the dutycycle of pulse signal is constant 50%,
The clock signal with 50% constant duty ratio is exported after entering row buffering eventually through buffer circuit.
6. a kind of sampling clock for the time-interleaved analog-digital converter of multichannel according to claim 5 produces circuit,
It is characterized in that：When integral operation result is equal with target voltage, edge adjustment no longer changes, eventually through buffering electricity
Clock signal of the road output with 50% constant duty ratio.
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