CN103944461A - Single-FPGA-realized multi-asynchronous-motor control system and control method - Google Patents
Single-FPGA-realized multi-asynchronous-motor control system and control method Download PDFInfo
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Abstract
The invention discloses a control system and a control method for a plurality of asynchronous motors realized by a single FPGA, wherein an IP core outputs PWM driving pulse, an optical coupling isolation unit receives the PWM driving signal provided by the IP core and outputs the PWM driving signal to an inversion unit, the inversion unit receives the PWM driving pulse isolated by the optical coupling isolation unit and drives a motor to operate and generate a voltage signal, the voltage signal generated by the inversion unit of a voltage and current detection unit is converted into a digital signal and then is input into the IP core after being isolated by a serial port, 6 paths of PWM pulse signals of each motor are obtained in the IP core through an SVPWM algorithm and a VVVF algorithm, by the mode, the invention can adopt a single FPGA chip to realize the control of a plurality of motors with extremely few hardware resources, meanwhile, a strong current and weak current isolation measure is adopted, so that the system is not interfered by a strong current part, and the reliability of the system is improved.
Description
Technical field
The present invention relates to a kind of Motor Control Field, multiple asynchronous motors control system and control method that particularly a kind of single FPGA is realized.
Background technology
Along with the development of present science and technology, each art is also more and more advanced, and in many industrial application, in the main equipment such as Digit Control Machine Tool, Computerized flat knitting machine, generally all need multiple asynchronous motors to drive different institutions to carry out collaborative work, this just relates to the Collaborative Control problem of multiple asynchronous motors simultaneously.General control mode all adopts the mode of a motor of a microprocessor control at present, and then adopt a total microprocessor, by communication interface, as the interface such as RS485 or CAN, coordinate to control each microprocessor, thereby realize the control of multiple asynchronous motors.Its major defect is: adopt this control mode, need a master microprocessor and the sub-microprocessor of polylith, and need to solve the Communication between master microprocessor and each sub-microprocessor, therefore need the cost on hardware and need to write corresponding bitcom, cause system to realize cost higher, the resource of looking together module needs is more, and control method is comparatively complicated, causes the speed of computing low.
Summary of the invention
The technical problem that the present invention mainly solves is to provide multiple asynchronous motors control system and the control method that a kind of single FPGA is realized, realized the control that realizes multiple asynchronous motors with few hardware resource by a fpga chip, and the light current of whole system and forceful electric power can be realized electrical isolation, ensure that control system can reliably working, be not subject to the impact of strong power part circuit.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: the multiple asynchronous motors control system that provides a kind of single FPGA to realize, comprise: FPGA IP kernel and multiple electric motors, be all in series with the electric current and voltage detecting unit of light-coupled isolation unit, inversion unit and multi-path serial in the path of described IP kernel and every described motor;
Described FPGA IP kernel, output PWM driving pulse, every corresponding six road PWM driving pulses of motor;
Described light-coupled isolation unit, the PWM that receiving described FPGA IP kernel provides drives signal, forceful electric power and light current is isolated simultaneously, drives signal to export to described inversion unit PWM;
Described inversion unit, receives by the PWM driving pulse after isolation in described light-coupled isolation unit, drive motors running, and produce a voltage signal;
Described electric current and voltage detecting unit, converts the voltage signal producing in described inversion unit to digital signal, then after isolating by serial ports, inputs described FPGA IP kernel.
In a preferred embodiment of the present invention, described FPGA IP kernel comprises separate unit motor SVPWM algoritic module, and described separate unit motor SVPWM algoritic module comprises:
According to given frequency, traffic direction with whether turn round, obtain the position alpha of space vector and the rotating vector generation module of modulation ratio m;
Receive position alpha and the modulation ratio m data of space vector, according to the predetermined formula computer memory vector computing module of action time;
Obtain the PWM block of state of 6 road pwm pulses action time according to space vector;
6 road pwm pulses are converted to the dead band module of 6 road pwm pulses of last three-phase inversion unit;
Described rotating vector generation module, computing module, PWM block of state are carried out to the timing management module of timing management.
In a preferred embodiment of the present invention, described computing module comprises sine and cosine module and multiplier module, described sine and cosine module and described multiplier module respectively with described timing management module, receive the clock signal of described timing management module assignment.
The present invention also provides a kind of control method of multiple asynchronous motors control system of single FPGA realization, and concrete steps are as follows:
(100) whether distribute corresponding command signal to every motor will controlling, described command signal comprises: frequency, direction of rotation and move;
(200) by the VVVF control algolithm module of three command signal input separate unit motors of n platform motor, adopt SVPWM algorithm to obtain pwm pulse the latch output of n platform motor, and got off in the position at the space vector place of n platform motor and sector latch, complete the control of n platform motor;
(300) three command signals of n=n+1 platform motor are sent in the VVVF control algolithm module of above-mentioned separate unit motor to repeating step (200).
In a preferred embodiment of the present invention, in described step (200), the step of SVPWM algorithm is as follows:
(210), first according to given frequency, traffic direction with whether turn round, obtain the sector sector at position alpha, modulation ratio m and the space vector place of space vector;
(220), calculate α angle corresponding sine and cosine value sin α and cos α by the position alpha of above-mentioned space vector;
(230), calculate two of space voltage by resolution of vectors again and decompose T1 action time, the T2 of vector and T0 action time of zero vector;
(240), then by relatively obtaining 3 road pwm pulse signal cycle T C1, TC2, TC3;
(250), then by above-mentioned 3 road pwm pulse signal cycle negates, obtain 6 road pwm pulse signals.
In a preferred embodiment of the present invention, in step (230), two of described space voltage T1 action time, T2 that decompose vectors and zero vector action time T0 computing formula be respectively:
（1）
（2）
（3）
Wherein, Tpwm is the cycle of a pwm pulse signal;
In a preferred embodiment of the present invention, in step (240), the table of comparisons in described 3 road pwm pulse signal cycles is as follows:
Wherein, the computing formula of Tcm1, Tcm2, Tcm3 is as follows:
（4）
(Sector=1/3/5) or
(Sector=2/4/6) （5）
（6）
The invention has the beneficial effects as follows:
1, single FPGA of the present invention is realized multiple asynchronous motors control system and control method, adopt monolithic fpga chip, realize spatial vector pulse width modulation algorithm and the VVVF control algolithm of multiple asynchronous motors, thereby reached the control that adopts few hardware resource to realize multiple asynchronous motors.
2, single FPGA of the present invention is realized multiple asynchronous motors control system and control method, the control thought that adopts time-sharing multiplex to combine with parallel and serial, the control algolithm of the multiple electric motors of realizing, improve the renewal speed of PWM, and the hardware resource needing is few, can utilize the FPGA that scale is less to realize.
3, whole system has adopted the measure of forceful electric power and light current isolation, and the system that ensured is not subject to the interference of strong power part, has improved the reliability of system.
Brief description of the drawings
Fig. 1 is total system frame diagram of the present invention;
Fig. 2 is the inversion unit schematic diagram in the present invention;
Fig. 3 is light-coupled isolation unit schematic diagram in the present invention;
Fig. 4 is electric current and voltage detecting unit in the present invention;
Fig. 5 is the control flow chart of multiple asynchronous motors in the present invention;
Fig. 6 is that in inverter of the present invention, 6 effective switches decompose polar plot;
Fig. 7 is motor of the present invention at the space vector isoboles of voltage sometime;
Fig. 8 is pwm pulse signal generation method figure of the present invention;
Fig. 9 is that the IP kernel of separate unit motor in the present invention is realized block diagram;
Figure 10 is spatial vector pulse width modulation algorithm SVPWM algoritic module specific implementation flow chart of the present invention;
Figure 11 is the multiplier module interface in the present invention;
Figure 12 is the multiplier module realization flow figure in the present invention;
Figure 13 is the sine and cosine module interface in the present invention;
Figure 14 is the sine and cosine module realization flow figure in the present invention.
Embodiment
The present invention is described in detail, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.
The multiple asynchronous motors control system that a kind of single FPGA of the present invention is realized, entire system block diagram is as Fig. 1, figure comprises: IP kernel and motor 1, motor 2 ... motor n, its IP kernel and described motor 1, motor 2 ... in the direct each path of motor n, correspondence is in series with light-coupled isolation unit 1, light-coupled isolation unit 2 ... light-coupled isolation unit n and inversion unit 1 inversion unit 2 ... inversion unit n, and there is an electric current and voltage detecting unit in each path serial, described electric current and voltage detecting unit and described IP kernel are isolated by serial ports, obtain motor 1 by the IP kernel in FPGA, motor 2 ... motor n Zhong six road driving pulses, through light-coupled isolation unit 1, light-coupled isolation unit 2 ... after light-coupled isolation unit n, send into inversion unit 1, inversion unit 2 ... inversion unit n, described inversion unit 1, inversion unit 2 ... inversion unit n is all directly by corresponding light-coupled isolation unit 1, light-coupled isolation unit 2 ... driving signal after light-coupled isolation unit n isolation is controlled, and all correspondence produces a voltage signal, in circuit, multi-path serial has electric current and voltage detecting unit simultaneously, described voltage signal enters electric current and voltage detecting unit and carries out digitlization, isolate by serial ports, be input in IP kernel, thereby learn system voltage and current of electric.Whole system has adopted the measure of forceful electric power and light current isolation, and the system that ensured is not subject to the interference of strong power part, has improved the reliability of system.
As shown in Figure 2, for the schematic diagram of Zhong Yi of the present invention road inversion unit, HA in figure, HB, HC and LA, LB, LC is respectively three-phase inverter Liu road pwm pulse signal, described three-phase inverter adopts PS21997 module, this module is by fast diode D1, D2, D3 gives respectively capacitor C 1, C2, C3 charging, realize bootstrapping function, thereby make whole drive circuit only need 1 road 15V Power supply, this unit receives by the PWM driving pulse after isolation in described light-coupled isolation unit, drive motors running, and produce a voltage signal, described inversion unit is also by R1 and C14 capacitance-resistance filter, then signal is sent into the over-current detection pin of PS21997 module, thereby realize the overcurrent protection function of inversion unit.
As shown in Figure 3, for the light-coupled isolation unit in the present invention, Figure 3 shows that the buffer circuit of 1 road pwm pulse, in figure, HA_FPGA is connected with the IP kernel in described fpga chip, the HA pin of HA and described inversion unit is connected, for forceful electric power and the light current of buffer circuit, it is the buffer circuit of pwm pulse.
As shown in Figure 4, for the potential circuit testing circuit in the present invention, in figure, TLC3544 one has the chip of SPI Serial Communication Function, the voltage signal obtaining from inversion unit is carried out digitlization conversion by it, isolate by serial ports, be input in IP kernel, thereby learn system voltage and current of electric, can realize the current sample of 4 asynchronous motors.As needs, control exceedes 4 motors, can select TLC3548 chip, can realize the sampling of 8 tunnel analog quantitys.SPI communication interface is isolated by optocoupler ISO7231, then connects with fpga chip, has realized the strong and weak electric signal isolation of analog signal sampling.
The present invention has also disclosed multiple asynchronous motors control system and the control method that a kind of single FPGA is realized, the present invention adopts fpga chip, the VVVF (variable voltage variable frequency) that realizes multiple asynchronous motors controls, the control of concrete separate unit motor realizes, main frequency modulation and the Regulation Control that adopts space vector modulation (SVPWM) algorithm to realize asynchronous machine three-phase voltage, as shown in Figure 5, for the control flow chart of multiple asynchronous motors, first in the IP kernel of FPGA, distribute corresponding control command resource to every motor will controlling, be respectively frequency f req(16 position), direction of rotation dir(1 position) and whether move run(1 position) three instructions, if control 4 motors, need 4 groups of such orders, next first three command signals of motor 1 are sent into separate unit motor VVVF algoritic module, finally obtain the pwm pulse of motor 1, and latch output, next and position and the sector latch at the space vector place when front motor get off, complete like this control of a motor, next step starts the control of motor 2, in the control of motor 2, only control command need to be sent in the VVVF algoritic module of the separate unit motor identical with motor 1, just can realize the control of motor 2, do not need like this to realize identical VVVF algorithm to every motor, only need 1 VVVF algoritic module just can realize, thereby reached the control that realizes multiple asynchronous motors with less hardware resource.In the present invention, a VVVF algoritic module needs 140 clocks, be 40M crystal oscillator as the present invention adopts chip fpga chip, that is to say, the realization of a VVVF algorithm need to about 3.5us, the switch periods of general asynchronous machine is 10K left and right, it is the cycle of 0.1ms, therefore, because the FPGA implementation algorithm speed of service is fast, in the cycle of 0.1ms, can realize 28 VVVF algorithms nearly, that is to say, adopt control method of the present invention, when nearly can realizing 28 asynchronous motors, control, the control of the hardware resource simultaneously needing and 1 motor is more or less the same.
Shown in Fig. 6, Fig. 7, the instantaneous voltage in arbitrary moment of threephase asynchronous machine can indicate with the vector in a space, as the three-phase voltage of a certain moment motor is respectively u
a, u
b, u
c, space vector can be expressed as:
For three-phase inverter, there are 8 on off states, wherein 6 is effective on off state, can form 6 switching vector selectors of Fig. 6, totally six sectors, the voltage of a certain moment three phase electric machine can be expressed as a vector in Fig. 7, according to weber equilibrium principle, can be the space voltage vector in arbitrary moment the action effect at a switch periods Tpwm, be equivalent to two switching vector selectors that are adjacent and act on respectively T1 and T2 sum, its space vector decomposes isoboles as shown in Figure 7.
As shown in Figure 9, for the present invention is the block diagram of realizing of separate unit motor I P core, first the order of inputting given frequency, traffic direction and whether turning round in first rotating vector generation module in IP kernel, obtain the sector sector at angle [alpha], modulation ratio m and the space vector place of space vector, then calculate sine and cosine value corresponding to α angle by sine and cosine module, calculate two of space voltage by resolution of vectors again and decompose T1 action time, the T2 of vector and T0 action time of zero vector, its concrete formula is:
（1）
（2）
（3）
Wherein, Tpwm is the cycle of a pwm pulse signal;
Then be delivered to comparison module again and obtain 3 road pwm pulse signal cycle T C1, TC2, TC3, the table of comparisons of described 3 road pwm pulse signal cycle T C1, TC2, TC3 is specific as follows:
Wherein, the computing formula of Tcm1, Tcm2, Tcm3 is as follows:
（4）
(Sector=1/3/5) or
(Sector=2/4/6) （5）
（6）
As described in Figure 8, for PWM status signal generation method figure in the present invention, obtain after TC1, TC2, TC3, negate is conveyed into PWM block of state together, generate 6 road pwm pulse signals according to Fig. 8, obtain 6 road pwm pulse signals of last three-phase inversion unit finally by mistake dead band module.In whole process, described rotating vector generation module, computing module and PWM block of state are all connected with timing management module, and this is the process of a serial, for carrying out the timing management of each module.
As shown in figure 10, for spatial vector pulse width modulation algorithm SVPWM algoritic module specific implementation flow chart in the present invention, arrow in figure represents to realize the needed fpga chip clock number of each module, m*Tpwm module in figure and T1 calculate and T2 computing module, three modules adopt same multiplier, carry out the calculating of modulation ratio m and Tpwm at clock 1-20, carry out T1 calculating at clock 77-96, carry out T2 calculating at 97-116, and sinusoidal calculations module and cosine computing module in figure all adopts sine and cosine arithmetic unit, adopt the principle of time-sharing multiplex only to adopt 1 multiplier and sine and cosine arithmetic unit to realize the computing of whole SVPWM algoritic module, can effectively economize on resources, and these two modules are parallel mutually with major cycle, do not take the time of whole circulation, improve the renewal speed of PWM.
As Figure 11, shown in Figure 13, be respectively described multiplier module output interface and described sine and cosine output interface, in figure, Counter is entire system counter, Rmtpwm is the product of modulation ratio m and PWM cycle T pwm, its specific implementation flow chart is respectively as Figure 12, shown in Figure 14, be between 1-20 time at clock number, output valve is Rmtpwm, be between 21-48 time at clock number, output valve is cos(60-α), be between 49-76 time at clock number, output valve is sin α, be between 76-97 time at clock number, output valve is Rmtpwm and cos(60-α) product, be T1, be between 96-117 time at clock number, output valve is the product of Rmtpwm and sin α, be T2.
Be different from prior art, in the present invention, FPGA IP kernel is the system core, be responsible for realizing space vector modulation (SVPWM) and the VVVF control algolithm of multiple electric motors, and because FPGA is generally equipped with more IO mouth, therefore can easily obtain every motor Liu road PWM driving pulse by FPGA.FPAG core is the control centre of whole system, is the key component of whole system.What obtained by FPGA does not have a platform motor Liu road driving pulse, through light-coupled isolation 1 ~ light-coupled isolation N, then delivers to inverter circuit 1-inverter circuit N part, and inverter circuit adopts IPM module to realize, and can directly be controlled by the driving signal after light-coupled isolation.The inspection of current of electric and busbar voltage directly realizes by multi-path serial AD; the result obtaining is by after isolating by serial ports; be sent to fpga chip; in FPGA, realize and have corresponding serial ports read-write capability module; thereby can obtain busbar voltage and the current of electric of system, provide protection inverter circuit for realizing overcurrent-overvoltage etc.Between whole system light current and forceful electric power, all realize electrical isolation, thereby ensured that control system can reliably working, be not subject to the impact of strong power part circuit.
The present invention adopts monolithic fpga chip, realize spatial vector pulse width modulation algorithm and the VVVF control algolithm of multiple asynchronous motors, thereby reach the control that adopts few hardware resource to realize multiple asynchronous motors, the control thought that simultaneously adopts time-sharing multiplex to combine with parallel and serial, the control algolithm of the multiple electric motors of realizing, improved the renewal speed of PWM, and the hardware resource needing is few, can utilizes the FPGA that scale is less to realize; And whole system has adopted the measure of forceful electric power and light current isolation, and the system that ensured is not subject to the interference of strong power part, has improved the reliability of system.
The foregoing is only embodiments of the invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes specification of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (6)
1. the multiple asynchronous motors control system that single FPGA is realized, it is characterized in that: comprising: FPGA IP kernel and multiple electric motors, be all in series with the electric current and voltage detecting unit of light-coupled isolation unit, inversion unit and multi-path serial in the path of described IP kernel and every described motor;
Described FPGA IP kernel, output PWM driving pulse, every corresponding six road PWM driving pulses of motor;
Described light-coupled isolation unit, the PWM that receiving described FPGA IP kernel provides drives signal, forceful electric power and light current is isolated simultaneously, drives signal to export to described inversion unit PWM;
Described inversion unit, receives by the PWM driving pulse after isolation in described light-coupled isolation unit, drive motors running, and produce a voltage signal;
Described electric current and voltage detecting unit, converts the voltage signal producing in described inversion unit to digital signal, then after isolating by serial ports, inputs described FPGA IP kernel.
2. the multiple asynchronous motors control system that single FPGA according to claim 1 is realized, is characterized in that: described FPGA IP kernel comprises separate unit motor SVPWM algoritic module, and described separate unit motor SVPWM algoritic module comprises:
According to given frequency, traffic direction with whether turn round, obtain the position alpha of space vector and the rotating vector generation module of modulation ratio m;
Receive position alpha and the modulation ratio m data of space vector, according to the predetermined formula computer memory vector computing module of action time;
Obtain the PWM block of state of 6 road pwm pulses action time according to space vector;
6 road pwm pulses are converted to the dead band module of 6 road pwm pulses of last three-phase inversion unit;
Described rotating vector generation module, computing module, PWM block of state are carried out to the timing management module of timing management.
3. the multiple asynchronous motors control system that single FPGA according to claim 1 is realized, is characterized in that:
Described computing module comprises a sine and cosine module and a multiplier module, described sine and cosine module and described multiplier module respectively with described timing management module, receive the clock signal of described timing management module assignment.
4. a control method for the multiple asynchronous motors control system that single FPGA is realized, is characterized in that: concrete steps are as follows:
(100) whether distribute corresponding command signal to every motor will controlling, described command signal comprises: frequency, direction of rotation and move;
(200) by the VVVF control algolithm module of three command signal input separate unit motors of n platform motor, adopt SVPWM algorithm to obtain pwm pulse the latch output of n platform motor, and got off in the position at the space vector place of n platform motor and sector latch, complete the control of n platform motor;
(300) three command signals of n=n+1 platform motor are sent in the VVVF control algolithm module of above-mentioned separate unit motor to repeating step (200).
5. the control method of the multiple asynchronous motors control system that single FPGA according to claim 4 is realized, is characterized in that: in described step (200), the step of SVPWM algorithm is as follows:
(210), first according to given frequency, traffic direction with whether turn round, obtain the sector sector at position alpha, modulation ratio m and the space vector place of space vector;
(220), calculate α angle corresponding sine and cosine value sin α and cos α by the position alpha of above-mentioned space vector;
(230), calculate two of space voltage by resolution of vectors again and decompose T1 action time, the T2 of vector and T0 action time of zero vector;
(240), then by relatively obtaining 3 road pwm pulse signal cycle T C1, TC2, TC3;
(250), then by above-mentioned 3 road pwm pulse signal cycle negates, obtain 6 road pwm pulse signals.
6. the control method of the multiple asynchronous motors control system that single FPGA according to claim 5 is realized, it is characterized in that: in step (230), two of described space voltage T1 action time, T2 that decompose vectors and zero vector action time T0 computing formula be respectively:
（1）
（2）
（3）
Wherein, Tpwm is the cycle of a pwm pulse signal;
The control method of the multiple asynchronous motors control system that a kind of single FPGA according to claim 5 is realized, is characterized in that: in step (240), the table of comparisons in described 3 road pwm pulse signal cycles is as follows:
Wherein, the computing formula of Tcm1, Tcm2, Tcm3 is as follows:
（4）
(Sector=1/3/5) or
(Sector=2/4/6) （5）
（6）
。
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106240145A (en) * | 2016-07-29 | 2016-12-21 | 西安电子科技大学 | The polychrome flexible steel roller printing machine automatic voltage regulating system controlled based on monolithic FPGA |
| CN108768220A (en) * | 2018-07-23 | 2018-11-06 | 南京工程学院 | A kind of integrative coordinated control device and method of articulated robot |
| CN111983943A (en) * | 2019-10-25 | 2020-11-24 | 深圳市安达自动化软件有限公司 | Servo motor control method, controller, device, equipment and storage medium thereof |
| CN112506090A (en) * | 2020-10-19 | 2021-03-16 | 中国人民解放军海军工程大学 | Time-sharing multiplexing servo device and method for controlling operation of multiple motors |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101902185A (en) * | 2009-05-28 | 2010-12-01 | 通用汽车环球科技运作公司 | Control method of operating, system and the equipment of two interchanges (AC) motor |
| CN101976999A (en) * | 2010-11-30 | 2011-02-16 | 中国汽车技术研究中心 | Three-leg nine-switch inverter for driving double-alternating current motor |
| CN202085117U (en) * | 2011-06-21 | 2011-12-21 | 杭州电子科技大学 | All-digital AC servo drive for double motors |
| CN102594242A (en) * | 2012-02-10 | 2012-07-18 | 北方工业大学 | Vector control method based on indirect matrix converter multi-machine transmission system |
| CN102651625A (en) * | 2012-04-27 | 2012-08-29 | 浙江吉利汽车研究院有限公司杭州分公司 | Motor control system for hybrid electric vehicle |
| JP2012228155A (en) * | 2011-04-22 | 2012-11-15 | Ricoh Co Ltd | Motor drive device |
| CN102811012A (en) * | 2012-07-20 | 2012-12-05 | 华中科技大学 | Field programmable gate array-based (FPGA-based) multi-axis servo motor current loop control system and control method |
| CN103248284A (en) * | 2013-05-17 | 2013-08-14 | 上海电机学院 | Special driver for linear shaft motor |
-
2014
- 2014-03-26 CN CN201410115541.9A patent/CN103944461B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101902185A (en) * | 2009-05-28 | 2010-12-01 | 通用汽车环球科技运作公司 | Control method of operating, system and the equipment of two interchanges (AC) motor |
| CN101976999A (en) * | 2010-11-30 | 2011-02-16 | 中国汽车技术研究中心 | Three-leg nine-switch inverter for driving double-alternating current motor |
| JP2012228155A (en) * | 2011-04-22 | 2012-11-15 | Ricoh Co Ltd | Motor drive device |
| CN202085117U (en) * | 2011-06-21 | 2011-12-21 | 杭州电子科技大学 | All-digital AC servo drive for double motors |
| CN102594242A (en) * | 2012-02-10 | 2012-07-18 | 北方工业大学 | Vector control method based on indirect matrix converter multi-machine transmission system |
| CN102651625A (en) * | 2012-04-27 | 2012-08-29 | 浙江吉利汽车研究院有限公司杭州分公司 | Motor control system for hybrid electric vehicle |
| CN102811012A (en) * | 2012-07-20 | 2012-12-05 | 华中科技大学 | Field programmable gate array-based (FPGA-based) multi-axis servo motor current loop control system and control method |
| CN103248284A (en) * | 2013-05-17 | 2013-08-14 | 上海电机学院 | Special driver for linear shaft motor |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106240145A (en) * | 2016-07-29 | 2016-12-21 | 西安电子科技大学 | The polychrome flexible steel roller printing machine automatic voltage regulating system controlled based on monolithic FPGA |
| CN106240145B (en) * | 2016-07-29 | 2018-05-25 | 西安电子科技大学 | Polychrome flexible steel roller printing machine automatic voltage regulating system based on monolithic FPGA controls |
| CN108768220A (en) * | 2018-07-23 | 2018-11-06 | 南京工程学院 | A kind of integrative coordinated control device and method of articulated robot |
| CN108768220B (en) * | 2018-07-23 | 2024-04-26 | 南京工程学院 | Multi-joint robot integrated cooperative control device |
| CN111983943A (en) * | 2019-10-25 | 2020-11-24 | 深圳市安达自动化软件有限公司 | Servo motor control method, controller, device, equipment and storage medium thereof |
| CN112506090A (en) * | 2020-10-19 | 2021-03-16 | 中国人民解放军海军工程大学 | Time-sharing multiplexing servo device and method for controlling operation of multiple motors |
| CN112506090B (en) * | 2020-10-19 | 2022-03-29 | 中国人民解放军海军工程大学 | Time-sharing multiplexing servo device and method for controlling operation of multiple motors |
| CN112532142A (en) * | 2020-11-27 | 2021-03-19 | 中电凯杰科技有限公司 | AGV biax steering wheel is based on high resource reuse's of low-cost FPGA control system |
| CN112787549A (en) * | 2020-12-24 | 2021-05-11 | 季华实验室 | STO control circuit of multi-axis driver |
| CN112787549B (en) * | 2020-12-24 | 2022-07-15 | 季华实验室 | STO control circuit of multi-axis driver |
| CN113014152A (en) * | 2021-04-08 | 2021-06-22 | 中国第一汽车股份有限公司 | Dual-motor control system and method |
| CN113014152B (en) * | 2021-04-08 | 2023-06-20 | 中国第一汽车股份有限公司 | Dual-motor control system and method |
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