CN103943669B - A kind of anti-fuse structures and preparation method thereof - Google Patents
A kind of anti-fuse structures and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to a kind of anti-fuse structures and preparation method thereof, methods described includes：Semiconductor substrate；N traps, in the substrate；Polysilicon gate, on the substrate above the N traps；High k dielectric layer, between the polysilicon gate and the substrate；Source and drain doping area, in the N traps of the grid both sides；N-type doping area, in the N traps on the outside of the source and drain doping area.The N-type gate material layers and the N traps are used for reducing the program voltage of the anti-fuse structures in the present invention, while control the leakage of electric current after programming by reducing work function.Use high K polysilicon gates in the present invention, the area of grid in the polysilicon gate is not limited by metal gates Chemical Mechanical Polishing (CMP), and the area of grid accurately adjusted can obtain more suitable program voltage in design.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates to a kind of anti-fuse structures and preparation method thereof.
Background technology
With the continuous development of semiconductor technology, antifuse（Anti-fuse）Technology has attracted many inventors, IC
Designer and the notable concern of manufacturer.Antifuse is the structure that can change to conduction state, or, in other words, antifuse is
Never conduction state changes into the electronic device of conduction state.Equally, binary condition can be in response in electric stress (as programmed
Voltage or program current) high resistance and any of low resistance.Antifuse device can be disposed in storage array, by
This forms generally known One Time Programmable (OTP) memory.
Current antifuse exploitation concentrates on three-dimension film structure and special intermetallic material.This antifuse technology needs
Will in standard CMOS process not available additional processing step, set which prevent antifuse in typical VLSI and ASIC
Application in meter, here, programmability can help to overcome cycle device lifetime constantly shortened and the chip constantly risen to open
The problem of sending out cost.Therefore, industrially obvious need be present to the reliable anti-fuse structures using standard CMOS process.
Antifuse（Anti-fuse）Programmable chip technology provide the stable and conductive path between transistor
Footpath, relative to the fuse of routine（blowing fuses）Molten link method for, antifuse technology is by dividing conductive path
A conducting channel is opened in footpath, and antifuse passes through growth（growing）One conductive channel closes circuit.
Antifuse in the prior art（Anti-fuse）Structure as illustrated in fig. 1 and 2, wherein, the shape on the substrate 101
Into the interlayer structure of metal level 102- dielectric layer 103- metal levels 104, wherein the dielectric layer is amorphous silicon（amorphous
silicon）, the sequencing of grid array is carried out using the antifuse, wherein as shown in figure 1, when in the anti-fuse structures
On when not applying voltage, the middle dielectric layer is in "off" state, and now the dielectric layer is non-conductive, when in the fuse
When applying voltage in structure, the dielectric layer amorphous silicon（amorphous silicon）It is changed into polysilicon
（polysilicon）, in conduction state, the antifuse is in "open" state, as shown in Fig. 2 carrying out antifuse with this
Sequencing.
Although antifuse technology is widely developed and applied in semiconductor technology, in the prior art antifuse
Structure be the element based on polysilicon gate, with the continuous renewal of technology, fuse element of the prior art is simultaneously uncomfortable
For metal gates, therefore, it is necessary to antifuse element of the prior art is improved further.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of anti-fuse structures, including：
Semiconductor substrate；
N traps, in the substrate；
Polysilicon gate, on the substrate above the N traps；
High k dielectric layer, between the polysilicon gate and the substrate；
Source and drain doping area, in the N traps of the grid both sides；
N-type doping area, in the N traps on the outside of the source and drain doping area.
Preferably, during the n-type doping area ground connection, the device has high leakage current, the source after programming
When drain region is grounded, the device has Low dark curient electric current after programming, can be in the antifuse by above two method
Leakage current after two kinds of different sequencing is realized in structure.
Preferably, the anti-fuse structures also include the skew side wall positioned at the grid both sides.
Preferably, it is also formed with coating between the grid and the high k dielectric layer.
Preferably, it is also formed with boundary layer between the high k dielectric layer and the substrate.
Preferably, the grid is n-type doping.
Partly overlapped preferably, the source and drain doping area has with the grid.
Present invention also offers a kind of preparation method of anti-fuse structures, including：
Semiconductor substrate is provided；
N traps are formed over the substrate；
High k dielectric layer, polysilicon layer are formed on the substrate above the N traps, and is patterned to form polysilicon
Grid；
Source and drain doping area is formed in the N traps of the grid both sides；
N-type doping area is formed in the N traps on the outside of the source and drain doping area.
Preferably, the grid is n-type doping.
Preferably, the n-type doping area is formed by the method for LDD ion implantings or source and drain ion implanting.
Preferably, the source-drain area is formed by LDD ion implantings, to ensure that the source-drain area has with the grid
Partly overlap.
Preferably, methods described is additionally included between the grid and the high k dielectric layer the step of forming coating.
Preferably, methods described is additionally included between the high k dielectric layer and the substrate the step of forming boundary layer.
The N-type gate material layers and the N traps are used for reducing the program voltage of the anti-fuse structures in the present invention,
Simultaneously by reduce work function control programming after electric current leakage.High K polysilicon gates, the polycrystalline are used in the present invention
Area of grid in silicon gate is not limited by metal gates Chemical Mechanical Polishing (CMP), the area of grid accurately adjusted,
More suitable program voltage can be obtained during design.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the device of the present invention and principle.In the accompanying drawings,
Fig. 1-2 is in structural representation during off and on state for anti-fuse structures in the prior art；
Fig. 3 is anti-fuse structures schematic diagram in the present invention；
Structural representation when Fig. 4-5 is middle two kinds of different conditions of anti-fuse structures in the present invention；
Fig. 6 is the schematic flow sheet for preparing anti-fuse structures in the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, it is of the present invention anti-to illustrate
Fuse-wires structure and preparation method thereof.Obviously, execution of the invention is not limited to the spy that the technical staff of semiconductor applications is familiar with
Different details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have
Other embodiment.
It should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that when using term "comprising" and/or " comprising " in this manual
When, it, which is indicated, has the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or more
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, the exemplary embodiment according to the present invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Understand be to provide these embodiments be in order that disclosure of the invention is thoroughly and complete, and by these exemplary implementations
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make identical element is presented with like reference characters, thus description of them will be omitted.
Semiconductor devices of the present invention and preparation method are described further with reference to Fig. 1, such as Fig. 1 institutes
Show, Semiconductor substrate 201 be provided first,
Specifically, the Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, silicon-on-insulator
（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）And germanium on insulator SiClx
（SiGeOI）Deng.Could be formed with doped region and/or isolation structure in the substrate, the isolation structure be shallow trench every
From（STI）Structure or selective oxidation silicon（LOCOS）Isolation structure.
The substrate selects P type substrate in the present invention, and specifically, those skilled in the art select P commonly used in the art
Type substrate, N traps are then formed in the P type substrate, in an embodiment of the present invention, first in the P type substrate
N trap windows are formed, ion implanting is carried out in the N traps window, annealing steps is then performed and promotes to form N traps.
Then SiO is formed over the substrate2Boundary layer, pass through rapid thermal oxidation process（RTO）Or ald work
Skill（ALD）To form SiO2 boundary layers 202, grid stack layer is then formed on the semiconductor substrate, including stack gradually
Gate dielectric 203, coating 204 and gate material layers 205, specifically, the gate dielectric is formed from hafnium
Layer, is used for example in Hf02The middle ratio for introducing the element such as Si, Al, N, La, Ta and optimizing each element is come obtained hafnium etc..
Wherein, the method for forming gate dielectric can be physical gas-phase deposition or atom layer deposition process.
In an embodiment of the present invention, in the SiO2HfAION gate dielectrics are formed on boundary layer, its thickness is 15 to 60 angstroms.So
The coating of gate stack structures is formed on gate dielectric afterwards, the coating is TiN layer in the present invention, as preferred
Can also in TiN layer deposit diffusion barriers, can be TaN layers or AlN layers.Finally grid material is formed on the coating
The bed of material, the gate material layers are preferably the polysilicon material layer of n-type doping in the present invention.
The polysilicon material layer of the n-type doping can pass through ion diffusion or the side of ion implanting in the present invention
Method is formed, and when forming the polysilicon material layer from ion method of diffusion, can be passed through while deposition containing needed for
The admixture of gas of dopant, it is doped while deposition；Preferably, the method for ion implanting is selected in the present invention
Form the n-type doping polysilicon.
The grid stack layer is etched to form grid structure over the substrate；
Specifically, the SiO that photoetching process can be used to form above step2Boundary layer, high k dielectric layer, coating
And the polysilicon material layer of n-type doping, the grid structure is obtained, the grid formed has the structure of storehouse.
Then, carry out forming offset side wall（offset spacer）The step of.The material of offset side wall can be nitridation
The insulating materials such as silicon, silica or silicon oxynitride.Offset side wall can improve the channel length of the transistor of formation, reduce short
Channelling effect and the hot carrier's effect caused by short-channel effect.
Then entered using the mask layer of the grid structure, the skew side wall of grid structure and ion implanting window as mask
Source/drain (LDD) is lightly doped in the N traps of grid structure both sides in row.The method of the formation LDD can be LDD ion implantings
Technique.The foreign ion injected in the present invention is boron.According to the concentration of required foreign ion, ion implantation technology can be with one
Step or multistep are completed.
The n-type doping area can be formed by the method for LDD ion implantings or source and drain ion implanting in the present invention,
Preferably, formed in the present invention preferably by the method for LDD ion implantings, during from LDD ion implantings with it is described light
Doped source/drain (LDD) is carried out simultaneously；Preferably the polysilicon layer is n-type doping in the present invention as further,
The doping of the polysilicon can be formed by the LDD ion implantings of the step.In addition, as a kind of embodiment, in this hair
Can also be formed described in bright by the method for source and drain ion implanting, in the method, first have in the grid structure and
It is lightly doped on source/drain (LDD) and forms mask layer, then described n-type doping is gone to carry out source and drain ion implanting.Wherein institute
State n-type doping area to be located in the N traps, the either side of the grid structure.
As shown in figure 3, the foreign ion mixed in LDD injection in the present invention or source and drain injection technology is phosphorus, arsenic,
One kind or combination in antimony, bismuth.
When removing the polysilicon gate as dummy gate, the polysilicon of the anti-fuse structures is covered using coating
Grid, the coating is removed substantially simultaneously during the CMP of metal gates afterwards, can be used here commonly used in the art each
Kind material is used as the coating, such as silicon nitride.The N-type gate material layers and the N traps are used for dropping in the present invention
The program voltage of the low anti-fuse structures, at the same by reduce work function control programming after electric current leakage.In the present invention
Middle to use high K polysilicon gates, the area of grid in the polysilicon gate is not by metal gates Chemical Mechanical Polishing (CMP)
Limitation, the area of grid accurately adjusted, design when can obtain more suitable program voltage.
Wherein described n-type doping area connects the first earth terminal Vss1, the source and drain doping area connection second of the grid both sides
Earth terminal Vss2, wherein, the source and drain of the grid both sides is only capable of injecting to form shallow doped region by LDD, and with the grid
The both sides of structure overlap.
The antifuse is programmed with two kinds of programs, and wherein the first is that the n-type doping area is floating（Floating）, institute
The source and drain ground connection of the both sides of grid structure is stated, applies programm voltage on the grid（Program voltage）, i.e. Vss1=
Floating, Vss2 are grounded, and the device has Low dark curient electric current after programming,（lower post-program
leakage）, the ON corresponded in conventional antifuse state；The anti-fuse structures also have another program, work as institute
State n-type doping area to be grounded, the source and drain of the both sides of grid structure is floating in the PMOS area（Floating）, on the grid
Apply programm voltage（Program voltage）, i.e. Vss1 ground connection, Vss2=Floating, grid is in the situation in sequencing
There is high leakage current afterwards（lower post-program leakage）, the OFF corresponded in conventional antifuse state；
Realize the sequencing of the anti-fuse structures respectively by above two state.
In addition, present invention also offers a kind of anti-fuse structures, the anti-fuse structures include：
Semiconductor substrate；
N traps, in the substrate；
Polysilicon gate, on the substrate above the N traps；
High k dielectric layer, between the polysilicon gate and the substrate；
Source and drain doping area, in the N traps of the grid both sides；
N-type doping area, in the N traps on the outside of the source and drain doping area.
Wherein, during the n-type doping area ground connection, the device has high leakage current, the source-drain area after programming
During ground connection, when the source-drain area is grounded, the device has Low dark curient electric current after programming, pass through above two state point
The sequencing of the anti-fuse structures is not realized.
Specifically, be also formed with coating between the grid and the high k dielectric layer, the high k dielectric layer with it is described
Boundary layer is also formed between substrate；The grid is n-type doping；The source and drain doping area has part weight with the grid
It is folded.
As shown in figure 3, wherein described substrate 201 is preferably P type substrate, the grid structure comprises at least gate material layers
205, the gate material layers are preferably polysilicon layer, and the polysilicon layer is n-type doping；Preferably, in the polysilicon
Further comprising boundary layer 202, high k dielectric layer 203, coating 204 under layer, wherein, the interface layer layer is preferably SiO2,
Hafnium is used in Hf02The middle ratio for introducing the element such as Si, Al, N, La, Ta and optimizing each element obtains, and the coating is
TiN layer.
The antifuse is programmed with two kinds of programs, and wherein the first is floating in the n-type doping area（Floating）,
The source and drain doping area ground connection of the both sides of the grid structure, applies programm voltage on the grid（Program voltage）,
That is Vss1=Floating, Vss2 are grounded, and grid is that the device has Low dark curient electric current after programming in the situation,
（lower post-program leakage）, as shown in figure 4, the ON corresponded in conventional antifuse state；
The anti-fuse structures also have another program, when the n-type doping area be grounded, the two of the grid structure
The source and drain doping area of side is floating（Floating）, apply programm voltage on the grid（Program voltage）, i.e. Vss1
Ground connection, Vss2=Floating, the device has high leakage current after programming, when the source-drain area is grounded（lower
post-program leakage）, the OFF corresponded in conventional antifuse state is as shown in Figure 5；Pass through above two shape
State realizes the sequencing of the anti-fuse structures.
Fig. 6 is the preparation method of anti-fuse structures of the present invention, is comprised the following steps：
Step 201 provides Semiconductor substrate；
Step 202 forms N traps over the substrate；
Step 203 forms high k dielectric layer, polysilicon layer on the substrate above the N traps, and patterns to be formed
Polysilicon gate；
Step 204 forms source and drain doping area in the N traps of the grid both sides；
Step 205 forms n-type doping area in the N traps on the outside of the source and drain doping area.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
1. a kind of anti-fuse structures, including：
Semiconductor substrate；
N traps, in the substrate；
Polysilicon gate, on the substrate above the N traps, the grid is n-type doping, passes through the N-type grid and institute
N traps are stated to reduce the program voltage of the anti-fuse structures；
High k dielectric layer, between the polysilicon gate and the substrate；
Source and drain doping area, in the N traps of the grid both sides, the doping type in the source and drain doping area is N-type；
N-type doping area, in the N traps on the outside of the source and drain doping area, the n-type doping area and the source and drain doping section every
Set.
2. structure according to claim 1, it is characterised in that during the n-type doping area ground connection, the grid is in sequencing
There is high leakage current afterwards, when the source-drain area is grounded, the grid has Low dark curient electric current after programming, passes through above-mentioned two
Kind method can realize leakage current after two kinds of different sequencing in the anti-fuse structures.
3. structure according to claim 1, it is characterised in that the anti-fuse structures also include being located at the grid both sides
Skew side wall.
4. structure according to claim 1, it is characterised in that be also formed between the grid and the high k dielectric layer
Coating.
5. structure according to claim 1, it is characterised in that be also formed between the high k dielectric layer and the substrate
Boundary layer.
6. structure according to claim 1, it is characterised in that the source and drain doping area has part weight with the grid
It is folded.
7. a kind of preparation method of anti-fuse structures, including：
Semiconductor substrate is provided；
N traps are formed over the substrate；
High k dielectric layer, polysilicon layer are formed on the substrate above the N traps, and is patterned to form polysilicon gate,
The grid is n-type doping, and the program voltage of the anti-fuse structures is reduced by the N-type grid and the N traps；
Source and drain doping area is formed in the N traps of the grid both sides, the doping type in the source and drain doping area is N-type；
N-type doping area, the n-type doping area and the source and drain doping section are formed in the N traps on the outside of the source and drain doping area
Every setting.
8. according to the method for claim 7, it is characterised in that the n-type doping area passes through LDD ion implantings or source and drain
The method of ion implanting is formed.
9. according to the method for claim 7, it is characterised in that the source-drain area is formed by LDD ion implantings, to ensure
The source-drain area has with the grid to partly overlap.
10. according to the method for claim 7, it is characterised in that methods described is additionally included in the grid and is situated between with the high K
The step of coating is formed between electric layer.
11. according to the method for claim 7, it is characterised in that methods described be additionally included in the high k dielectric layer with it is described
The step of boundary layer is formed between substrate.
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6897543B1 (en) * | 2003-08-22 | 2005-05-24 | Altera Corporation | Electrically-programmable integrated circuit antifuses |
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| US6630724B1 (en) * | 2000-08-31 | 2003-10-07 | Micron Technology, Inc. | Gate dielectric antifuse circuits and methods for operating same |
| US7256471B2 (en) * | 2005-03-31 | 2007-08-14 | Freescale Semiconductor, Inc. | Antifuse element and electrically redundant antifuse array for controlled rupture location |
| US7453755B2 (en) * | 2005-07-01 | 2008-11-18 | Sandisk 3D Llc | Memory cell with high-K antifuse for reverse bias programming |
| KR101398636B1 (en) * | 2008-12-17 | 2014-05-22 | 삼성전자주식회사 | Transistor dielectric rupture type anti-fuse utilizing CHISEL or CHISHL, and program circuit having it |
| WO2011050464A1 (en) * | 2009-10-30 | 2011-05-05 | Sidense Corp. | Twin well split-channel otp memory cell |
| US20110108926A1 (en) * | 2009-11-12 | 2011-05-12 | National Semiconductor Corporation | Gated anti-fuse in CMOS process |
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| US6897543B1 (en) * | 2003-08-22 | 2005-05-24 | Altera Corporation | Electrically-programmable integrated circuit antifuses |
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