CN103943512A - Method for reducing graphene and electrode contact resistance - Google Patents

Method for reducing graphene and electrode contact resistance Download PDF

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Publication number
CN103943512A
CN103943512A CN201410189193.XA CN201410189193A CN103943512A CN 103943512 A CN103943512 A CN 103943512A CN 201410189193 A CN201410189193 A CN 201410189193A CN 103943512 A CN103943512 A CN 103943512A
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graphene
electrodes
film
source
reduction
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CN103943512B (en
Inventor
王浩敏
谢红
王慧山
孙秋娟
卢光远
陈吉
张学富
吴天如
谢晓明
***
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66015Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
    • H01L29/66037Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66045Field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions

Abstract

The invention provides a method for reducing graphene and electrode contact resistance. The method includes the steps: firstly, providing a substrate and forming graphene on the substrate; secondly, forming BN (boron nitride) membranes exposed to the edges of two ends of the graphene on the surface of the graphene; thirdly, defining source and drain electrode areas to form a metal catalytic layer, annealing metal catalytic layer in hydrogen atmosphere, reuniting the metal catalytic layer to form catalyst particles, reacting hydrogen with the graphene and the BN membranes along the edges of the catalyst particles, and forming holes with zigzag structures in the surfaces of the graphene and the BN membranes; fourthly, forming a source, a drain metal electrode, a grid dielectric layer and a grid electrode. The graphene is etched by the aid of the metal catalytic layer, the metal catalytic layer is reunited to form small particles in the annealing process in the hydrogen atmosphere, the surface of the BN/graphene is etched by the hydrogen along the edges of the particles to form the holes with the Zigzag edge structures, and the holes, the subsequently deposited source and the drain metal electrode can form strong chemical bonds, so that the metal electrode more effectively contacts with the graphene.

Description

A kind of method that reduces Graphene and Electrodes
Technical field
The present invention relates to microelectronics technology, particularly relate to a kind of method that reduces Graphene and Electrodes.
Background technology
Graphene is since coming out, and its excellent electrology characteristic is as high electron mobility, and thermal conductivity is strong, and conductance is high, Stability Analysis of Structures, and electron transfer speed is fast, has caused people's extensive concern, is expected to be used to manufacture high-performance electronic of new generation and learns device.But, in the research based on graphene device, find that electric property and theoretical value that test obtains differ greatly.Wherein Graphene-Metal Contact resistance becomes the most important factor that affects Graphene transistor performance.At present, have been reported and reduce the Electrodes between Graphene and metal by various method, the most frequently used method is to Graphene being carried out to after annealing processing before metallizing, although research shows annealing and can remove the pollution on Graphene surface, on the impact of Electrodes little.Or adopt atomic force scan process, UV/ozone (UVO) is processed, the methods such as plasma treatment, but these methods are not only time-consuming but also can destroy graphene-structured.Experiment showed, the contact resistance that only can not effectively reduce Graphene metal by removing the residual photoresist on Graphene surface.And the method for annealing again by electron beam exposure or oxygen plasma treatment, can be in Graphene edge defect, plated metal subsequently, forms " contactless " Graphene-Metal Contact interface, can effectively reduce the contact resistance of graphene device.If but unannealed, the edge being etched along Graphene can form the structure of unordered amorphous, the contact area of Graphene and metal also will diminish.
And will adopt a kind of easier method to effectively reduce the Electrodes of graphene device herein, adopt metal catalytic etching Graphene, in atmosphere of hydrogen, in graphite aggregate alkene, can form and there is Zigzag border hole subsequently, then plated metal can obtain less Graphene Metal Contact resistance.The present invention and CMOS manufacturing process compatibility, can be applied to the making of graphene nano electronic device and and be hopeful to be applied in graphene-based integrated circuit.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method that reduces Graphene and Electrodes, for solving the large problem of contact resistance between prior art Graphene and metal electrode.
For achieving the above object and other relevant objects, the invention provides a kind of method that reduces Graphene and Electrodes, described method at least comprises the following steps:
1) provide a substrate, on described substrate, form Graphene;
2) form BN film on described Graphene surface, described BN film exposes the edge at Graphene two ends;
3) the Graphene edge that graphic definition comprises exposure and source, the drain electrode region of part BN film, in described source, drain regions area deposition form metal catalytic layer, and anneal in hydrogen atmosphere, described metal catalytic layer is reunited and form catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts with Graphene and BN film along the edge of described catalysed particulate, at the hole of Graphene and BN film surface formation laciniation;
4) in described source, drain regions area deposition metal forms source, leaks metal electrode, described source, leaks metal electrode and fills and cover in described hole, contact with the formation of described Graphene;
5) on Graphene between described metal electrode and BN film, form gate dielectric layer, and form grid on described gate dielectric layer.
Preferably, described step 1) in backing material be Si, SiO 2, SiO 2any one in/Si, GaAs or GaN.
Preferably, described step 1) the middle method acquisition graphene film that adopts mechanical stripping or chemical vapor deposition growth to shift, adopt again photoetching or electron beam exposure definition Graphene etching figure, finally adopt reactive ion beam etching (RIBE) method to form step 1 by oxygen plasma etch graphene film) in required banded Graphene.
Preferably, described step 2) in BN film be that mechanical stripping obtains, transfer to step 1) in described structure; The thickness of described BN film is 10~30nm.
Preferably, described step 2) in the Graphene border width that exposes be 1~2 atomic layer degree of depth.
Preferably, described step 3) in the thickness of metal catalytic layer that forms of deposition be 1~10nm.
Preferably, described metal catalytic layer is any one in nickel, gold, chromium, copper, platinum.
Preferably, described step 3) annealing process in also comprise and pass into argon gas, adopt the argon hydrogen mixed atmosphere of 150~250sccm flow to anneal, wherein, Ar and H 2flow-rate ratio is 1.8:1~2:1, and annealing temperature is 200~600 DEG C, and annealing time scope is 10~30min.
Preferably, described step 4) in source, to leak the thickness of metal electrode be 30~100nm.
Preferably, described source, leakage metal electrode material are nickel.
Preferably, described step 5) the middle described gate dielectric layer of method growth formation that adopts ald.
Preferably, the described gate dielectric layer of formation is Al 2o 3, the thickness of gate dielectric layer is 10~50nm.
Preferably, in described step 5) afterwards, also comprise the step that forms respectively contact electrode on described source, leakage metal electrode and gate electrode.
As mentioned above, the method for reduction Graphene of the present invention and Electrodes, comprises step: first, provide a substrate, on described substrate, form Graphene; Then, form BN film on described Graphene surface, described BN film exposes the edge at Graphene two ends; Then, graphic definition comprises the Graphene edge of exposure and source, the drain electrode region of part BN film, in described source, drain regions area deposition form metal catalytic layer, and anneal in hydrogen atmosphere, described metal catalytic layer is reunited and form catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts with Graphene and BN film along the edge of described catalysed particulate, at the hole of Graphene and BN film surface formation laciniation; Then in described source, drain regions area deposition forms source, leaks metal electrode; Finally on Graphene between described metal electrode and BN film, form gate dielectric layer, and form grid on described gate dielectric layer.The present invention adopts metal catalytic layer etching Graphene: in the process of annealing under atmosphere of hydrogen, metal catalytic layer is reunited and is formed little particle, hydrogen starts etching BN/ Graphene surface along the edge of nickel particle, form triangle or the hexagonal hole with Zigzag marginal texture.And the pore quantity that BN/ Graphene is etched depends on the thickness of deposited thin layer nickel film, nickel thickness is thinner, and the Graphene hole that etching forms is more.Metal catalytic layer etching technics makes the hole edge of the flawless Zigzag of the having structure of Graphene surface formation, and can form extremely strong chemical bond with the source depositing subsequently, leakage metal electrode, and metal electrode is contacted better with Graphene.The metal electrode that the present invention obtains is without in addition in annealing, and Graphene Metal Contact resistance also will reduce greatly, can obtain higher carrier mobility.
Brief description of the drawings
Fig. 1 is shown as the present invention reduces the method flow schematic diagram of Graphene and Electrodes.
Fig. 2 a is substrate schematic perspective view of the present invention.
Fig. 2 b is substrate cutaway view of the present invention.
Fig. 3 a is the structural upright schematic diagram that forms Graphene on substrate.
Fig. 3 b is the structure cutaway view that forms Graphene on substrate.
Fig. 4 a is the structural upright schematic diagram that Graphene is etched.
Fig. 4 b is the structure cutaway view that Graphene is etched.
Fig. 5 a is the structural upright schematic diagram that forms BN film on substrate.
Fig. 5 b is the cutaway view that forms BN film on substrate.
Fig. 6 a is the structural upright schematic diagram after etching BN film.
Fig. 6 b is the structure cutaway view after etching BN film.
Fig. 7 a forms the structure vertical view of sheet metal Catalytic Layer in S/D region.
Fig. 7 b forms the cutaway view of sheet metal Catalytic Layer in S/D region.
Fig. 8 is structure vertical view after substrat structure annealing.
Fig. 9 is the structure vertical view of S/D area deposition thick-layer metallic nickel electrode.
Figure 10 is the structure vertical view of ALD growth gate dielectric layer.
Figure 11 is the structure vertical view of gate electrode of growing on gate dielectric layer.
Figure 12 is the structure vertical view that etching gate medium exposes source, leakage metal electrode.
Figure 13 is the structure vertical view that forms S/D/G electrode contact.
Element numbers explanation
S1~S5 step
1 substrate
2 Graphenes
3 BN films
4 metal catalytic nickel thin layers
5 sources, leakage metal electrode
6 gate dielectric layers
7 grids
8 contact electrodes
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The invention provides a kind of method that lowers Graphene and Electrodes, as shown in Figure 1, described method at least comprises step:
S1, provides a substrate, on described substrate, forms Graphene;
S2, forms BN film on described Graphene surface, and described BN film exposes the edge at Graphene two ends;
S3, graphic definition comprises the Graphene edge of exposure and source, the drain electrode region of part BN film, in described source, drain regions area deposition form metal catalytic layer, and anneal in hydrogen atmosphere, described metal catalytic layer is reunited and form catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts with Graphene and BN film along the edge of described catalysed particulate, at the hole of Graphene and BN film surface formation zigzag (zigzag) structure;
S4, in described source, drain regions area deposition forms source, leaks metal electrode, described source, leaks metal electrode and is filled in described hole, forms and contacts with described Graphene;
S5 forms gate dielectric layer, and form grid on described gate dielectric layer on Graphene between described metal electrode and BN film.
Below in conjunction with concrete accompanying drawing, the method for reduction Graphene of the present invention and Electrodes is done to detailed introduction.
First perform step S1, a substrate is provided, on described substrate, form Graphene.
Referring to accompanying drawing 2a and Fig. 2 b, is substrate 1 provided by the invention, and described substrate 1 includes but not limited to Si, SiO 2, SiO 2/ Si, GaAs, GaN etc., in the present embodiment, be preferably SiO 2/ Si substrate.In this step, also comprise the cleaning step of substrate 1, in the present embodiment, adopt standard RCA technique to clean described SiO 2/ Si substrate.
Refer to accompanying drawing 3a and Fig. 3 b, for forming Graphene 2 films on described substrate 1 surface.Wherein, Graphene 2 films can be transferred on described substrate 1 and be obtained by chemical vapour deposition (CVD) (CVD) growth, can be also directly to obtain by the method for mechanical stripping.The present embodiment is preferably and adopts CVD growth transfer to obtain.
Refer to accompanying drawing 4a and Fig. 4 b, for forming required Graphene 2 by 2 films of Graphene described in etching.Detailed process is: by the etching figure of photoetching or electron beam exposure definition Graphene 2, and adopt reactive ion etching (RIE) to form the Graphene 2 of banded structure by oxygen plasma etch graphene film.
Perform step afterwards S2, form BN film on described Graphene surface, described BN film exposes the edge at Graphene two ends.
Can adopt mechanical stripping method to obtain after BN film the BN film transfer obtaining to described substrate, thereby on described substrate 1, form the BN film 3 that covers described Graphene 2, as shown in Fig. 5 a and 5b.The THICKNESS CONTROL of described BN film 3 is within the scope of 10~30nm.
As Fig. 6 a and 6b are depicted as the structure that the BN film in etching Fig. 5 a and 5b forms, so that described BN film 3 exposes the edge at Graphene 2 two ends, Graphene 2 border widths of exposure are 1~2 atomic layer degree of depth.Concrete forming process is: successively obtain at Fig. 5 a and 5b structure on form 90nm PMMA and 90nm hydrogen radical siloxane HSQ electron beam adhesive as etch mask layer, through after electron beam exposure, adopt ICP etching BN film to obtain as BN film 3 structures of Fig. 6 a and 6b.Because BN film 3 lattices and Graphene 2 is approximate and surface is comparatively smooth, it is good insulating material, can completely cut off Graphene surface and contact with the direct of metal electrode, the Graphene Zigzag edge formation Metal Contact that the hole forming after making metal electrode by follow-up metal catalytic etching BN/ Graphene and etching obtain.
Then perform step S3, the source of the Graphene edge that graphic definition comprises exposure and part BN film, drain electrode region, in described source, drain regions area deposition form metal catalytic layer, and anneal in hydrogen atmosphere, described metal catalytic layer is reunited and form catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts with Graphene and BN along the edge of described catalysed particulate, at the hole of Graphene table and BN face formation laciniation.
The metal catalytic nickel thin layer 4 forming is as shown in Fig. 7 a and 7b.Particularly, adopt photoetching or electron beam exposure definition source, drain electrode region, and stringer metal catalytic nickel film 4, peel off and remove photoresist subsequently.Graphene 2 edges that described source, drain electrode region comprise exposure and part BN film 3, therefore, the metal catalytic nickel film 4 of deposition covers Graphene 2 edges and part BN film 3.Can adopt sputter or electron-beam evaporation metal catalytic nickel film 4, the thickness of this sheet metal catalytic nickel film 4 is 1~10nm.In the present embodiment, metal catalytic nickel film 4 is preferably 2nm left and right.
In the argon hydrogen mixed atmosphere that is 200sccm at flow by the structure of Fig. 7 a and 7b, anneal, wherein, Ar and H 2flow-rate ratio is 2:1.Annealing temperature is arranged within the scope of 200~600 DEG C, and annealing time is 10~30min.In the process of hydrogen annealing, sheet metal catalytic nickel film 4 is reunited and is formed little particle, hydrogen starts etching Graphene 2 and BN film 3 surfaces along the edge of these nickel particles, make BN/ Graphene surface form triangle or the hexagonal hole with zigzag (Zigzag) marginal texture, the structure after annealing as shown in Figure 8.Wherein the mechanism of nickel catalysis etching is: under the catalytic action of nickel, Graphene 2 reacts with hydrogen: C (solid)+2H 2(gas)---CH 4(gas); BN film 3 reacts with hydrogen: BN (solid)+H 2(gas)---B xh y(Gas)+NH 3(gas).Nickle atom group is final forms the island being embedded in Graphene 2 and BN film 3, and the pore quantity that Graphene is etched depends on the thickness of deposited thin layer nickel catalytic film, and nickel thickness is thinner, and the Graphene hole that etching forms is more.Nickel catalysis etching technics makes the hole edge of the flawless Zigzag of the having structure of Graphene surface formation, and can become with the thick-layer nickel film-shaped depositing subsequently extremely strong chemical bond.The electrode obtaining is without in addition in annealing, and Graphene Metal Contact resistance also will reduce greatly.Described metal catalytic material can be nickel, gold, chromium, titanium, copper, platinum etc.In the present embodiment, preferably adopt nickel as metal catalytic material.
Then perform step S4, in described source, drain regions area deposition forms source, leaks metal electrode, described source, leak metal electrode and be filled in described hole, form and contact with described Graphene.
Particularly, the step in definition source, drain electrode region in repeating step S3.In the source defining, drain electrode region, deposit thick-layer nickel film as metal electrode material, peeling off removes photoresist obtains source, leak metal electrode 5, be illustrated in figure 9 vertical view, this source, leakage metal electrode 5 cover in Graphene 2, BN film 3 surfaces and hole, form and contact with described Graphene 2.
Due to the catalysis corrasion of sheet metal nickel Catalytic Layer in step S3, before deposition thick-layer metallic nickel electrode, BN/ Graphene surface has been etched and has formed triangle or the hexagonal hole with Zigzag marginal texture, therefore, between Graphene 2 and metal electrode 4, can form extremely strong chemical bond by orbital hybridization, thereby the Graphene-metal electrode contact resistance obtaining is effectively reduced.Graphene 2 edges of 1~2 the atom width simultaneously exposing in step S2 can be etched equally and form Zigzag structure, can be directly and Metal Contact form the electrode contact structure of good approximate one dimension.The thickness of its medium bed source, leakage metal electrode 4 nickel films is 30~100nm.
Perform step again S5, on Graphene between described metal electrode and BN film, form gate dielectric layer, and form grid on described gate dielectric layer.
Refer to accompanying drawing 10, the gate dielectric layer 6 that the method that first adopts ald (ALD) is 10~50nm at whole substrate surface growth thickness, the body structure surface that this gate dielectric layer 6 obtains step S4 all covers, and this gate dielectric layer 6 can be Al 2o 3.
Refer to accompanying drawing 11, then adopt photoetching or electron beam exposure (EBL) graphic definition gate electrode figure, plated metal Ti/Au forms gate electrode 7 on the gate dielectric layer between source, leakage metal electrode 4.
Refer to accompanying drawing 12, adopt the etching figure of photoetching or electron beam exposure (EBL) graphic definition gate dielectric layer, etching gate dielectric layer 6 exposes source, leaks metal electrode 4.
Refer to accompanying drawing 13, after formation source, leakage metal electrode 4 and gate electrode 7, adopt photoetching or electron beam exposure (EBL) graphic definition S/D/G electrode contact figure, plated metal Ti/Au, peeling off removes photoresist forms the contact electrode 8 of S/D/G, is convenient to subsequent device performance test.
In sum, the invention provides a kind of method that reduces Graphene and Electrodes, adopt the method for metal catalytic etching Graphene to process Graphene, depositing metal films forms the contact of Graphene-metal electrode subsequently.When the method is annealed Graphene under atmosphere of hydrogen, metal material meeting catalysis etching Graphene has formed the hole of perfect Zigzag structure, therefore can effectively reduce the Graphene Metal Contact resistance of graphene device, makes carrier mobility improve 1.5 times.Device technology can further be annealed after completing again simultaneously.Preparation method provided by the invention and traditional cmos manufacturing process compatibility, for Graphene is applied to nano electron device and graphene-based integrated circuit provides good solution.
So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.

Claims (14)

1. a method that reduces Graphene and Electrodes, is characterized in that, the method for described reduction Graphene and Electrodes at least comprises step:
1) provide a substrate, on described substrate, form Graphene;
2) form BN film on described Graphene surface, described BN film exposes the edge at Graphene two ends;
3) the Graphene edge that graphic definition comprises exposure and source, the drain electrode region of part BN film, in described source, drain regions area deposition form metal catalytic layer, and anneal in hydrogen atmosphere, described metal catalytic layer is reunited and form catalysed particulate, under the catalytic action of catalysed particulate, described hydrogen reacts with Graphene and BN film along the edge of described catalysed particulate, at the hole of Graphene and BN film surface formation laciniation;
4) in described source, drain regions area deposition forms source, leaks metal electrode, described source, leaks metal electrode and fills and cover in described hole, contact with the formation of described Graphene;
5) on the Graphene between described metal electrode and BN film, form gate dielectric layer, and form grid on described gate dielectric layer.
2. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 1) in backing material be Si, SiO 2, SiO 2any one in/Si, GaAs or GaN.
3. the method for reduction Graphene according to claim 1 and Electrodes, it is characterized in that: described step 1) the middle method acquisition graphene film that adopts mechanical stripping or chemical vapor deposition growth to shift, adopt again photoetching or electron beam exposure definition Graphene etching figure, finally adopt reactive ion beam etching (RIBE) method to form step 1 by oxygen plasma etch graphene film) in required banded Graphene.
4. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 2) in BN film be that mechanical stripping obtains, transfer to step 1) in described structure; The thickness of described BN film is 10~30nm.
5. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 2) in the Graphene border width that exposes be 1~2 atomic layer degree of depth.
6. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 3) in the thickness of metal catalytic layer that forms of deposition be 1~10nm.
7. the method for reduction Graphene according to claim 6 and Electrodes, is characterized in that: described metal catalytic layer is any one in nickel, gold, chromium, copper, platinum.
8. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 3) in the hole of laciniation be triangle or hexagon.
9. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 3) annealing process in also comprise and pass into argon gas, adopt the argon hydrogen mixed atmosphere of 150~250sccm flow to anneal, wherein, Ar and H 2flow-rate ratio is 1.8:1~2:1, and annealing temperature is 200~600 DEG C, and annealing time scope is 10~30min.
10. the method for reduction Graphene according to claim 1 and Electrodes, is characterized in that: described step 4) in source, to leak the thickness of metal electrode be 30~100nm.
The method of 11. reduction Graphenes according to claim 10 and Electrodes, is characterized in that: described source, leakage metal electrode material are nickel.
The method of 12. reduction Graphenes according to claim 1 and Electrodes, is characterized in that: described step 5) the middle described gate dielectric layer of method growth formation that adopts ald.
The method of 13. reduction Graphenes according to claim 12 and Electrodes, is characterized in that: the described gate dielectric layer of formation is Al 2o 3, the thickness of gate dielectric layer is 10~50nm.
The method of 14. reduction Graphenes according to claim 1 and Electrodes, is characterized in that: in described step 5) afterwards, also comprise the step that forms respectively contact electrode on described source, leakage metal electrode and gate electrode.
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CN108231559A (en) * 2016-12-09 2018-06-29 全球能源互联网研究院 A kind of contact electrode preparation method and MOSFET power devices
CN108548852A (en) * 2018-06-27 2018-09-18 北京镭硼科技有限责任公司 A kind of graphene-based film-type hydrogen gas sensor and preparation method thereof
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CN110676169A (en) * 2019-09-05 2020-01-10 中国电子科技集团公司第十三研究所 Preparation method of graphene capsule-packaged transistor

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CN104851787A (en) * 2015-04-01 2015-08-19 中国科学院上海微***与信息技术研究所 Method for improving ohmic contact between metal electrode and graphene
CN104992905A (en) * 2015-06-05 2015-10-21 中国科学院上海微***与信息技术研究所 Boron nitride substrate surface step etching method
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