CN103929192A - Partial parallel input right shift accumulation QC-LDPC encoder in near-earth communications - Google Patents

Abstract

The invention provides a partial parallel input right shift accumulation QC-LDPC encoder in near-earth communications. The partial parallel input right shift accumulation QC-LDPC encoder comprises a 511-bit shifting register used for conducting rotate right on information segments, two generator polynomial lookup tables which are prestored and generate all circulant matrix generator polynomials in a matrix, two 511-bit binary multipliers which are used for conducting scalar multiplication on the content of the shifting register and the bits of the generator polynomials, two 511-bit binary adders which are used for conducting modulo 2 addition on products and the content of accumulators, and the two 511-bit accumulators. Finally, calibration data are included in the two accumulators. The partial parallel input encoder is suitable for QC-LDPC codes in a CCSDS near-earth communication system and has the advantages of being few in register, simple in structure, small in power consumption, low in cost, high in working efficiency, large in throughput capacity and the like.

Description

The cumulative QC-LDPC encoder that moves to right of part parallel input in near-earth communication

Technical field

The present invention relates to field of channel coding, particularly the cumulative QC-LDPC encoder that moves to right of part parallel input in a kind of CCSDS near-earth communication system.

Background technology

Low-density checksum (Low-Density Parity-Check, LDPC) code is one of efficient channel coding technology, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.Generator matrix G and the check matrix H of QC-LDPC code are all the arrays being made up of circular matrix, have the feature of segmentation circulation, therefore be called as QC-LDPC code.The first trip of circular matrix is the result of 1 of footline ring shift right, and all the other each provisional capitals are results of 1 of its lastrow ring shift right, and therefore, circular matrix is characterized by its first trip completely.Conventionally, the first trip of circular matrix is called as its generator polynomial.

CCSDS near-earth communication standard adopts the QC-LDPC code of system form, and the left-half of its generator matrix G is a unit matrix, and right half part is by a × c b × b rank circular matrix G _i,jthe array that (0≤i<a, a≤j<t, t=a+c) forms, as follows:

Wherein, I is b × b rank unit matrixs, the full null matrix in the 0th, b × b rank.Capable and the b row of the continuous b of G are called as respectively the capable and piece row of piece.From formula (1), G has the capable and t piece of a piece row.Make circular matrix G _i,jfirst trip _{gi, j}it is its generator polynomial.CCSDS near-earth communication standard has adopted a kind of QC-LDPC code, wherein, and a=14, b=511, c=2, t=16.

For CCSDS near-earth communication standard, the corresponding code word v=of generator matrix G (s, p), that the front a piece of G is listed as correspondence is information vector s=(e ₀, e ₁..., e _{a × b-1}), that rear c piece row are corresponding is verification vector p=(d ₀, d ₁..., d _{c × b-1}).Taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1); Verification vector p is divided into c section, i.e. p=(p ₀, p ₁..., p _c-1).From v=sG, j-a section verification vector meets

p _j-a＝s ₀G _0,j+s ₁G _1,j+…+s _iG _i,j+…+s _a-1G _a-1,j (2)

Wherein, 0≤i<a, a≤j<t, t=a+c.Order with respectively generator polynomial g _i,jthe result of ring shift right n position and ring shift left n position, wherein, 0≤n≤b.So, the i item on formula (2) equal sign the right is deployable is

$s_i{G}_{i,j}=e_{i\&times;b}{g}_{i,j}^{r\left(0\right)}+e_{i\&times;b+1}{g}_{i,j}^{r\left(1\right)}+...+e_{i\&times;b+b-1}{g}_{i,j}^{r(b-1)}---\left(3\right)$

What at present, QC-LDPC code extensively adopted is the serial encoder that adds accumulator (Type-I Shift-Register-Adder-Accumulator, SRAA-I) circuit based on c I type shift register.Fig. 1 is the functional block diagram of single SRAA-I circuit, and information vector s by turn serial sends into this circuit.When using SRAA-I circuit to verification section _pj-awhen (a≤j<t) encodes, all generator polynomials of the j piece row of the pre-stored generator matrix G of generator polynomial look-up table, accumulator is cleared initialization.In the time that the 0th clock cycle arrives, shift register loads the 0th row of G, the generator polynomial of j piece row from generator polynomial look-up table information bit e ₀move into circuit, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of accumulator, and deposit back accumulator.In the time that the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes information bit e ₁move into circuit, and with the content of shift register carry out scalar multiplication, product content with accumulator mould 2 adds, and deposit back accumulator.Above-mentionedly move to right-take advantage of-Jia-storing process proceeds down.In the time that b-1 clock cycle finishes, information bit e _b-1moved into circuit, now that cumulative adder stores is part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.In the time that b clock cycle arrives, shift register loads the 1st row of G, the generator polynomial of j piece row from generator polynomial look-up table repeat above-mentionedly to move to right-take advantage of-Jia-storing process.As message segment s ₁while moving into circuit completely, cumulative adder stores be part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until the whole serials of whole information vector s move into circuit.Now, cumulative adder stores is verification section _pj-a.Use c the serial encoder shown in SRAA-I circuit energy pie graph 2, it obtains c verification section within a × b clock cycle simultaneously.This scheme needs 2 × c × b register, c × b two input and door and c × b two input XOR gate, also needs the generator polynomial of c a × b bit ROM storage circular matrix.

In CCSDS near-earth communication standard, the existing solution of QC-LDPC encoder is based on 2 SRAA-I circuit.This scheme has two shortcomings: the one, need 2044 registers, and cause the power consumption of circuit large, cost is high; The 2nd, serial input information bit, loaded in parallel generator polynomial, needs 1023 connecting lines.So many line can cause that circuit structure complexity, the operating frequency of encoder is low, throughput is little.

Summary of the invention

In CCSDS near-earth communication system there is the shortcoming that power consumption is large, cost is high, circuit structure is complicated, operating frequency is low, throughput is little in the existing implementation of QC-LDPC encoder, for these technical problems, the invention provides a kind of part parallel input coding device based on moving to right cumulative.

As shown in Figure 4, in CCSDS near-earth communication system, the cumulative QC-LDPC encoder that moves to right of part parallel input is mainly made up of 5 parts: shift register, generator polynomial look-up table, b position binary multiplier, b position binary adder and accumulator.Cataloged procedure divides 5 steps to complete: the 1st step, zero clearing accumulator R ₀and R ₁; The 2nd step, shift register input message section s _i(0≤i<a); The 3rd step, generator polynomial look-up table L ₀and L ₁export respectively generator matrix G i piece capable in the 14th and the generator polynomial bit of 15 row, these generator polynomial bits are respectively by b position binary multiplier M ₀and M ₁carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀and M ₁product respectively by b position binary adder A ₀and A ₁with accumulator R ₀and R ₁content be added, b position binary adder A ₀and A ₁with deposit respectively accumulator R in ₀and R ₁; The 4th step, one of shift register ring shift right, repeats the 3rd step b time; The 5th step, changes the value of i taking 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, accumulator R ₀and R ₁that store is respectively verification section p ₀and p ₁, they have formed verification vector p=(p ₀, p ₁).

Part parallel input coding device provided by the invention is simple in structure, can, keeping, under the condition of coding rate, reducing register and line, reduce power consumption and cost, improves operating frequency and throughput.

Can be further understood by detailed description and accompanying drawings below about advantage of the present invention and method.

Brief description of the drawings

Fig. 1 is the functional block diagram that I type shift register adds accumulator SRAA-I circuit;

Fig. 2 is the QC-LDPC serial encoder being made up of c SRAA-I circuit;

Fig. 3 is the functional block diagram that II type shift register adds accumulator SRAA-II circuit;

Fig. 4 is a kind of part parallel input QC-LDPC encoder based on moving to right cumulative being made up of 2 SRAA-II circuit.

Embodiment

Below in conjunction with accompanying drawing, preferred embodiment of the present invention is elaborated, thereby so that advantages and features of the invention can be easier to be it will be appreciated by those skilled in the art that, protection scope of the present invention is made to more explicit defining.

Make generator polynomial _{gi, j}=( _{gi, j, 0, gi, j, 1}..., _{gi, j, b-1}), G _i,jcan be considered the weighted sum of unit matrix ring shift right version,

G _i,j＝g _i,j,0I ^r(0)+g _i,j,1I ^r(1)+…+g _i,j,b-1I ^r(b-1) (4)

So, the i item on formula (2) equal sign the right is deployable is

$\begin{array}{c}{s}_i{G}_{i,j}=s_i(g_{i,j,0}{I}^{r\left(0\right)}+g_{i,j,1}{I}^{r\left(1\right)}+...+g_{i,j,b-1}{I}^{r(b-1)})\\ =g_{i,j,0}{s}_i{I}^{r\left(0\right)}+g_{i,j,1}{s}_i{I}^{r\left(1\right)}+...+g_{i,j,b-1}{s}_i{I}^{r(b-1)}\\ =g_{i,j,0}{s}_i^{r\left(0\right)}+g_{i,j,1}{s}_i^{r\left(1\right)}+...+g_{i,j,b-1}{s}_i^{r(b-1)}\end{array}---\left(5\right)$

Compared with formula (3), the remarkable advantage of formula (5) is the parallel input information bits of segmentation, and serial loads generator polynomial _{gi, j}.Formula (5) is one and moves to right-take advantage of-process of Jia-storage, and it is realized and adds accumulator (Type-II Shift-Register-Adder-Accumulator, SRAA-II) circuit with II type shift register.Fig. 3 is the functional block diagram of SRAA-II circuit, and information vector s is taking b bit as one section of parallel this circuit of sending into.When using SRAA-II circuit to verification section _pj-awhen (a≤j<t) encodes, all generator polynomials of the j piece row of the pre-stored generator matrix G of generator polynomial look-up table, accumulator is cleared initialization.In the time that the 0th clock cycle arrives, message segment s ₀move into shift register, the 0th row of generator polynomial look-up table output G, the generator polynomial g of j piece row _{0, j}the 0th bit g _{0, j, 0}, and with the content of shift register carry out scalar multiplication, product add with content 0 mould 2 of accumulator, and deposit back accumulator.In the time that the 1st clock cycle arrives, 1 of shift register ring shift right, content becomes generator polynomial look-up table output g _{0, j}the 1st bit g _{0, j, 1}, and with the content of shift register carry out scalar multiplication, product content with accumulator mould 2 adds, and deposit back accumulator.Above-mentionedly move to right-take advantage of-Jia-storing process proceeds down.In the time that b-1 clock cycle finishes, generator polynomial look-up table has been exported g _{0, j}last bit g _{0, j, b-1}, now that cumulative adder stores is part and s ₀g _{0, j}, this is message segment s ₀to p _j-acontribution.In the time that b clock cycle arrives, message segment s ₁move into shift register, repeat above-mentionedly to move to right-take advantage of-Jia-storing process.When generator polynomial look-up table has been exported g _{1, j}last bit g _{1, j, b-1}time, cumulative adder stores be part and s ₀g _{0, j}+ s ₁g _{1, j}.Repeat said process, until all parallel circuit that moves into of whole information vector s.Now, cumulative adder stores is verification section _pj-a.

Fig. 4 has provided a kind of part parallel input QC-LDPC encoder based on moving to right cumulative being made up of 2 SRAA-II circuit, is made up of shift register, generator polynomial look-up table, b position binary multiplier, b position binary adder and accumulator five functions module.Shift register is to message segment s _i(0≤i<a) ring shift right.Generator polynomial look-up table L ₀and L ₁the all circular matrix generator polynomials that prestore respectively in generator matrix G the 14th and 15 row.Generator polynomial look-up table L ₀and L ₁the generator polynomial bit of output carries out scalar multiplication with the content of shift register respectively, and these 2 scalar multiplications are respectively by b position binary multiplier M ₀and M ₁complete.B position binary multiplier M ₀and M ₁product respectively with accumulator R ₀and R ₁content be added, these 2 nodulo-2 additions are respectively by b position binary adder A ₀and A ₁complete.B position binary adder A ₀and A ₁with deposit respectively accumulator R in ₀and R ₁.

Generator polynomial look-up table L ₀and L ₁circular matrix generator polynomial in storage QC-LDPC code generator matrix.L ₀and L ₁store respectively all generator polynomials in the 14th and 15 row of G, for arbitrary row, store successively the 0th, 1 ..., 13 generator polynomials that row is corresponding.

The invention provides a kind of part parallel input QC-LDPC coding method based on moving to right cumulative, be applicable to the QC-LDPC code in CCSDS near-earth communication standard, its coding step is described below:

The 1st step, zero clearing accumulator R ₀and R ₁;

The 2nd step, shift register input message section s _i(0≤i<a);

The 3rd step, generator polynomial look-up table L ₀and L ₁export respectively generator matrix G i piece capable in the 14th and the generator polynomial bit of 15 row, these generator polynomial bits are respectively by b position binary multiplier M ₀and M ₁carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀and M ₁product respectively by b position binary adder A ₀and A ₁with accumulator R ₀and R ₁content be added, b position binary adder A ₀and A ₁with deposit respectively accumulator R in ₀and R ₁;

The 4th step, one of shift register ring shift right, repeats the 3rd step b time;

The 5th step, changes the value of i taking 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, accumulator R ₀and R ₁that store is respectively verification section p ₀and p ₁, they have formed verification vector p=(p ₀, p ₁).

Be not difficult to find out from above step, whole cataloged procedure needs a × b clock cycle altogether, identical with the existing serial encoding method based on 2 SRAA-I circuit.

In CCSDS near-earth communication standard, the existing solution of QC-LDPC encoder needs 2044 registers, 1022 two inputs and door and 1022 two input XOR gate, and the present invention needs 1533 registers, 1022 two inputs and door and 1022 two input XOR gate.Two kinds of coding methods expend equal number with door and XOR gate, but the present invention has saved 25% register.

Existing solution needs 1023 lines to connect shift register and generator polynomial look-up table, and the present invention only needs 513 connecting lines.

As fully visible, for the encoder of QC-LDPC code in CCSDS near-earth communication standard, compared with existing solution, the present invention has kept identical coding rate, save 1/4 register, greatly simplify circuit connection, there is the advantages such as simple in structure, power consumption is little, cost is low, operating frequency is high, throughput is large.

The above; it is only one of the specific embodiment of the present invention; but protection scope of the present invention is not limited to this; any those of ordinary skill in the art are in the disclosed technical scope of the present invention; the variation that can expect without creative work or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.

Claims (3)

1. the cumulative QC-LDPC encoder that moves to right of part parallel input in near-earth communication, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, _{gi, j}circular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, CCSDS near-earth communication standard has adopted a kind of QC-LDPC code, a=14, b=511, c=2, t=16, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁), it is characterized in that, described encoder comprises following parts:

B bit shift register is carried out ring shift right to message segment;

Generator polynomial look-up table L ₀and L ₁, in the QC-LDPC code generator matrix G that prestores respectively the 14th and the circular matrix generator polynomial of 15 row;

B position binary multiplier M ₀and M ₁, the content to shift register and generator polynomial look-up table L respectively ₀and L ₁output bit carry out scalar multiplication;

B position binary adder A ₀and A ₁, respectively to b position binary multiplier M ₀and M ₁sum of products accumulator R ₀and R ₁content carry out mould 2 and add;

Accumulator R ₀and R ₁, store respectively b position binary adder A ₀and A ₁result and final verification section p ₀and p ₁.

2. a kind of cumulative QC-LDPC encoder that moves to right of part parallel input in near-earth communication according to claim 1, is characterized in that described generator polynomial look-up table L ₀and L ₁store respectively all generator polynomials in the 14th and 15 row of G, for arbitrary row, store successively the 0th, 1 ..., 13 generator polynomials that row is corresponding.

3. the cumulative QC-LDPC coding method that moves to right of part parallel input in near-earth communication, the generator matrix G of QC-LDPC code is divided into the capable and t piece row of a piece, and it is by a × c b × b rank circular matrix G that rear c piece is listed as corresponding part generator matrix _i,jthe array forming, _{gi, j}circular matrix G _i,jgenerator polynomial, wherein, t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<a, a≤j<t, CCSDS near-earth communication standard has adopted a kind of QC-LDPC code, a=14, b=511, c=2, t=16, the corresponding code word v=of generator matrix G (s, p), that the front a piece row of G are corresponding is information vector s, and that rear c piece row are corresponding is verification vector p, taking b bit as one section, information vector s is divided into a section, i.e. s=(s ₀, s ₁..., s _a-1), verification vector p is divided into c section, i.e. p=(p ₀, p ₁), it is characterized in that, described coding method comprises the following steps:

The 1st step, zero clearing accumulator R ₀and R ₁;

The 2nd step, shift register input message section s _i, wherein, 0≤i<a;

The 3rd step, generator polynomial look-up table L ₀and L ₁export respectively generator matrix G i piece capable in the 14th and the generator polynomial bit of 15 row, these generator polynomial bits are respectively by b position binary multiplier M ₀and M ₁carry out scalar multiplication with the content of shift register, b position binary multiplier M ₀and M ₁product respectively by b position binary adder A ₀and A ₁with accumulator R ₀and R ₁content be added, b position binary adder A ₀and A ₁with deposit respectively accumulator R in ₀and R ₁;

The 4th step, one of shift register ring shift right, repeats the 3rd step b time;

The 5th step, changes the value of i taking 1 as step-length increases progressively, and repeats 2nd～4 step a time, until that whole information vector s inputs is complete, now, accumulator R ₀and R ₁that store is respectively verification section p ₀and p ₁, they have formed verification vector p=(p ₀, p ₁).