CN103929162B - Gate driving circuit, power switch circuit and grid drive method - Google Patents
Gate driving circuit, power switch circuit and grid drive method Download PDFInfo
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Abstract
Disclose a kind of gate driving circuit, power switch circuit and grid drive method.The gate driving circuit includes power end, earth terminal, input and output end, the gate driving circuit receives gate drive input signal in input, gate driver output signal is provided in output end, for driving semiconductor switch device, wherein, the gate driving circuit also includes clamp end, and, when gate drive input signal is the first level, voltage difference between output end and clamp end is remained the first steady state value by the gate driving circuit, when gate drive input signal is second electrical level, voltage difference between output end and clamp end is remained the second steady state value by the gate driving circuit.The gate driving circuit can remain the gate source voltage of semiconductor switch device constant voltage difference, change without the influence due to load.The gate driving circuit can protect semiconductor switch device not puncture due to high gate source voltage.
Description
Technical field
The present invention relates to power switch circuit, more particularly to the gate driving circuit for semiconductor switch device, bag
Power switch circuit and grid drive method containing gate driving circuit.
Background technology
Power switch circuit for drive motor includes semiconductor switch device, such as MOS field
Effect transistor (MOSFET) and igbt (IGBT) etc..In power switch circuit, it is connected with the power supply end
High side semiconductor switch device sometimes needs to bear the high voltage more than 600V.LDMOS effect
Answer transistor (ldmos transistor) be included in identical region injection twice and high temperature progradation formation source region and leakage
Area.In ldmos transistor, source region and drain region square horizontal proliferation under the gate form a raceway groove with concentration gradient.This
Outside, ldmos transistor source region formation with the well region of the conduction type opposite dopant type of ldmos transistor, drain region shape
In the drift region of the high resistant of the conduction type opposite dopant type of Cheng Yu devices.Due to the presence of drift region, LDMOS drain electrode
High voltage can be born.Ldmos transistor has the advantages that large-drive-current, low on-resistance and high-breakdown-voltage, widely
Semiconductor switch device as power switch circuit, particularly as bearing high-tension high side semiconductor switch device.
Although LDMOS drain electrode can bear high voltage, the source configuration of ldmos transistor still with it is conventional
MOSFET is the same.Ldmos transistor is easy to due to high gate source voltage VGSAnd puncture.Accordingly, it would be desirable to design suitable grid
Drive circuit provides suitable gate drive voltage for the high side semiconductor switch device of ldmos transistor etc.
The content of the invention
It is an object of the invention to provide a kind of gate driving circuit that can protect semiconductor switch device at work,
Power switch circuit and grid drive method comprising the gate driving circuit.
According to the first aspect of the invention there is provided a kind of gate driving circuit, including power end, earth terminal, input and
Output end, the gate driving circuit receives gate drive input signal in input, and raster data model output is provided in output end
Signal, for driving semiconductor switch device, wherein, the gate driving circuit also includes clamp end, also, in raster data model
When input signal is the first level, it is permanent that the voltage difference between output end and clamp end is remained first by the gate driving circuit
Definite value, when gate drive input signal is second electrical level, the gate driving circuit is by output end and clamps the electricity between end
Pressure difference remains the second steady state value.
Preferably, in the gate driving circuit, first steady state value is more than the second steady state value, and described second
Steady state value is substantially equal to 0.
Preferably, the first level is higher than second electrical level in the gate driving circuit.
Preferably, the gate driving circuit also includes：Be sequentially connected in series first resistor between power end and ground,
The first transistor and the first current source；It is sequentially connected in series the second current source, the second crystal between power end and clamp end
Pipe and second resistance；It is sequentially connected in series the 3rd current source, third transistor and the 4th crystalline substance between power end and clamp end
Body pipe；And the 3rd resistor between output end and clamp end is connected to, wherein, the grid of the 4th transistor is connected to the second crystalline substance
The intermediate node of body pipe and second resistance, when gate drive input signal is the first level, the first transistor and the 3rd crystal
Pipe is turned on, and second transistor and the 4th transistor disconnect, and when gate drive input signal is second electrical level, first crystal
Pipe and third transistor disconnect, second transistor and the 4th transistor turns.
Preferably, the gate driving circuit also includes：First phase inverter, its input is connected to first resistor and first
The intermediate node of transistor, its output end is connected to the grid of second transistor；And second phase inverter, its input is connected to
The output end of first phase inverter, its input is connected to the grid of third transistor.
Preferably, in the gate driving circuit, when gate drive input signal is the first level, the first transistor
Conducting, the output end of the first phase inverter produces the first level so that second transistor disconnects, and the output end of the second phase inverter is produced
Second electrical level so that third transistor is turned on, because second transistor disconnects, the gate source voltage difference of the 4th transistor is 0 so that
4th transistor disconnects, and the 3rd current source produces constant current, flows through 3rd resistor, is produced between output end and clamp end permanent
Fixed voltage difference；And when gate drive input signal is second electrical level, the first transistor disconnects, the output of the first phase inverter
End produces second electrical level so that second transistor is turned on, and the output end of the second phase inverter produces the first level so that the 3rd crystal
Pipe disconnects, due to second transistor conducting, and the grid of the 4th transistor is the first level so that the 4th transistor turns, output
End and clamp end short circuit.
Preferably, the gate driving circuit also includes：Be sequentially connected in series the 4th resistance between power end and ground,
5th transistor and the 4th current source；And first phase inverter, its input is connected to the input of gate driving circuit, and its is defeated
Go out end and be connected to the grid of the 5th transistor, wherein, the grid of third transistor is connected to the first transistor and first resistor
Intermediate node, and the grid of second transistor are connected to the intermediate node of the 4th resistance and the 5th transistor.
Preferably, in the gate driving circuit, when gate drive input signal is the first level, the first transistor
Conducting, produces second electrical level so that third transistor is turned in the grid of third transistor, and the output end of the first phase inverter is produced
Second electrical level so that the 5th transistor disconnects, correspondingly, second transistor and the 4th transistor are disconnected, and the 3rd current source is produced
Constant current, flows through 3rd resistor, and constant voltage difference is produced between output end and clamp end；And in raster data model input
When signal is second electrical level, the first transistor disconnects, and produces the first level in the grid of third transistor so that third transistor
Disconnect, the output end of the first phase inverter produces the first level so that the 5th transistor turns, correspondingly, second transistor conducting,
Due to second transistor conducting, the grid of the 4th transistor is the first level so that the 4th transistor turns, output end and clamp
Hold short circuit.
Preferably, in the gate driving circuit, each in the first to the 3rd current source is by auxiliary transistor structure
Into.
Preferably, in the gate driving circuit, first and the 4th transistor be the first conduction type MOSFET, the
Two and third transistor be the second conduction type MOSFET.
Preferably, in the gate driving circuit, the first conduction type is one kind in N-type and p-type, the second conductive-type
Type is another in N-type and p-type.
According to the second aspect of the invention there is provided a kind of power switch circuit, including：It is sequentially connected in series in the first power supply
The first high side semiconductor switch device and the first downside semiconductor switch device between voltage and ground；And as described above
One gate driving circuit, wherein, the first high side semiconductor switch device and the first downside semiconductor switch device include source respectively
Pole, drain and gate, the power end of the first grid drive circuit are connected to second source voltage, and the first grid
The output end of drive circuit is connected with the grid of the first high side semiconductor switch device, the pincers of the first grid drive circuit
Position end is connected with the source electrode of the first high side semiconductor switch device.
Preferably, in the power switch circuit, in the first high side semiconductor switch device and the first downside semiconductor
There is provided load driving voltage between the intermediate node and ground of switching device.
Preferably, the power switch circuit also includes：It is sequentially connected in series between the first supply voltage and ground
Two high side semiconductor switch devices and the second downside semiconductor switch device；And second grid drive circuit as described above,
Wherein, the second high side semiconductor switch device and the second downside semiconductor switch device include source electrode, drain and gate, institute respectively
The power end for stating second grid drive circuit is connected to second source voltage, and the second grid drive circuit output end
It is connected with the grid of the second high side semiconductor switch device, clamp end and the second high side half of the second grid drive circuit
The source electrode of conductor switching device is connected.
Preferably, in the power switch circuit, in the first high side semiconductor switch device and the first downside semiconductor
The intermediate node of the intermediate node of switching device and the second high side semiconductor switch device and the second downside semiconductor switch device
Between there is provided load driving voltage.
Preferably, in the power switch circuit, the first high side semiconductor switch device and the first downside semiconductor are opened
Close the MOSFET that device is respectively identical conduction type.
Preferably, in the power switch circuit, the first high side semiconductor switch device and the first downside semiconductor are opened
It is respectively ldmos transistor to close device.
Preferably, in the power switch circuit, second source voltage is 2 multiple values of the first supply voltage.
There is provided a kind of grid drive method for being used to drive semiconductor switch device, bag according to the third aspect of the invention we
Include：Gate drive input signal is received in input, and gate driver output signal is provided in output end, wherein, in grid
When drive input signal is the first level, the voltage difference between output end and clamp end is remained into the first steady state value, in grid
When drive input signal is second electrical level, the voltage difference between output end and clamp end is remained into the second steady state value.
Preferably, in the process, first steady state value is more than the second steady state value, and second steady state value is big
Cause to be equal to 0.
Preferably, in the process, the first level is higher than second electrical level.
Gate driving circuit according to an embodiment of the invention, can in the whole controlling cycle of semiconductor switch device
It is always constant voltage difference or 0 to keep the voltage difference between the output end of gate driving circuit and clamp end, so that by LDMOS
The gate source voltage V of transistorGSThe constant voltage difference or 0 are remained, is changed without the influence due to load.At work,
The gate driving circuit may insure the normal switch switching of semiconductor switch device, while protecting semiconductor switch device will not
Punctured due to high voltage.
Brief description of the drawings
By description referring to the drawings to the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 is the schematic circuit of the power switch circuit according to prior art；
Fig. 2 is the oscillogram of the power switch circuit according to prior art shown in Fig. 1；
Fig. 3 is the schematic circuit of the power switch circuit according to embodiments of the invention；And
Fig. 4 is the first reality of the gate driving circuit used in power switch circuit according to an embodiment of the invention
Example；And
Fig. 5 is the second reality of the gate driving circuit used in power switch circuit according to an embodiment of the invention
Example.
Embodiment
Various embodiments of the present invention are more fully described hereinafter with reference to accompanying drawing.In various figures, identical element
Represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
Fig. 1 is the schematic circuit of the power switch circuit according to prior art.In the configuration of prior art, power
On-off circuit can include two ldmos transistors for being arranged to half-H-bridge, or four are arranged the LDMOS crystal for helping H bridges
Pipe, for driving load.
In the power switch circuit shown in Fig. 1, four ldmos transistor M1-M4 according to full configuration of H bridge are shown.
First group of two ldmos transistors M1 and M3 are connected between power supply VCC and ground GND, second group of two ldmos transistor M2 and
M4 is connected between power supply VCC and ground GND, forms symmetrical bridge arm.In first group of two ldmos transistors M1 and M3 centre
Between node and second group of two ldmos transistors M2 and M4 intermediate node, connection load.It is connected to power supply VCC and centre
Two ldmos transistor M1 and M2 between node are connected between two between node and ground GND respectively as high-side switch
Individual ldmos transistor M3 and M4 is respectively as low side switch.Power switch circuit also includes charge pump U0, for producing power supply
VCC 2 times of voltage, i.e. 2*VCC.Gate driving circuit U1-U4 includes input, output end, power end and earth terminal respectively.
Grid of the gate driving circuit U1-U4 output end respectively with ldmos transistor M1-M4 is connected, to control it to be turned on or off.
Gate driving circuit U1 and U2 power end are connected with charge pump U0, to obtain 2*VCC supply voltage, gate driving circuit U3
Power supply VCC is connected directly to U4 power end.
Fig. 2 is the oscillogram of the power switch circuit shown in Fig. 1.Gate driving circuit U1 input A1 and raster data model
The input B2 of circuit U 4 receives identical first grid drive input signal.It is the first electricity in first grid drive input signal
Usually, gate driving circuit U1 output end H1 provides such as 2*VCC first grid drive output signal, gate driving circuit
U4 output end L2 provides VCC the 4th gate driver output signal.When first grid drive input signal is second electrical level,
Gate driving circuit U1 output end H1 and gate driving circuit U4 output end L2 gate driver output signal are second
Level, such as GND.In one example, the first level is higher than second electrical level.Gate driving circuit U2 input A2 and grid
Drive circuit U3 input B1 receives identical second grid drive input signal.It is the in second grid drive input signal
During one level, gate driving circuit U2 output end H2 provides such as 2*VCC second grid drive output signal, raster data model
The output end L1 of circuit U 3 provides VCC the 3rd gate driver output signal.It is the second electricity in second grid drive input signal
Usually, gate driving circuit U2 output end H2 and gate driving circuit U3 output end L1 gate driver output signal are
Second electrical level, such as GND.
The grid and second group of LDMOS of ldmos transistor M1 (i.e. the first high-side switch) in first group of ldmos transistor
The grid of ldmos transistor M4 (i.e. the second low side switch) in transistor receives identical gate driver output signal, thus
Simultaneously turn on or disconnect.Similarly, in second group of ldmos transistor ldmos transistor M2 (i.e. the second high-side switch) grid
Pole and the ldmos transistor M3 (i.e. the first low side switch) in first group of ldmos transistor grid receive identical grid and driven
Dynamic output signal, thus simultaneously turn on or disconnect.The power switch circuit has two kinds of working conditions, in the first working condition
In, ldmos transistor M1 and M4 conducting, and ldmos transistor M2 and M3 disconnect, in the second working condition, ldmos transistor
M1 and M4 is disconnected, and ldmos transistor M2 and M3 are turned on, so as to alternately provide electric current to load.LDMOS as high-side switch
Transistor M1, M2 have the drain electrode that is connected with VCC and the source electrode being connected with load respectively, in its conducting state, and electric current is from power supply
VCC flow direction loads, its source voltage pull-up is VCC.Ldmos transistor M3, M4 as low side switch have and load respectively
Connected drain electrode and the source electrode being connected with ground GND, its source voltage remain GND.
By taking the first working condition as an example, when ldmos transistor M1 is turned on, its grid voltage is 2*VCC.If electric
Motivation normally starts, then its source voltage pull-up is VCC, gate source voltage VGS=2*VCC-VCC.If however, motor fails
Start in time, ldmos transistor M1 source voltage is likely to be very low.Ldmos transistor M1 VGSIt is possible to be much larger than
VCC, even up to 2*VCC.As a result, ldmos transistor M1 is easy to due to high gate source voltage VGSAnd puncture.Similarly, exist
In second working condition, ldmos transistor M2 is equally easy to due to high gate source voltage VGSAnd puncture.
In addition, similar with the full bridge configuration shown in Fig. 1, in half-H-bridge configuration, two ldmos transistors are connected on power supply
Between VCC and ground GND.Between the intermediate node and ground GND of two ldmos transistors, connection load.At work, two
Ldmos transistor alternate conduction, so as to provide electric current to load.Ldmos transistor for high-side switch may also be due to height
Gate source voltage VGSAnd puncture.
Fig. 3 is the schematic circuit of the power switch circuit according to embodiments of the invention.Figure 3 illustrates according to
Four ldmos transistor M1-M4 of full configuration of H bridge.Power switch circuit also includes charge pump U0,2 for producing power supply VCC
Voltage again, i.e. 2*VCC.Four gate driving circuit U1-U4 include input, output end, power end and earth terminal respectively.Four
Grid of the individual gate driving circuit U1-U4 output end respectively with four ldmos transistor M1-M4 is connected, to control it to turn on
Or disconnect.High side gate drive circuit U1 and U2 power end are connected with charge pump U0, low to obtain 2*VCC supply voltage
Side gate driving circuit U3 and U4 power end are connected directly to power supply VCC.
It is different from the power switch circuit according to prior art shown in Fig. 1, two raster data models for high-side switch
Circuit U 1 and U2 include additional clamp end S1 and S2 respectively.Gate driving circuit U1 clamp end S1 and ldmos transistor M1
Source electrode be connected.During ldmos transistor M1 is turned on, between gate driving circuit U1 output end H1 and clamp end S1
Voltage is always steady state value, so that by ldmos transistor M1 gate source voltage VGSThe steady state value is remained, without due to high electricity
Press and puncture.Similarly, gate driving circuit U2 clamp end S2 is connected with ldmos transistor M2 source electrode.It is brilliant in LDMOS
During body pipe M2 is turned on, the voltage difference between gate driving circuit U2 output end H2 and clamp end S2 is always steady state value, from
And by ldmos transistor M2 gate source voltage VGSThe steady state value is remained, without puncturing due to high voltage.
In addition, similar with the full bridge configuration shown in Fig. 3, in half-H-bridge configuration, two ldmos transistors are connected on power supply
Between VCC and ground GND.Between the intermediate node and ground GND of two ldmos transistors, connection load.At work, two
Ldmos transistor alternate conduction, so as to provide electric current to load.High side gate drive circuit includes input, output end, power supply
End and earth terminal, and additional clamp end.The clamp end of the gate driving circuit and the ldmos transistor for high-side switch
Source electrode be connected.
Fig. 4 is the first of the gate driving circuit U1 used in power switch circuit according to an embodiment of the invention
Example.Gate driving circuit U1 includes input A1, output end H1, power end 2*VCC and earth terminal GND, and additional pincers
Position end S1.
First resistor R1, the first transistor M11 and the first current source Id1 are sequentially connected in series on power end 2*VCC and ground
Between GND.The first transistor M11 grid is connected with input A1.Second current source Id2, second transistor M12 and second
Resistance R2 is sequentially connected in series between power end 2*VCC and clamp end S1.First phase inverter N1 input is connected to first
Resistance R1 and the first transistor M11 intermediate node, its output end are connected to second transistor M12 grid.3rd current source
Id3, third transistor M13 and the 4th transistor M14 are sequentially connected in series between power end 2*VCC and clamp end S1.4th
Transistor M14 grid is connected to second transistor M12 and second resistance R2 intermediate node.Second phase inverter N2 input
The first phase inverter N1 output end is connected to, its output end is connected to third transistor M13 grid.Third transistor M13 and
4th transistor M14 intermediate node is connected to output end H1.3rd resistor is connected between output end H1 and clamp end S1.
First phase inverter N1 and the second phase inverter N2 the first level are output as 2*VCC, and second electrical level is output as VCC.
Under first phase inverter N1 and the second phase inverter N2 control, second transistor M12 and third transistor M13 alternate conductions and disconnected
Open.
In the embodiment shown in fig. 4, the first transistor M11 and the 4th transistor M14 is N-type MOSFET, the second crystal
Pipe M12 and third transistor M13 is p-type MOSFET.In alternate embodiments, in first to fourth transistor M11-M14
Each can be N-type MOSFET or p-type MOSFET.In addition, the above-mentioned first to the 3rd current source Id1-Id3 respectively can be with
It is made up of auxiliary transistor.
At work, gate driving circuit U1 input A1 receives gate drive input signal as shown in Figure 2, for example
Pwm signal.
When gate drive input signal is the first level, the first transistor M11 conductings.First current source Id1 produces permanent
Determine electric current, ground GND is flow to from power end 2*VCC via first resistor R1.The second electricity is produced in the first phase inverter N1 input
It is flat.First phase inverter N1 output end produces the first level so that second transistor M12 disconnects.Second phase inverter N2 output
End produces second electrical level so that third transistor M13 is turned on.Simultaneously as second transistor M12 disconnects, the 4th transistor M14
Gate source voltage difference be 0 so that the 4th transistor M14 disconnect.As a result, the 3rd current source Id3 produces constant current, from power end
2*VCC flow to ground GND via 3rd resistor R3.Constant voltage difference will be produced at 3rd resistor R3 two ends.So, high side
LDMOS M1 gate source voltage VGSConstant voltage difference is remained, is changed without the influence due to load.
When gate drive input signal is second electrical level, the first transistor M11 cut-offs.In the first phase inverter N1 input
End produces the first level.First phase inverter N1 output end produces second electrical level so that second transistor M12 is turned on.Second is anti-
Phase device N2 output end produces the first level so that third transistor M13 disconnects.Simultaneously as second transistor M12 is turned on,
The constant current that second constant-current source Id2 is produced flow to ground GND via second resistance R2.Produced in the 4th transistor M14 grid
First level so that the 4th transistor M14 is turned on.As a result, short circuit between output end H1 and clamp end S1.So, high side LDMOS
M1 gate source voltage VGS0 is remained, is changed without the influence due to load.
As can be seen here, in the whole cycle of pwm signal, high side LDMOS M1 gate source voltage VGSPerseverance can be remained
Fixed voltage difference, or be 0, without being influenceed by the voltage change loaded.By changing the 3rd current source and the 3rd electricity
The numerical value of resistance, can also control gate source voltage V during high side LDMOS M1 conductingsGSNumerical value.
Fig. 5 is the second of the gate driving circuit U1 used in power switch circuit according to an embodiment of the invention
Example.Gate driving circuit U1 includes input A1, output end H1, power end 2*VCC and earth terminal GND, and additional pincers
Position end S1.
First resistor R1, the first transistor M11 and the first current source Id1 are sequentially connected in series on power end 2*VCC and ground
Between GND.The first transistor M11 grid is connected with input A1.Second current source Id2, second transistor M12 and second
Resistance R2 is sequentially connected in series between power end 2*VCC and clamp end S1.3rd current source Id3, third transistor M13 and
Four transistor M14 are sequentially connected in series between power end 2*VCC and clamp end S1.Third transistor M13 grid is connected to
The first transistor M11 and first resistor R1 intermediate node.4th transistor M14 grid be connected to second transistor M12 and
Second resistance R2 intermediate node.Third transistor M13 and the 4th transistor M14 intermediate node are connected to output end H1.The
Three resistance are connected between output end H1 and clamp end S1.4th resistance R4, the 5th transistor M15 and the 4th current source Id4 according to
It is secondary to be connected in series between power end 2*VCC and ground GND.First phase inverter N1 input is connected with input A1, and its is defeated
Go out the grid that end is connected to the 5th transistor M15.Second transistor M12 grid is connected to the electricity of the 5th transistor M15 and the 4th
Hinder R4 intermediate node.
Under the first phase inverter N1 and the 5th transistor M15 control, second transistor M12 and third transistor M13 are handed over
For turning on and disconnect.
In the embodiment shown in fig. 5, the first transistor M11, the 4th transistor M14 and the 5th transistor M15 are N-type
MOSFET, second transistor M12 and third transistor M13 are p-type MOSFET.In alternate embodiments, first to fourth is brilliant
Each in body pipe M11-M14 can be N-type MOSFET or p-type MOSFET.In addition, first to fourth above-mentioned current source
Id1-Id4 can be made up of auxiliary transistor respectively.
At work, gate driving circuit U1 input A1 receives gate drive input signal as shown in Figure 2, for example
Pwm signal.When gate drive input signal is the first level, the first transistor M11 conductings.First current source Id1 produces permanent
Determine electric current, ground GND is flow to from power end 2*VCC via first resistor R1.The second electricity is produced in third transistor M13 grid
It is flat so that third transistor M13 is turned on.First phase inverter N1 output end produces second electrical level so that the 5th transistor M15 breaks
Open.Correspondingly, second transistor M12 and the 4th transistor M14 disconnect.As a result, the 3rd current source Id3 produces constant current,
Ground GND is flow to from power end 2*VCC via 3rd resistor R3.Constant voltage difference will be produced at 3rd resistor R3 two ends.So,
High side LDMOS M1 gate source voltage VGSConstant voltage difference is remained, is changed without the influence due to load.
When gate drive input signal is second electrical level, the first transistor M11 disconnects.In third transistor M13 grid
Pole produces the first level so that third transistor M13 disconnects.First phase inverter N1 output end produces the first level so that the
Five transistor M15 are turned on.Correspondingly, second transistor M12 is turned on.Due to second transistor M12 conductings, the second constant-current source Id2
The constant current of generation flow to ground GND via second resistance R2.The first level is produced in the 4th transistor M14 grid so that
4th transistor M14 is turned on.As a result, short circuit between output end H1 and clamp end S1.So, high side LDMOS M1 gate source voltage
VGS0 is remained, is changed without the influence due to load.
As can be seen here, in the whole cycle of pwm signal, high side LDMOS M1 gate source voltage VGSPerseverance can be remained
Fixed voltage difference, or be 0, without being influenceed by the voltage change loaded.By changing the 3rd current source and the 3rd electricity
The numerical value of resistance, can also control gate source voltage V during high side LDMOS M1 conductingsGSNumerical value.
Gate driving circuit U1 according to an embodiment of the invention, can in ldmos transistor M1 whole controlling cycle
It is always constant voltage difference or 0 to keep the voltage difference between gate driving circuit U1 output end H1 and clamp end S1, so that
By ldmos transistor M1 gate source voltage VGSThe constant voltage difference or 0 are remained, without puncturing due to high voltage.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, it can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle and practical application of the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The protection model of the present invention
The scope that enclosing should be defined by the claims in the present invention is defined.
Claims (20)
1. a kind of gate driving circuit, including power end, earth terminal, input and output end and clamp end, the grid drive
Dynamic circuit receives gate drive input signal in input, and gate driver output signal is provided in output end, is partly led for driving
Body switching device,
Wherein, the gate driving circuit also includes：
It is sequentially connected in series first resistor, the first transistor and the first current source between power end and ground；
It is sequentially connected in series the second current source, second transistor and second resistance between power end and clamp end；
It is sequentially connected in series the 3rd current source, third transistor and the 4th transistor between power end and clamp end；And
The 3rd resistor between output end and clamp end is connected to,
Wherein, the grid of the 4th transistor is connected to second transistor and the intermediate node of second resistance,
When gate drive input signal is the first level, the first transistor and third transistor conducting, second transistor and the
Four transistors disconnect so that the voltage difference between output end and clamp end remains the first steady state value, and
When gate drive input signal is second electrical level, the first transistor and third transistor disconnect, second transistor and the
Four transistor turns so that the voltage difference between output end and clamp end remains the second steady state value,
The gate driving circuit ensures the normal switch switching of semiconductor switch device, while protecting semiconductor switch device not
It can be punctured due to high voltage.
2. gate driving circuit according to claim 1, wherein first steady state value is more than the second steady state value, and institute
The second steady state value is stated equal to 0.
3. gate driving circuit according to claim 1, wherein the first level is higher than second electrical level.
4. gate driving circuit according to claim 1, in addition to：
First phase inverter, its input is connected to the intermediate node of first resistor and the first transistor, and its output end is connected to
The grid of two-transistor；And
Second phase inverter, its input is connected to the output end of the first phase inverter, and its output end is connected to the grid of third transistor
Pole.
5. gate driving circuit according to claim 4, wherein
When gate drive input signal is the first level, the first transistor conducting, the output end of the first phase inverter produces first
Level so that second transistor disconnects, the output end of the second phase inverter produces second electrical level so that third transistor is turned on, by
Disconnected in second transistor, the gate source voltage difference of the 4th transistor is 0 so that the 4th transistor is disconnected, and the 3rd current source is produced
Constant current, flows through 3rd resistor, and constant voltage difference is produced between output end and clamp end；And
When gate drive input signal is second electrical level, the first transistor disconnects, and the output end of the first phase inverter produces second
Level so that second transistor is turned on, the output end of the second phase inverter produces the first level so that third transistor disconnects, by
In second transistor conducting, the grid of the 4th transistor is the first level so that the 4th transistor turns, output end and clamp end
Short circuit.
6. gate driving circuit according to claim 1, in addition to：
It is sequentially connected in series the 4th resistance, the 5th transistor and the 4th current source between power end and ground；And
First phase inverter, its input is connected to the input of gate driving circuit, and its output end is connected to the 5th transistor
Grid,
Wherein, the grid of third transistor is connected to the first transistor and the intermediate node of first resistor, and second transistor
Grid be connected to the intermediate node of the 4th resistance and the 5th transistor.
7. gate driving circuit according to claim 6, wherein
When gate drive input signal is the first level, the first transistor conducting produces second in the grid of third transistor
Level so that third transistor is turned on, the output end of the first phase inverter produces second electrical level so that the 5th transistor disconnects, phase
Ying Di, second transistor and the 4th transistor disconnect, and the 3rd current source produces constant current, 3rd resistor is flowed through, in output end
Constant voltage difference is produced between clamp end；And
When gate drive input signal is second electrical level, the first transistor is disconnected, and first is produced in the grid of third transistor
Level so that third transistor disconnects, the output end of the first phase inverter produces the first level so that the 5th transistor turns, phase
Ying Di, second transistor conducting, due to second transistor conducting, the grid of the 4th transistor is the first level so that the 4th is brilliant
Body pipe is turned on, output end and clamp end short circuit.
8. gate driving circuit according to claim 1, wherein, each in the first to the 3rd current source is brilliant by auxiliary
Body pipe is constituted.
9. gate driving circuit according to claim 1, wherein first and the 4th transistor be the first conduction type
MOSFET, second and third transistor be the second conduction type MOSFET.
10. gate driving circuit according to claim 9, wherein the first conduction type is one kind in N-type and p-type, the
Two conduction types are another in N-type and p-type.
11. a kind of power switch circuit, including：
The the first high side semiconductor switch device and the first downside being sequentially connected in series between the first supply voltage and ground are partly led
Body switching device；And
Gate driving circuit according to any one of claim 1-10 as first grid drive circuit,
Wherein, the first high side semiconductor switch device and the first downside semiconductor switch device include source electrode, drain electrode and grid respectively
Pole,
The power end of the first grid drive circuit is connected to second source voltage, and
The output end of the first grid drive circuit is connected with the grid of the first high side semiconductor switch device, and described first
The clamp end of gate driving circuit is connected with the source electrode of the first high side semiconductor switch device.
12. power switch circuit according to claim 11, wherein low in the first high side semiconductor switch device and first
There is provided load driving voltage between the intermediate node and ground of side semiconductor switch device.
13. power switch circuit according to claim 11, in addition to：
The the second high side semiconductor switch device and the second downside being sequentially connected in series between the first supply voltage and ground are partly led
Body switching device；And
Gate driving circuit according to any one of claim 1-10 as second grid drive circuit,
Wherein, the second high side semiconductor switch device and the second downside semiconductor switch device include source electrode, drain electrode and grid respectively
Pole,
The power end of the second grid drive circuit is connected to second source voltage, and
The output end of the second grid drive circuit is connected with the grid of the second high side semiconductor switch device, and described second
The clamp end of gate driving circuit is connected with the source electrode of the second high side semiconductor switch device.
14. power switch circuit according to claim 13, wherein low in the first high side semiconductor switch device and first
The intermediate node of side semiconductor switch device and the second high side semiconductor switch device and the second downside semiconductor switch device
There is provided load driving voltage between intermediate node.
15. the power switch circuit according to any one of claim 11-14, wherein the first high side semiconductor switch device
It is respectively the MOSFET of identical conduction type with the first downside semiconductor switch device.
16. power switch circuit according to claim 15, wherein the first high side semiconductor switch device and the first downside
Semiconductor switch device is respectively ldmos transistor.
17. the power switch circuit according to any one of claim 11-14, wherein second source voltage are the first power supply
2 multiple values of voltage.
18. a kind of grid drive method for being used to drive semiconductor switch device, including：
Gate drive input signal is received in input, and
Gate driver output signal is provided in output end,
Wherein, the voltage difference between control output end and clamp end so that, will when gate drive input signal is the first level
The voltage difference remains the first steady state value, and when gate drive input signal is second electrical level, the voltage difference is remained
Second steady state value, so that it is guaranteed that the normal switch switching of semiconductor switch device, while protecting semiconductor switch device will not be by
Puncture in high voltage.
19. method according to claim 18, wherein first steady state value is more than the second steady state value, and described second
Steady state value is equal to 0.
20. method according to claim 18, wherein the first level is higher than second electrical level.
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| CN201410184165.9A CN103929162B (en) | 2014-04-30 | 2014-04-30 | Gate driving circuit, power switch circuit and grid drive method |
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| CN103929162B true CN103929162B (en) | 2017-09-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107026561B (en) * | 2016-02-01 | 2019-07-19 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| JP7151325B2 (en) * | 2018-09-25 | 2022-10-12 | 富士電機株式会社 | driver circuit |
| CN109547009B (en) * | 2018-11-19 | 2022-08-12 | 中国电子科技集团公司第五十八研究所 | High-reliability level shift circuit |
| CN110365324B (en) * | 2019-07-22 | 2024-03-15 | 无锡安趋电子有限公司 | Grid driving circuit of power tube |
| CN113078888B (en) * | 2020-01-06 | 2024-04-19 | 达尔科技股份有限公司 | Gate driving apparatus and control method |
| US11101796B2 (en) | 2020-01-06 | 2021-08-24 | Diodes Incorporated | Gate drive apparatus and control method |
| US11165422B2 (en) * | 2020-04-01 | 2021-11-02 | Delta Electronics, Inc. | Gate driver circuit with reduced power semiconductor conduction loss |
| CN114244339B (en) * | 2022-01-04 | 2022-08-02 | 芯洲科技（北京）有限公司 | Gate drive circuit and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232267A (en) * | 2007-01-02 | 2008-07-30 | Ami半导体比利时有限公司 | Method and apparatus for driving a DC motor |
| CN101373964A (en) * | 2007-08-21 | 2009-02-25 | 艾默生网络能源***有限公司 | Bridge circuit's drive circuit |
| CN103187955A (en) * | 2011-12-31 | 2013-07-03 | 意法半导体研发（上海）有限公司 | Cascade drive circuit |
| CN103401544A (en) * | 2013-07-03 | 2013-11-20 | 西安电子科技大学 | Driving circuit for charge management chip external high-voltage N-channel metal oxide semiconductor (NMOS) transistor |
| CN203800914U (en) * | 2014-04-30 | 2014-08-27 | 杭州士兰微电子股份有限公司 | Grid electrode drive circuit and power switch circuit |
-
2014
- 2014-04-30 CN CN201410184165.9A patent/CN103929162B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232267A (en) * | 2007-01-02 | 2008-07-30 | Ami半导体比利时有限公司 | Method and apparatus for driving a DC motor |
| CN101373964A (en) * | 2007-08-21 | 2009-02-25 | 艾默生网络能源***有限公司 | Bridge circuit's drive circuit |
| CN103187955A (en) * | 2011-12-31 | 2013-07-03 | 意法半导体研发（上海）有限公司 | Cascade drive circuit |
| CN103401544A (en) * | 2013-07-03 | 2013-11-20 | 西安电子科技大学 | Driving circuit for charge management chip external high-voltage N-channel metal oxide semiconductor (NMOS) transistor |
| CN203800914U (en) * | 2014-04-30 | 2014-08-27 | 杭州士兰微电子股份有限公司 | Grid electrode drive circuit and power switch circuit |
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