CN103928331B - The forming method of MOS transistor - Google Patents
The forming method of MOS transistor Download PDFInfo
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- CN103928331B CN103928331B CN201310011744.9A CN201310011744A CN103928331B CN 103928331 B CN103928331 B CN 103928331B CN 201310011744 A CN201310011744 A CN 201310011744A CN 103928331 B CN103928331 B CN 103928331B
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000010410 layer Substances 0.000 claims abstract description 120
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- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000011229 interlayer Substances 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 31
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000011259 mixed solution Substances 0.000 claims abstract description 25
- 239000000243 solution Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000005516 engineering process Methods 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 235000011149 sulphuric acid Nutrition 0.000 claims description 7
- 239000001117 sulphuric acid Substances 0.000 claims description 7
- -1 tetramethyl hydroxylamine Chemical compound 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000007864 aqueous solution Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
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- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
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- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical compound ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
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- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
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- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
A kind of forming method of MOS transistor, including: Semiconductor substrate is provided；Form pseudo-grid structure on the semiconductor substrate, and form interlayer dielectric layer in the Semiconductor substrate of pseudo-grid structure both sides, dummy gate structure includes the pseudo-gate dielectric layer being positioned in Semiconductor substrate and the pseudo-grid being positioned on pseudo-gate dielectric layer, the upper surface of dummy gate and the upper surface flush of described interlayer dielectric layer；Remove dummy gate；Remove dummy gate dielectric layer by the mixed solution of ammonia, hydrogen peroxide and water, form groove；The upper surface flush of grid structure, the upper surface of described grid structure and described interlayer dielectric layer is formed in described groove.The MOS transistor performance that the present invention is formed is good, yield rate is high.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of MOS transistor.
Background technology
Along with the development of semiconductor technology, the characteristic size of MOS transistor constantly reduces, and MOS is brilliant
In body pipe, the thickness of gate dielectric layer also thins down by the principle of scaled down, when described gate medium
The thickness of layer is thin after certain degree, its integrity problem, especially with the puncturing of time correlation, heat
Impurity in carrier effect, gate electrode, to problems such as the diffusions of substrate, will have a strong impact on stablizing of device
Property and reliability.Now, silicon oxide layer has reached its physics limit as gate dielectric layer, utilizes high k material
The gate dielectric layer of material substitutes gate silicon oxide dielectric layer, can keep equivalent oxide thickness (EOT) no
It is greatly increased its physical thickness in the case of change, thus reduces grid leakage current.
Existing technique, when forming the MOS transistor comprising high-g value gate dielectric layer, mainly includes walking as follows
Rapid: with reference to Fig. 1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 is formed pseudo-grid structure and
Being positioned at the interlayer dielectric layer 108 in pseudo-grid structure semiconductor substrates on two sides 100, dummy gate structure includes position
Silicon oxide puppet gate dielectric layer 102 in Semiconductor substrate 100, the polysilicon being positioned on pseudo-gate dielectric layer 102
Pseudo-grid 104 and be positioned at the side wall 106 on pseudo-gate dielectric layer 102 and pseudo-grid 104 sidewall；With reference to Fig. 2, remove
Pseudo-grid 104 described in Fig. 1；With reference to Fig. 3, remove pseudo-grid described in Fig. 2 by the hydrofluoric acid solution of dilution and be situated between
Matter layer 102, forms groove 110；With reference to Fig. 4, in the most described groove 110, form the grid of high-g value
Dielectric layer 112 and the metal gates 114 being positioned on gate dielectric layer 112.
But, find when the MOS transistor detection that above-mentioned technique is formed, the MOS that existing technique is formed
Transistor easily lost efficacy, and yield rate is low.
The U.S. that the forming method of more MOS transistors refer to Application No. US2008149982A1 is special
Profit application.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of MOS transistor, improves formed MOS
The performance of transistor and yield rate.
For solving the problems referred to above, the invention provides the forming method of a kind of MOS transistor, including:
Semiconductor substrate is provided；
Form pseudo-grid structure on the semiconductor substrate, and in the Semiconductor substrate of pseudo-grid structure both sides
Forming interlayer dielectric layer, dummy gate structure includes the pseudo-gate dielectric layer being positioned in Semiconductor substrate and is positioned at
Pseudo-grid on pseudo-gate dielectric layer, the upper surface of dummy gate and the upper surface flush of described interlayer dielectric layer；
Remove dummy gate；
Remove dummy gate dielectric layer by the mixed solution of ammonia, hydrogen peroxide and water, form groove；
Grid structure, the upper surface of described grid structure and described interlayer dielectric layer is formed in described groove
Upper surface flush.
Optionally, the temperature of the mixed solution of described ammonia, hydrogen peroxide and water is 25 DEG C ~ 65 DEG C, ammonia,
The volume ratio of hydrogen peroxide and water is 1:1 ~ 5:50 ~ 200.
Compared with prior art, technical solution of the present invention has the advantage that
Dummy gate dielectric layer is removed, due to ammonia, double by the mixed solution of ammonia, hydrogen peroxide and water
The mixed solution of oxygen water and water is less to the etch rate of interlayer dielectric layer, is removing pseudo-gate dielectric layer process
In, can be prevented effectively from and remove too much interlayer dielectric layer, and then avoid in the forming process of grid structure
At interlayer dielectric layer remained on surface metal material, prevent the metal material residuing in dielectric layer surface to MOS
The performance of transistor impacts, and improves performance and the yield rate of formed MOS transistor.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the schematic diagram forming MOS transistor in existing technique；
Fig. 5 is the schematic flow sheet of forming method one embodiment of MOS transistor of the present invention；
Fig. 6 ~ Figure 10 is the schematic diagram of forming method one embodiment of MOS transistor of the present invention；
Figure 11 is to remove, by the mixed solution of ammonia, hydrogen peroxide and water, the oxygen formed by thermal oxidation technology
During SiClx, remove the graph of a relation of time and removed silicon oxide thickness；
Figure 12 is to be removed by sub-aumospheric pressure cvd by the mixed solution of ammonia, hydrogen peroxide and water
During the silicon oxide that technique is formed, remove the graph of a relation of time and removed silicon oxide thickness.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but this
Bright other can also be used to be different from alternate manner described here implement, therefore the present invention is not by following
The restriction of disclosed specific embodiment.
The most as described in the background section, the MOS transistor that existing technique is formed easily lost efficacy, finished product
Rate is low.
Inventor finds through research, and the MOS transistor that existing technique is formed easily lost efficacy, yield rate
Low mainly caused by following reason: the material of the pseudo-gate dielectric layer 102 of MOS transistor and interlayer in Fig. 1
The material of dielectric layer 108 is silicon oxide, is removing dummy gate medium by the hydrofluoric acid solution of dilution
Layer 102 simultaneously, also can consume the interlayer dielectric layer 108 of segment thickness.But due to pseudo-gate dielectric layer 102 He
The forming method of interlayer dielectric layer 108 is different, and the method forming pseudo-gate dielectric layer 102 is thermal oxidation technology,
The method forming interlayer dielectric layer 108 is chemical vapor deposition method, and the hydrofluoric acid solution of dilution is to pseudo-grid
Dielectric layer 102 and interlayer dielectric layer 108 etch rate also differ, and it is to pseudo-gate dielectric layer 102 and layer
Between dielectric layer 108 etch rate than about 1:13.Therefore, although the thinner thickness of pseudo-gate dielectric layer 102,
But owing to the etch rate of interlayer dielectric layer 108 is much larger than pseudo-gate dielectric layer by the hydrofluoric acid solution of dilution
The etch rate of 102, causes to remove thicker interlayer dielectric layer 108 when removing pseudo-gate dielectric layer 102,
The upper surface of interlayer dielectric layer 108 in Fig. 3 is made to be less than the top of side wall 106.At pseudo-grid 104 and pseudo-grid
After dielectric layer 102 is removed, when forming gate dielectric layer 112 and metal gates 114 in Fig. 4, it is used for
The metal material of formation metal gates 114, while filling up Fig. 3 further groove 110, also covers side wall 106
Top and the interlayer dielectric layer 108 of side wall 106 both sides.Planarize subsequently through chemical mechanical milling tech
Metal material, after forming metal gates 114, is positioned at interlayer dielectric layer 108 surface of side wall 106 both sides
Also covered by metal material 116, have impact on the insulating properties of interlayer dielectric layer 108, cause formed MOS
Transistor nonfunctional, yield rate are low.
Further study show that through inventor, the solution being made up of ammonia, hydrogen peroxide and water is to by changing
Learn gas-phase deposition formed interlayer dielectric layer etch rate with to the puppet formed by thermal oxidation technology
The etch rate of gate dielectric layer is more or less the same, and due to the thinner thickness of pseudo-gate dielectric layer, removes puppet completely
The time of gate dielectric layer is shorter, removes pseudo-gate dielectric layer little on the impact of interlayer dielectric layer.Forming grid
During electrode structure, interlayer dielectric layer can be prevented effectively from and be covered by the metallic material, and then improve formed MOS
The performance of transistor and yield rate.
It is described in detail below in conjunction with specific embodiment.
With reference to Fig. 5, for the schematic flow sheet of forming method one embodiment of MOS transistor of the present invention,
Including:
Step S1, it is provided that Semiconductor substrate；
Step S2, forms pseudo-grid structure, and partly leading in pseudo-grid structure both sides on the semiconductor substrate
Forming interlayer dielectric layer on body substrate, dummy gate structure includes the pseudo-gate medium being positioned in Semiconductor substrate
Layer and the pseudo-grid being positioned on pseudo-gate dielectric layer, the upper surface of dummy gate and the upper table of described interlayer dielectric layer
Face flushes；
Step S3, removes dummy gate；
Step S4, removes dummy gate dielectric layer by the mixed solution of ammonia, hydrogen peroxide and water, is formed
Groove；
Step S5, forms protective layer at described bottom portion of groove；
Step S6, forms gate dielectric layer on described protective layer；
Step S7, forms metal material on described gate dielectric layer and interlayer dielectric layer；
Step S8, carries out flatening process to described metal material, to exposing described interlayer dielectric layer,
Form grid.
With reference to Fig. 6 ~ Figure 12, by specific embodiment the forming method of MOS transistor of the present invention done into
One step explanation.
With reference to Fig. 6, it is provided that Semiconductor substrate 200.
In the present embodiment, the material of described Semiconductor substrate 200 is monocrystal silicon, SiGe, silicon-carbon or III-V
Compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).Described Semiconductor substrate 200 is also formed
There is fleet plough groove isolation structure (not shown), by mutually isolated for adjacent active area.In Semiconductor substrate 200
Also there is well region (not shown), the conduction type of dopant ion and formed MOS transistor in well region
Type is correlated with.When the MOS transistor formed is nmos pass transistor, dopant ion in well region
Conduction type is p-type, such as boron ion, boron difluoride ion etc..When the MOS transistor formed is
During PMOS transistor, in well region, the conduction type of dopant ion is N-type, such as phosphonium ion, arsenic ion etc..
With continued reference to Fig. 6, described Semiconductor substrate 200 forms pseudo-grid structure, and in pseudo-grid structure two
Forming interlayer dielectric layer 208 in the Semiconductor substrate 200 of side, dummy gate structure includes being positioned at quasiconductor lining
Pseudo-gate dielectric layer 202 at the end 200, it is positioned on pseudo-gate dielectric layer 202 pseudo-grid 204 and is positioned at pseudo-grid and is situated between
Side wall 206 on matter layer 202 and pseudo-grid 204 sidewall, the upper surface of dummy gate 204 is situated between with described interlayer
The upper surface flush of matter layer 208.
In the present embodiment, the material of dummy gate dielectric layer 202 is silicon oxide, forms dummy gate medium
The method of layer 202 is thermal oxidation technology.When the pseudo-grid 204 of follow-up removal, pseudo-gate dielectric layer 202 can
Protect described Semiconductor substrate 200 from damage.
Described side wall 206 can be single layer structure, it is also possible to for laminated construction.The material of side wall 206 can
One or more combinations for silicon nitride, silicon oxynitride or silicon oxide.The material of dummy gate 204 can be
Polysilicon.
The material of described interlayer dielectric layer 208 is silicon oxide, the method forming described interlayer dielectric layer 208
For chemical vapor deposition method, as based on ozone (O3) and tetraethyl orthosilicate (Tetraethyl Orthosilicate,
Referred to as TEOS) sub-aumospheric pressure cvd (Sub-atmospheric Chemical Vapor
Deposition, is called for short SACVD) technique.
With reference to Fig. 7, remove pseudo-grid 204 described in Fig. 6.
In the present embodiment, the method removing dummy gate 204 is wet etching, described wet etching molten
Liquid can be ammonia or tetramethyl hydroxylamine solution.Such as, the tetramethyl that mass percent can be used to be 2.38%
Hydroxylamine solution removes dummy gate 204.
During removing pseudo-grid 204, pseudo-gate dielectric layer 202 can effectively protect half be disposed below
Conductor substrate 200, it is to avoid the channel region of MOS transistor is caused damage by wet-etching technology, improves
The performance of formed MOS transistor.
With reference to Fig. 8, by ammonia (NH4OH), hydrogen peroxide (H2O2) and water (H2O) mixing is molten
Liquid removes pseudo-gate dielectric layer 202 described in Fig. 7, forms groove 210.
In the present embodiment, (Standard Cleaning-1 is called for short the mixed solution of ammonia, hydrogen peroxide and water
For SC1 solution) temperature be 25 DEG C ~ 65 DEG C, ammonia in the mixed solution of ammonia, hydrogen peroxide and water,
The volume ratio of hydrogen peroxide and water is 1: 1 ~ 5:50 ~ 200.Owing to the mixed solution of ammonia, hydrogen peroxide and water is to puppet
The etch rate of gate dielectric layer 202 and interlayer dielectric layer 208 is more or less the same, and due to pseudo-gate dielectric layer 202
Thinner thickness, the time removing pseudo-gate dielectric layer 202 completely is shorter, consumes interlayer dielectric layer 208
Thickness is the most relatively thin, removes pseudo-gate dielectric layer 202 little on the impact of interlayer dielectric layer 208.
With reference to Fig. 9, bottom the most described groove 210, form protective layer 212.
In the present embodiment, the material of described protective layer 212 is silicon oxide.The method forming protective layer 212 is
Wet process oxidation technology, to form the silicon oxide film of thinner thickness, by Semiconductor substrate 200 be subsequently formed
Gate dielectric layer isolation, it is to avoid in gate dielectric layer metallic atom enter MOS transistor channel region, enter
And improve the performance of formed MOS transistor.
Concrete, the solution of described wet process oxidation technology can be ozone (O3) aqueous solution, described ozone
Aqueous solution in the mass concentration of ozone be 30ppm ~ 80ppm, the time of wet process oxidation technology is
30s~180s.I.e. to the water of the ozone that Fig. 8 further groove 210 bottom spray mass concentration is 30ppm ~ 80ppm
Solution 30s ~ 180s, is melted into silicon oxide by Semiconductor substrate 200 Surface Oxygen bottom groove 210, forms protection
Layer 212.
The solution of described wet process oxidation technology can be also temperature be ammonia, hydrogen peroxide and the water of 25 DEG C ~ 65 DEG C
Mixed solution, in the mixed solution of ammonia, hydrogen peroxide and water, the volume ratio of ammonia, hydrogen peroxide and water is
1:1~5:50~200。
The solution of described wet process oxidation technology can be also temperature be sulphuric acid and the hydrogen peroxide of 120 DEG C ~ 180 DEG C
Mixed solution.The mixed solution of sulphuric acid and hydrogen peroxide is i.e. used to carry out dioxysulfate water cleaning (Sulfuric
Peroxide Method, referred to as SPM), form described protective layer 212.Sulphuric acid and the mixing of hydrogen peroxide
In solution, the volume ratio of sulphuric acid and hydrogen peroxide is 2 ~ 5:1, and the time of wet process oxidation technology is 30s ~ 300s.
With continued reference to Fig. 9, described protective layer 212 forms gate dielectric layer 214.
In the present embodiment, the material of described gate dielectric layer 214 is high-g value, as hafnium oxide, zirconium oxide,
Lanthana, aluminium oxide, titanium oxide, strontium titanates, aluminium oxide lanthanum, yittrium oxide, nitrogen hafnium oxide, nitrogen aoxidize
Zirconium, nitrogen lanthana, aluminum oxynitride, titanium oxynitrides, nitrogen strontium oxide titanium, nitrogen lanthana aluminum, yttrium oxynitride
In one or more.Forming the method for described gate dielectric layer 214 is chemical vapor deposition method or former
Sublayer depositing operation.In other embodiments, described gate dielectric layer 214 can also be other high-g value.
With continued reference to Fig. 9, described gate dielectric layer 214 and interlayer dielectric layer 208 form metal material
216a。
In the present embodiment, the material of described metal material 216a can be aluminum or tungsten, forms described metal material
The method of material 216a can be physical gas-phase deposition.
With reference to Figure 10, metal material 216a described in Fig. 9 is carried out flatening process, described to exposing
Interlayer dielectric layer 208, forms grid 216b.
In the present embodiment, described flatening process can be chemical mechanical milling tech.
Although it should be noted that when removing pseudo-gate dielectric layer 202, the interlayer of segment thickness can be removed
Dielectric layer 208, but shorter owing to removing the time of pseudo-gate dielectric layer 202, remove interlayer dielectric layer 208
Thinner thickness, when carrying out flatening process, the metal material 216a energy being positioned on interlayer dielectric layer 208
Enough it is completely removed, interlayer dielectric layer 208 can be prevented effectively from and covered by metal material 216a, be formed
The better performances of MOS transistor, yield rate are high.
With reference to Figure 11, being 65 DEG C for using temperature, the volume ratio of ammonia, hydrogen peroxide and water is 1:2:100
Mixed solution when removing the silicon oxide formed by thermal oxidation technology, removal time and gone silicon
The graph of a relation of thickness.As shown in Figure 11, when the removal time is 5 minutes, 10 minutes and 15 minutes,
The thickness of gone silicon is 4.3 angstroms, 6.2 angstroms and 9.0 angstroms, removal time and gone silicon
Thickness approximation meets Figure 11 cathetus 301, and the slope of straight line 301 is 0.472, i.e. the removal speed of silicon oxide
Rate be 0.472 angstrom per minute.
With reference to Figure 12, being 65 DEG C for using temperature, the volume ratio of ammonia, hydrogen peroxide and water is 1:2:100
Mixed solution remove sub-aumospheric pressure cvd technique based on ozone and tetraethyl orthosilicate formed oxygen
During SiClx, remove the graph of a relation of time and removed silicon oxide thickness.As shown in Figure 12, when the time of removal
Be 5 minutes, 10 minutes, 15 minutes time, the thickness removing silicon is 5.37 angstroms, 10.50 angstroms and 17.68
Angstrom, the removal time meets Figure 12 cathetus 303 with the thickness approximation of gone silicon, straight line 303
Slope is 1.231, i.e. the removal rate of silicon oxide be 1.231 angstroms per minute.
From Figure 11 and Figure 12, thermal oxidation technology is formed by the mixed solution of ammonia, hydrogen peroxide and water
Silicon oxide removal rate and the removal rate to the silicon oxide that sub-aumospheric pressure cvd technique is formed
Ratio is 1:2.6, and it is much larger than 1:13.Therefore, puppet is removed by the mixed solution of ammonia, hydrogen peroxide and water
During gate dielectric layer 202, the impact on interlayer dielectric layer 208 is less, and then will not be at interlayer dielectric layer 208
Top kish material 216a, it is to avoid residue in 216a pair, metal material above interlayer dielectric layer 208
The performance of formed MOS transistor impacts, and improves performance and the yield rate of MOS transistor.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (15)
1. a forming method for MOS transistor, including:
Semiconductor substrate is provided；
Form pseudo-grid structure on the semiconductor substrate, and in the Semiconductor substrate of pseudo-grid structure both sides
Forming interlayer dielectric layer, dummy gate structure includes the pseudo-gate dielectric layer being positioned in Semiconductor substrate and is positioned at
Pseudo-grid on pseudo-gate dielectric layer, the upper surface of dummy gate and the upper surface flush of described interlayer dielectric layer；
Remove dummy gate；
It is characterized in that, also include:
Remove dummy gate dielectric layer by the mixed solution of ammonia, hydrogen peroxide and water, form groove；
Grid structure, the upper surface of described grid structure and described interlayer dielectric layer is formed in described groove
Upper surface flush.
2. the forming method of MOS transistor as claimed in claim 1, it is characterised in that described ammonia,
The temperature of the mixed solution of hydrogen peroxide and water is 25 DEG C～65 DEG C, the volume ratio of ammonia, hydrogen peroxide and water
For 1:1～5:50～200.
3. the forming method of MOS transistor as claimed in claim 1, it is characterised in that form described puppet
The method of gate dielectric layer is thermal oxidation technology.
4. the forming method of MOS transistor as claimed in claim 1, it is characterised in that form described layer
Between the method for dielectric layer be chemical vapor deposition method.
5. the forming method of MOS transistor as claimed in claim 1, it is characterised in that dummy gate
Material is polysilicon, and the method removing dummy gate is wet etching.
6. the forming method of MOS transistor as claimed in claim 5, it is characterised in that described wet method is carved
The solution of erosion is ammonia or tetramethyl hydroxylamine solution.
7. the forming method of MOS transistor as claimed in claim 1, it is characterised in that at described groove
Before interior formation grid structure, also include: form protective layer in the bottom of described groove.
8. the forming method of MOS transistor as claimed in claim 7, it is characterised in that described protective layer
Material be silicon oxide.
9. the forming method of MOS transistor as claimed in claim 8, it is characterised in that at described groove
Bottom formed protective layer method be wet process oxidation technology.
10. the forming method of MOS transistor as claimed in claim 9, it is characterised in that described wet method oxygen
The solution of metallization processes is the aqueous solution of ozone.
The forming method of 11. MOS transistors as claimed in claim 10, it is characterised in that described ozone
In aqueous solution, the mass concentration of ozone is 30ppm～80ppm, and the time of wet process oxidation technology is
30s～180s.
The forming method of 12. MOS transistors as claimed in claim 9, it is characterised in that described wet method oxygen
The solution of metallization processes is the mixed solution of ammonia, hydrogen peroxide and water.
The forming method of 13. MOS transistors as claimed in claim 12, it is characterised in that described ammonia,
The temperature of the mixed solution of hydrogen peroxide and water is 25 DEG C～65 DEG C, the volume ratio of ammonia, hydrogen peroxide and water
For 1:1～5:50～200.
The forming method of 14. MOS transistors as claimed in claim 9, it is characterised in that described wet method oxygen
The solution of metallization processes is the mixed solution of sulphuric acid and hydrogen peroxide.
The forming method of 15. MOS transistors as claimed in claim 14, it is characterised in that described sulphuric acid and
The temperature of the mixed solution of hydrogen peroxide is 120 DEG C～180 DEG C, and the volume ratio of sulphuric acid and hydrogen peroxide is 2～5:1,
The time of wet process oxidation technology is 30s～300s.
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| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN102569164A (en) * | 2010-12-14 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
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| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| CN102569164A (en) * | 2010-12-14 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
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