CN103927219A - Accurate-period simulation model for reconfigurable special processor core and hardware architecture thereof - Google Patents
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Abstract
The invention relates to an accurate-period simulation model for a reconfigurable special processor core on the basis of a SystemC accurate-period model. The accurate-period simulation model comprises a control module, a transmission module and an operation module. The control module sends out configuration parameters and is used for controlling interaction with the exterior of the model and the working conditions of all modules in the model. The transmission module is used for receiving the configuration parameters sent by the control module and used for data transmission outside the special processor core and inside the special processor core. The operation modules are used for receiving the configuration parameters sent by the control module and carrying out operation according to the received configuration parameters and the set algorithm. The accurate-period simulation model has the advantages that a good soft hardware interface is provided on the basis of SystemC language modeling; sequential logic of hardware can be well simulated due to the fact that the model is accurate in period, and the problems can be found fast; compared with other simulation tools and verification platforms, a verification platform of the model is easy to set up, and the simulation velocity is high.
Description
Technical field
The present invention relates to a kind of restructural application specific processor nuclear cycle accurate model, be applicable to the design verification of digital circuit software and hardware system, for emulation and the checking of restructural application specific processor core provide a kind of test emulation verification platform.
Background technology
Along with SoC complexity presents exponential growth, because the design complexities of RTL level is large, the design cycle is long, and the design of software must wait until that hardware design could integration testing after completing, and this can make the cycle of whole design become very long.But SoC system becomes increasingly complex, the duration is increased, Time To Market is shorter and shorter, and traditional RTL level design can not meet the demand of design, and forcing devisers to seek a kind of new method for designing is ESL (Department of Electronics's irrespective of size) design.In ESL design, description and the simulation velocity of SoC system are fast, are the qualities that design engineer can analyze SoC system architecture rapidly.On the one hand, function execution environment correct and cycle accurate makes to develop software in advance and becomes possibility, has shortened the integrated time of software and hardware; On the other hand, system is combining with checking flow process of morning more, can determine the correctness of engineering development product.
SystemC is a kind of Hardware/Software Collaborative Design language, a kind of system-level modeling language.SystemC on C++ basis, has expanded hardware classes and simulated core forms, owing to combining Object-Oriented Design programming and hardware modeling mechanism principle two aspects, so this makes SystemC the different levels on abstraction hierarchy to carry out system.Hardware can be described by SystemC class, and its elementary cell is module, in module, can comprise submodule, port or process, is connected and communicates by letter between module by port with signal.Transaction-level modeling, as the core of ESL design, separates calculation function and communication function, and the communication between module realizes by function call, has reduced the processing of event and information.Communication mechanism (as bus or FIFO) is modeled as channel, and presents to module with the form of SystemC interface class.And can provide corresponding design schedule according to concrete requirements, event.Transaction-level is modeled on abstraction hierarchy and describes SoC system, can be divided into three kinds of models, that is: the model of non-timed, approximate model, cycle accurate model of cycle.
Summary of the invention
The object of the invention is to overcome the deficiency of above prior art, and a kind of accurate realistic model of cycle and hardware structure thereof with good interface between software and hardware, efficient restructural application specific processor core is provided, and is specifically realized by following technical scheme:
The accurate realistic model of cycle of described restructural application specific processor core, based on SystemC cycle accurate model, comprises
Control module, sends configuration parameter, for controlling the duty of the each module inner with the mutual and model of described model outside;
Transport module, receives the configuration parameter that described control module is sent, for the data transmission of application specific processor core outside and application specific processor core inside;
Computing module, receives the configuration parameter that described control module is sent, for carrying out computing according to the selected algorithm of setting described in the configuration parameter receiving.
The further design of the accurate realistic model of cycle of described restructural application specific processor core is, between described control module, transport module and computing module, simulate the signal communication between modules port by function call, realize module communication connection between any two, and by add the register unblock assignment in time sequence information analog and digital circuit in described function, set up streamline, obtain computing input data and computing output data cycle accurate model on the waveform of emulation.
The further design of the accurate realistic model of cycle of described restructural application specific processor core is that described control module comprises
Dispensing unit, completes configuration, the start-up operation to control module according to the register arranging in dispensing unit;
Interruption, exception processing unit, comprise and interrupt processing unit and exception processing unit, receives look-at-me and the abnormal signal of control module and computing module, for realizing, interruptions at different levels are processed respectively, and the abnormal processing of computing module;
Status poll unit, for the inquiry to each module status, to determine the subsequent operation of respective modules.
The further design of the accurate realistic model of cycle of described restructural application specific processor core is, described computing module is made up of several operator unit, the modeling of the corresponding a kind of algorithm of each arithmetic element.
According to the accurate realistic model of cycle of described restructural application specific processor core, a kind of hardware structure of accurate realistic model of cycle of restructural application specific processor core is provided, described hardware structure comprises reconfigureable computing array unit, master controller, configuration register, reconfigurable controller, memory access switching network, storer, DMA unit and bus interface, described reconfigurable controller, configuration register, DMA interface and bus interface communicate to connect with master controller respectively, described reconfigurable controller, configuration register forms described control module with master controller communication connection respectively, restructural application specific processor core is connected to form described computing module by memory access switching network and memory communication, described transport module comprises described DMA unit and bus interface, described DMA unit and master controller communication connection, described bus interface is connected to form data channel by described DMA unit and memory communication, and described bus interface communicates to connect formation control passage with described configuration register and master controller respectively.
The further design of the hardware structure of the accurate realistic model of cycle of described restructural application specific processor core is, described bus interface is AXI interface.
Advantage of the present invention is as follows:
(1), the present invention is based on SystemC Language Modeling, therefore, there is good interface between software and hardware;
(2), the present invention is cycle accurate model, therefore, can well simulate the sequential logic of hardware, to pinpoint the problems fast;
(3), compare other emulation tool (VCS), verification platform (FPGA), the verification platform of this model is built simply, simulation velocity is fast.
Brief description of the drawings
Fig. 1 is the hardware structure figure of restructural application specific processor core.
Fig. 2 is that restructural application specific processor and cycle accurate model are simplified Organization Chart.
Fig. 3 is master controller configuration module interface.
Fig. 4 is interruption processing module interface.
Fig. 5 is abnormality processing module interface.
Fig. 6 is status poll module interface.
Fig. 7 is DMA data transmission module interface.
Fig. 8 is different simulation and verification platform performance comparison diagrams.
Embodiment
Below in conjunction with accompanying drawing, the present invention program is elaborated.
The accurate realistic model of cycle of the restructural application specific processor core that the present embodiment provides, based on SystemC cycle accurate model, comprises control module, transport module and computing module.Control module, sends configuration parameter, for controlling the duty of the each module inner with the mutual and model of described model outside.Transport module, receives the configuration parameter that described control module is sent, for the data transmission of application specific processor core outside and application specific processor core inside.Computing module, receives the configuration parameter that described control module is sent, for carrying out computing according to the selected algorithm of setting described in the configuration parameter receiving.
Further, between control module, transport module and computing module, simulate the signal communication between modules port by function call, realize module communication connection between any two, and by add the register unblock assignment in time sequence information analog and digital circuit in function, and then set up streamline, obtain computing input data and computing output data cycle accurate model on the waveform of emulation.
Wherein, control module is mainly made up of dispensing unit, interruption, exception processing unit, signal and abnormal signal and status poll unit.The dispensing unit of the present embodiment, completes configuration, the start-up operation to control module according to the register arranging in dispensing unit.The IO interface of dispensing unit comprises restructural application specific processor core mode of operation (main equipment, from equipment), configuration register start address Reg_Addr, and computing module is selected Module_Sel, referring to Fig. 3.
The interruption of the present embodiment, exception processing unit, comprise and interrupt processing unit and exception processing unit, referring to Fig. 4, Fig. 5, receive look-at-me and the abnormal signal of control module and computing module, for realizing, interruptions at different levels are processed respectively, and the abnormal processing of computing module.
The status poll unit of the present embodiment, for the inquiry of external unit to each module status in this model such as external data signal processors (DSP), to determine the subsequent operation of respective modules, referring to Fig. 6.
The computing module of the present embodiment is made up of 17 operator unit, the modeling of the corresponding a kind of algorithm of each arithmetic element.Comprising FFT/IFFT computing, vectorial auto-correlation, simple crosscorrelation, plus-minus method, multiplication, matrix inversion, plus-minus method, multiplication, dot product, covariance, real/complex FIR, real/complex Doppler, fixed floating conversion and plural number are asked the computings such as mould.Computing module, according to the configuration parameter of control module, is realized the computing of special algorithm, and this module is the major part of whole system modeling, is also the core of chip.
According to the accurate realistic model of cycle of above-mentioned restructural application specific processor core, provide a kind of hardware structure of accurate realistic model of cycle of restructural application specific processor core.This hardware structure is mainly made up of reconfigureable computing array unit, master controller, configuration register, reconfigurable controller, memory access switching network, storer, DMA unit and bus interface.
Wherein, reconfigurable controller, configuration register, DMA interface and bus interface communicate to connect with master controller respectively, and reconfigurable controller, configuration register form above-mentioned control module with master controller communication connection respectively.
Restructural application specific processor core is connected to form above-mentioned computing module by memory access switching network and memory communication.
Transport module is mainly made up of DMA unit and bus interface, DMA unit and master controller communication connection.Bus interface is connected to form data channel by DMA unit and memory communication, and bus interface communicates to connect formation control passage with configuration register and master controller respectively.The bus interface that the present embodiment adopts is AXI interface.
The present invention is based on SystemC cycle accurate model, and therefore, this model and RTL level also have basically identical property of cycle.This model comprises control module, transport module, budget module.Use system-level language to encapsulate on abstraction hierarchy, and communicate by letter with extraneous by port, between module, pass through signal exchange data.Signal is data capsule, in the time that data change, and generation event, driving simulation device.Signal has been set up the direct connection of intermodule.And port can be regarded " signal pointer " as, port and a signal are associated together.SystemC signal and port support postpone assignment, by the behavior of a Δ delay modeling hardware signal.It is minimum emulation step that Δ postpones.Simulated core is supported the Δ cycle, and Δ periodic packets has contained many valuations and cenotype more.A simulation time has multiple Δ cycles.In the time of event call function notify (), will in the Δ event queue of simulated environment, insert this event.Send update request with request (), in the time upgrading, call updata () update signal.
The read-write of SystemC middle port and signal postpones to realize based on Δ just.The write method providing in the sequential logical circuit that triggered by clock just carries out the renewal of data to it in the time that timeslice finishes.So the port and the signal that read in this cycle are the data in last cycle, and the data that this cycle upgrades will arrive the next cycle and just can read.This attribute of port and signal just with one of important difference of higher level lanquage general data type.So, utilize this feature just can realize the model such as register, storer on hardware, the register unblock assignment that can be used in analog and digital circuit.
In the present invention, adopt unblock assignment to postpone to realize the flowing water transition of Time Created.Usually, in digital circuit, totalizer, multiplier and divider etc. all can not complete computing in one-period, and in design likely the combination of demand totalizer and multiplier composition multiply accumulating rise etc.These are in Design of Digital Circuit, and often the mode of flowing water designs, and can be that design reaches less time requirement like this.And with respect to higher level lanquage, plus-minus method, multiplication and division are all to complete computing in one-period.In the sequential logical circuit that triggered by clock, the realization of a streamline need to, through the flowing water Time Created of one period, could realize the output that each cycle can complete an operational data.So, the data needs of inputting within this cycle, the data that need to export through N all after date be only the result of this computing.In the present invention, implementation method is that the data input delay that utilizes unblock assignment to realize N cycle carrys out analog stream waterline.So, utilize this feature just can on the waveform of emulation, computing input data and computing output data cycle accurate model, and can realize the foundation of streamline.
The present invention is in order to make the model cycle more accurate, in the proof procedure after design finishes, and the not only correctness in verification model function, simultaneous verification model sequential, correctness on the cycle.And by artificial correction, the cycle of implementation model is accurate as much as possible.Due in design process of hardware, in later stage bug debugging, tend to have influence on the periodicity of hardware design, but in model, not necessarily have this bug especially, so, just need to be by increasing artificially the consistance that postpones to meet periodicity.
What the present invention realized is a kind of restructural application specific processor nuclear cycle accurate model, and its object is to realize the emulation of restructural application specific processor core.As Fig. 8, higher level lanquage has obvious advantage on simulation velocity, rapidly the place of orientation problem.And building of its simulated environment is also fairly simple, can carry out at any time emulation testing.
Claims (6)
1. accurate realistic model of the cycle of restructural application specific processor core, based on SystemC cycle accurate model, is characterized in that comprising
Control module, sends configuration parameter, for controlling the duty of the each module inner with the mutual and model of described model outside;
Transport module, receives the configuration parameter that described control module is sent, for the data transmission of application specific processor core outside and application specific processor core inside;
Computing module, receives the configuration parameter that described control module is sent, for carrying out computing according to the selected algorithm of setting described in the configuration parameter receiving.
2. the accurate realistic model of cycle of restructural application specific processor core according to claim 1, it is characterized in that simulating the signal communication between modules port by function call between described control module, transport module and computing module, realize module communication connection between any two, and by add the register unblock assignment in time sequence information analog and digital circuit in described function, set up streamline, obtain computing input data and computing output data cycle accurate model on the waveform of emulation.
3. the accurate realistic model of cycle of restructural application specific processor core according to claim 2, is characterized in that described control module comprises
Dispensing unit, completes configuration, the start-up operation to control module according to the register arranging in dispensing unit;
Interruption, exception processing unit, comprise and interrupt processing unit and exception processing unit, receives look-at-me and the abnormal signal of control module and computing module, for realizing, interruptions at different levels are processed respectively, and the abnormal processing of computing module;
Status poll unit, for the inquiry to each module status, to determine the subsequent operation of respective modules.
4. the accurate realistic model of cycle of restructural application specific processor core according to claim 1, is characterized in that described computing module is made up of several operator unit, the modeling of the corresponding a kind of algorithm of each arithmetic element.
5. according to the accurate realistic model of cycle of the restructural application specific processor core described in any one of claim 1-4, a kind of hardware structure of accurate realistic model of cycle of restructural application specific processor core is provided, it is characterized in that described hardware structure comprises reconfigureable computing array unit, master controller, configuration register, reconfigurable controller, memory access switching network, storer, DMA unit and bus interface, described reconfigurable controller, configuration register, DMA interface and bus interface communicate to connect with master controller respectively, described reconfigurable controller, configuration register forms described control module with master controller communication connection respectively, restructural application specific processor core is connected to form described computing module by memory access switching network and memory communication, described transport module comprises described DMA unit and bus interface, described DMA unit and master controller communication connection, described bus interface is connected to form data channel by described DMA unit and memory communication, and described bus interface communicates to connect formation control passage with described configuration register and master controller respectively.
6. the hardware structure of the accurate realistic model of cycle of restructural application specific processor core according to claim 1, is characterized in that described bus interface is AXI interface.
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Application publication date: 20140716 |