CN103915433A - Radiation resistant SCR electrostatic protection device with annular grid MOSFET embedded - Google Patents
Radiation resistant SCR electrostatic protection device with annular grid MOSFET embedded Download PDFInfo
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- CN103915433A CN103915433A CN201410120973.9A CN201410120973A CN103915433A CN 103915433 A CN103915433 A CN 103915433A CN 201410120973 A CN201410120973 A CN 201410120973A CN 103915433 A CN103915433 A CN 103915433A
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Abstract
The invention discloses a radiation resistant SCR electrostatic protection device with an annular grid MOSFET embedded. The annular grid MOSFET embedded in the radiation resistant SCR electrostatic protection device can be applied to SCR electrostatic protection devices of six different structures. The six SCR electrostatic protection device structures are achieved by embedding an annular grid NMOS and an annular grid PMOS, and by embedding an annular grid MOSFET respectively and adding a P-type well region and an N-type well region at the same time. The embedding of the annular grids is equivalent to embedding of a grid-grounded NMOS structure or a grid-joint high potential PMOS structure, the trigger voltage of the annular grids is close to that of the grid-grounded NMOS structure or that of the grid-joint high potential PMOS structure, the trigger voltage is lowered, and starting speed is improved. The annular grid structure is adopted, the distance between a cathode and an anode is enlarged, electric leakage closed circuits on the edge of an NMOS component are blocked, and therefore the voltage maintaining capacity and the radiation resistant capacity of SCR components are improved.
Description
Technical field
The invention belongs to field of semiconductor devices, relate in particular to a kind of thyristor electrostatic protection structure design that is embedded with ring-shaped gate mos field effect transistor.
Background technology
Along with the fast development of semiconductor integrated circuit, electrostatic protection device is widely used in the electronic product in the fields such as Radiation Sterilization of Medical Products sterilization, space flight and aviation, space science detection, radiation chemical engineering and nuclear industry, electronic equipment.Static discharge is as a kind of common near field electromagnetic harm source, its electromagnetic energy produces transient state induced voltage or pulse current by the mode of radiation or conduction in circuit, the normal work of interfered circuit and device, the quality and reliability of electronic product, electronic equipment is reduced, even cause Important Project accident, make the whole world all suffer every year huge economic loss, also once caused massive losses and the disaster of numerous aerospace engineering projects.Static discharge is also thereupon more and more obvious on the impact of integrated circuit, approximately has according to statistics 37% chip failure because Electrostatic Discharge/overvoltage power (EOS) causes.But the suffered electrostatic discharge damage of electronic product has 90% to belong to stealthy damage, is difficult to directly occur by detection, only carries out electrostatic defending, just can reduce the harm that static discharge produces device, guarantee end product quality.On the other hand, electronic product is subject to the caused radiation effect of radiation and tends to make its life-span reduce or break down, and when serious, even directly causes the damage of electronic product, thereby whole electronic equipment lost efficacy.
In order to overcome the harm of static discharge, the ESD device of various new structures arises at the historic moment, as grid grounded metal oxide semiconductor field effect transistor (GGMOS), diode structure, reliability and yield that the structures such as thyristor (SCR) are electronic product escort.For guaranteeing the work of semiconductor integrated circuit energy stability and safety in radiation environment, must take various technical measures to reduce the impact of irradiation on semiconductor device.Silicon on sapphire (SOS) and silicon-on-insulator (SOI) at the most effective material aspect anti-irradiation, also can use GaAs (GaAs), gallium nitride (GaN) etc. to have the new material of stronger anti-radiation performance, single crystal silicon material can be by increasing shading ring between PMOS and nmos pass transistor, device adopts the methods such as annular grid structure, can improve to a certain extent the anti-radiation performance of integrated circuit.Improve Radiation hardness by domain reinforcement technique, as be increased in the distance between N+ diffusion on the diffusion of P+ in trap and substrate, the contact hole of increase trap as much as possible and substrate, block device edge current leakage path, uses the modes such as ring-shaped gate to strengthen the anti-radiation performance of ESD device.Improve on the other hand process conditions, reduce gate oxide thickness, adopt Vacuum Package, coating radioresistance coating to carry out radiation hardening.The SCR device architecture of capel shape gate metal oxide semiconductor field effect transistor of the present invention (MOSFET), with reference to above radiation hardened method, adopts and embeds ring-shaped gate MOS structure, realizes improving maintaining voltage and strengthening anti-radiation performance requirement.
Be illustrated in figure 1 the domain schematic diagram of traditional SCR electrostatic protection device, this structure has the advantages that area is little, antistatic capacity is strong, processing compatibility is good, but the defect that trigger voltage is high, opening speed is slow that is limited to this structure needs to carry out corresponding improvement in actual applications.Existing SCR improves the mainly boundary at negative electrode and anode and embeds NMOS pipe or PMOS pipe, as shown in Figure 2.Although it is high that the SCR device after improving can solve traditional SCR trigger voltage, the problem that opening speed is slow, maintains voltage and anti-irradiance problems is not still resolved.For this problem, patent of the present invention is to adopt the effective measures of embedding Gate-all-around MOSFET to improve the anti-radiation performance that maintains voltage, Enhanced SC R electrostatic protection device of SCR device by domain reinforcement technique.
Summary of the invention
The object of the invention is to maintain in order to solve SCR device the problem of voltage and anti-irradiation, SCR is improved, embed Gate-all-around MOSFET structure, making on basis simple, that processing compatibility is good, further reduce SCR device trigger voltage, raising SCR device maintains voltage and prevents latch-up, simultaneously Enhanced SC R device anti-radiation performance.
The Gate-all-around MOSFET embedding can be divided into nmos pass transistor and PMOS transistor, in practical application, grid end and the source of the ring-shaped gate NMOS embedding are connected and are connect negative electrode by plain conductor, and grid end and the source of the ring-shaped gate PMOS of embedding are connected and connect anode by plain conductor.The Gate-all-around MOSFET that the present invention embeds can be used for the SCR electrostatic protection device of following 6 kinds of different structures.
The domain schematic diagram of structure one, as shown in Figure 5, on traditional SCR architecture basics, embed NMOS pipe at negative electrode 1-1 and anode 1-2 boundary, the drain terminal N+ injection region 1-9 of ring-shaped gate NMOS pipe is placed on the interface of negative electrode 1-1 and anode 1-2, ring-shaped gate end 1-10,1-5JiP+ injection region, source N+ injection region 1-6 connect the negative electrode 1-1 that receives SCR by plain conductor, 1-3HeP+ injection region, N+ injection region 1-4 is connected and received anode 1-2 by plain conductor.N+ injects 1-3 district and P+ injection region 1-4, and 1-5HeP+ injection region, N+ injection region 1-6 both can be in contact with one another, and also can have certain distance.1-8 shown in Fig. 5 is P type light dope substrate.
The domain schematic diagram of structure two, as shown in Figure 6, on the basis of structure one, the ring-shaped gate NMOS pipe that Fig. 3 is embedded is changed into and is embedded ring-shaped gate PMOS pipe.Be the drain terminal P type heavy doping injection region 2-9 that drain terminal N-type heavy doping injection region 1-9 that Fig. 5 is placed in the NMOS pipe of negative electrode 1-1 and anode 1-2 boundary changes into the pipe of PMOS shown in Fig. 6, different from structure one is, ring-shaped gate end 2-10, the source P+ injection region 2-4 of PMOS are connected and are received the anode 2-2 of SCR together with the 2-3 of P+ injection region by plain conductor, and 2-5HeP+ injection region, N+ injection region 2-6 is connected to negative electrode 2-1 by plain conductor.2-8 shown in Fig. 6 is P type light dope substrate.
The domain schematic diagram of structure three, as shown in Figure 7, based on structure one, inject higher than the P type ion of P type light dope substrate implantation concentration and form P well region 3-11 lower than P+ in negative electrode dopant implant concentration, embed NMOS pipe at negative electrode 3-1 and anode 3-2 boundary, the drain terminal N+ injection region 3-9 of ring-shaped gate NMOS pipe is placed on the interface of negative electrode 3-1 and anode 3-2, ring-shaped gate end 3-10,3-5JiP+ injection region, source N+ injection region 3-6 connect the negative electrode 3-1 that receives SCR by plain conductor, 3-3HeP+ injection region, N+ injection region 3-4 is connected and received anode 3-2 by plain conductor.Compared with structure one, the avalanche breakdown face of structure three as shown in Figure 5 N+ injection region 1-9-P type substrate 1-8 shifts as N+ injection region 3-9-P well region 3-11 shown in Fig. 7, has further reduced the trigger voltage of SCR device.3-8 shown in Fig. 7 is P type light dope substrate.
The domain schematic diagram of structure four, as shown in Figure 8, based on structure two, inject higher than the P type ion of P type substrate implantation concentration and form P well region 4-11 lower than P+ in negative electrode dopant implant concentration, embed PMOS pipe at negative electrode 4-1 and anode 4-2 boundary, the drain terminal P+ injection region 4-9 of ring-shaped gate PMOS pipe is placed on the interface of negative electrode 4-1 and anode 4-2, ring-shaped gate end 4-10,4-4JiN+ injection region, source P+ injection region 4-3 connect the anode 4-2 that receives SCR by plain conductor, 4-5HeP+ injection region, N+ injection region 4-6 is connected and received negative electrode 4-1 by plain conductor.Compared with structure two, the R2 doping content of structure four increases resistance and reduces, and maintains voltage and decreases compared with structure two.4-8 shown in Fig. 8 is P type light dope substrate.
Shown in structure five Fig. 9, on the basis of structure three, negative electrode and anode have all been made in N-type light dope deep-well region 5-12, this structure can be made high pressure NMOS tubular construction by the NMOS pipe of embedding, also can increase as improvement such as lightly doped drain level LDD.
Structure six as shown in figure 10, on the basis of structure four, has all been made in negative electrode and anode in N-type light dope deep-well region 6-12, and this structure can be made high voltage PMOS tubular construction by the PMOS pipe of embedding.
The feature of the Gate-all-around MOSFET structure embedding in the present invention is that the grid of metal-oxide-semiconductor surround drain terminal along the edge of active area, source and drain terminal are in strip, grid end circularizes, the source of metal-oxide-semiconductor and drain terminal consistent size, the drain terminal of metal-oxide-semiconductor is placed in to the boundary of SCR device cathodes and anode, can changes flexibly size and the wide long size of embedding MOSFET that negative electrode and anode P injection or N inject according to the difference of designing requirement.
In the present invention, the SCR electrostatic protection device of embedding Gate-all-around MOSFET can be made symmetrical structure and unsymmetric structure, also can make and refer to that structure is to obtain larger current drain ability more.
Accompanying drawing explanation
Fig. 1 is the domain schematic diagram of traditional SCR electrostatic protection device.
Fig. 2 is the SCR electrostatic protection device domain schematic diagram of existing embedding NMOS pipe.
Fig. 3 is the SCR electrostatic protection device profile of Fig. 2 embedding NMOS pipe.
Fig. 4 is the SCR electrostatic protection device equivalent schematic diagram of Fig. 2 embedding NMOS pipe.
Fig. 5 is the domain schematic diagram of the SCR electrostatic protection device structure one of capel grid NMOS pipe of the present invention.
Fig. 6 is the domain schematic diagram of the SCR electrostatic protection device structure two of capel grid PMOS pipe of the present invention.
Fig. 7 is the domain schematic diagram of the SCR electrostatic protection device structure three of capel grid NMOS pipe of the present invention.
Fig. 8 is the domain schematic diagram of the SCR electrostatic protection device structure four of capel grid PMOS pipe of the present invention.
Fig. 9 is the domain schematic diagram of the SCR electrostatic protection device structure five of capel grid NMOS pipe of the present invention.
Figure 10 is the domain schematic diagram of the SCR electrostatic protection device structure six of capel grid NMOS pipe of the present invention.
Embodiment
For more well-known elaboration design feature of the present invention, below in conjunction with accompanying drawing, the present invention is described in further detail.
Fig. 3 is the profile corresponding to SCR electrostatic protection device of Fig. 2 structure embedding NMOS pipe, and Fig. 4 is the corresponding equivalent circuit diagram of Fig. 2 structure.Comprise a parasitic PNP triode Q1(by P type heavily doped region 8, N-type well region 9 and P type substrate 10 form), a parasitic NPN triode Q2(is by N-type heavily doped region 7, P type substrate 10 and N-type well region 9 form), a parasitic gate grounding NMOS pipe M1(is by N-type heavily doped region 6, N-type heavily doped region 7, N-type well region 9, P type heavily doped region 8 and polysilicon gate 3 form), a parasitic diode D1(is made up of N-type heavily doped region 6 and P type substrate 10) and the dead resistance R2 that forms of the dead resistance R1 that forms of N trap and P type substrate.When application, anode connects the chip pin that needs electrostatic defending, minus earth, in the time that positive esd pulse appears at anode, electric field maximum appears at the drain terminal of GGNMOS, with respect to the low-doped PN junction of N trap and the formation of P trap, can first there is avalanche breakdown in parasitic diode D1, GGNMOS is conducting first, the electronic current producing flows through N trap, make Q1, the positive feedback path of Q2 composition is opened, thereby release fast and effectively ESD electric current, as can be seen from Figure 4, negative electrode is to the resistance size of dead resistance R1 and the R2 of anode, the voltage that maintains of SCR device will be affected, the doping content of back biased diode D1 will determine the height of SCR device trigger voltage.
Structure one as shown in Figure 5, comprising: negative electrode 1-1 and anode 1-2 that grid end 1-10, the source N+ injection region 1-5 of embedding MOSFET, drain terminal N+ injection region 1-9, N+ injection region 1-3, P+ injection region 1-4, P+ injection region 1-6, N well region 1-7, P type light dope substrate 1-8 form.1-3HeP+ injection region, N+ injection region 1-4,1-5HeP+ injection region, source N+ injection region 1-6 both can be in contact with one another, and also can have certain distance.1-3HeP+ injection region, N+ injection region 1-4 connects the anode 1-2 that receives SCR by plain conductor; Grid end 1-10,1-5HeP+ injection region, source N+ injection region 1-6 are connected to the negative electrode 1-1 of SCR by plain conductor.When application, the anode of SCR electrostatic protection device is received on the pin that needs electrostatic defending chip, and negative electrode is received earth potential.The design feature of introducing embedding ring-shaped gate NMOS pipe shows: grid end is end to end, there is not the edge of grid width direction, the source of having eliminated leak between leak channel between two PN junctions, can effectively suppress the degeneration of the leakage current performance that irradiation causes, improve anti-radiation performance; The embedding of ring-shaped gate NMOS structure, makes negative electrode 1-1 increase to the distance between anode 1-2, and R2 resistance increases, and therefore the voltage that maintains of SCR device be also further enhanced, and effectively prevented the generation of SCR device latch-up.
Structure two as shown in Figure 6, on the basis of structure shown in Fig. 5, the NMOS pipe of embedding is changed into PMOS pipe, be the source P+ injection region 2-9 that the N+ of source shown in Fig. 5 injection region 1-9 changes into PMOS pipe, avalanche breakdown face is also the injection region 2-9 of source P+ shown in Fig. 6 and N-type well region 2-7 by source N+ injection region 1-9 and the P type light dope substrate 1-8 transfer of Fig. 5, and corresponding change also occurs trigger voltage.
Structure three as shown in Figure 7, on the basis of structure shown in Fig. 5, negative electrode increases P type well region 3-11, it is the injection region 3-9 of source N+ shown in Fig. 7 and the doping content P type well region 3-11 higher than P type light dope substrate that avalanche breakdown face is also shifted by the source N+ injection region 1-9 of Fig. 5 and P type light dope substrate 1-8, and trigger voltage further reduces.Its design feature is consistent with structure one.
Structure four as shown in Figure 8, on the basis of structure shown in Fig. 6, negative electrode increases P type well region 4-11.Increase after P type well region 4-11, the doping content of dead resistance R2 increases, and resistance reduces, and maintains voltage and decreases compared with structure two.
Structure five as shown in Figure 9, on the basis of structure shown in Fig. 7, negative electrode and anode have all been made in N-type light dope deep trap 5-12, this structure is mainly used in embedding the SCR device of high pressure annular coral NMOS, simultaneously, N-type light dope deep trap 5-12 separates P trap 5-11 and P type light dope substrate 5-8, has reduced the substrate noise of SCR device.
Structure six as shown in figure 10, on the basis of structure shown in Fig. 8, has all been made in negative electrode and anode in N-type light dope deep trap 6-12, and its design feature and structure cause May Day.
The execution mode that the present invention is routine, processing compatibility is good, and standard CMOS process, BiCMOS technique, BCD technique, SIO technique platform all can be realized.
Claims (2)
1. one kind is embedded with the anti-irradiation SCR electrostatic protection device of Gate-all-around MOSFET, comprise: MOSFET and SCR, it is characterized in that: described MOSFET is Gate-all-around MOSFET, wherein the source of ring-shaped gate NMOS pipe and grid end are connected to the negative electrode of SCR by plain conductor; The source of ring-shaped gate PMOS pipe and grid end are connected to the anode of SCR by plain conductor.
2. a kind of anti-irradiation SCR electrostatic protection device that is embedded with Gate-all-around MOSFET according to claim 1, is characterized in that: described Gate-all-around MOSFET is embed ring-shaped gate NMOS, ring-shaped gate PMOS or increase P type well region and the Gate-all-around MOSFET of N-type deep-well region simultaneously.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465666A (en) * | 2014-11-28 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection structure of SOI technology and electrostatic protection circuit formed by the same |
| CN111739887A (en) * | 2020-07-09 | 2020-10-02 | 中国科学院上海微***与信息技术研究所 | Electrostatic protection unit based on thyristor and parallel structure thereof |
| TWI728090B (en) * | 2017-04-06 | 2021-05-21 | 聯華電子股份有限公司 | Semiconductor structure |
| CN116525615A (en) * | 2023-07-03 | 2023-08-01 | 微传智能科技（常州）有限公司 | Method for preventing latch-up |
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| US5465189A (en) * | 1990-03-05 | 1995-11-07 | Texas Instruments Incorporated | Low voltage triggering semiconductor controlled rectifiers |
| CN102208412A (en) * | 2011-05-19 | 2011-10-05 | 电子科技大学 | SCR structure used for ESD protection of integrated circuit output stage |
| CN103268874A (en) * | 2013-04-23 | 2013-08-28 | 中国电子科技集团公司第十一研究所 | Radiation-proof infrared focal plane detector reading circuit |
| CN203883004U (en) * | 2014-03-28 | 2014-10-15 | 中国科学院上海技术物理研究所 | Anti-radiation SCR electrostatic protection device embedded with annular gate MOSFET |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US5465189A (en) * | 1990-03-05 | 1995-11-07 | Texas Instruments Incorporated | Low voltage triggering semiconductor controlled rectifiers |
| CN102208412A (en) * | 2011-05-19 | 2011-10-05 | 电子科技大学 | SCR structure used for ESD protection of integrated circuit output stage |
| CN103268874A (en) * | 2013-04-23 | 2013-08-28 | 中国电子科技集团公司第十一研究所 | Radiation-proof infrared focal plane detector reading circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465666A (en) * | 2014-11-28 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection structure of SOI technology and electrostatic protection circuit formed by the same |
| CN104465666B (en) * | 2014-11-28 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | The electrostatic preventing structure of SOI technology and its electrostatic discharge protective circuit of composition |
| TWI728090B (en) * | 2017-04-06 | 2021-05-21 | 聯華電子股份有限公司 | Semiconductor structure |
| CN111739887A (en) * | 2020-07-09 | 2020-10-02 | 中国科学院上海微***与信息技术研究所 | Electrostatic protection unit based on thyristor and parallel structure thereof |
| CN116525615A (en) * | 2023-07-03 | 2023-08-01 | 微传智能科技（常州）有限公司 | Method for preventing latch-up |
| CN116525615B (en) * | 2023-07-03 | 2023-08-25 | 微传智能科技（常州）有限公司 | Method for preventing latch-up |
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