CN103906305B - Drive circuit and driving method - Google Patents
Drive circuit and driving method Download PDFInfo
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- CN103906305B CN103906305B CN201210587364.5A CN201210587364A CN103906305B CN 103906305 B CN103906305 B CN 103906305B CN 201210587364 A CN201210587364 A CN 201210587364A CN 103906305 B CN103906305 B CN 103906305B
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Abstract
A kind of drive circuit and driving method, this drive circuit includes: a PWM drives module and the 2nd PWM to drive module. Oneth PWM drives module to produce the first square-wave signal according to the first data signal of data stream, in order to drive the first luminescence unit, wherein the first square-wave signal represents the first luminescence unit in the fluorescent lifetime of display cycle, and the rising edge of the first square-wave signal is positioned at the starting point of display cycle. 2nd PWM drives module to produce the second square-wave signal according to the second data signal of data stream, in order to drive the second luminescence unit, wherein the second square-wave signal represents the second luminescence unit in the fluorescent lifetime of display cycle, the trailing edge of the second square-wave signal is positioned at the end point of display cycle, and the rising edge of the second square-wave signal is later than the rising edge of the first square-wave signal. The invention enables the probability of each time point generation electric current in the display cycle comparatively average, it is thus possible to reduce the momentary load caused on the power line when the same unit interval turns at luminescence unit.
Description
Technical field
The present invention is related to a kind of luminescent system, in particular to a kind of drive circuit.
Background technology
Figure 1A is the schematic diagram of a luminescent system. As shown in Figure 1A, luminescent system 100 has drive circuit 110 and light emitting module 120. Drive circuit 110 has n channel and carrys out driven for emitting lights unit ED1 ~ EDn, and each luminescence unit ED1 ~ EDn receives power line Vp in succession.
Figure 1B is the graph of a relation of the online electric current of power supply and time. As shown in Figure 1B, waveform Cv1 represents the electric current of the 1st passage, and waveform Cv2 represents the electric current of the 2nd passage, and waveform Cv3 represents the electric current of the 3rd passage, and waveform Cvn represents the electric current of the n-th passage. Waveform Cvs represents the waveform Cv1 total current to waveform Cvn, is also the electric current on power line Vp.
It is apparent that due to n channel each display cycle DP at the beginning time simultaneously turn on, the electric current on power line Vp was increased sharply to n times of current value of single channel by zero moment, and this measure will result in noise concentrations in display cycle DP at the beginning. Therefore, a kind of drive circuit and driving method are needed badly, by the On current mean allocation on power line Vp to display cycle DP.
Summary of the invention
In view of this, the present invention provides a kind of drive circuit, including: one the oneth PWM drives module, one first data signal according to a data stream produces one first square-wave signal, in order to drive one first luminescence unit, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of above-mentioned display cycle; And one the 2nd PWM drive module, one second data signal according to above-mentioned data stream produces one second square-wave signal, in order to drive one second luminescence unit, wherein above-mentioned second square-wave signal represents above-mentioned second luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal.
The present invention also provides a kind of driving method, it is applicable to drive one first luminescence unit and one second luminescence unit, above-mentioned driving method includes: produce one first square-wave signal according to one first data signal of a data stream, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of a display cycle; Above-mentioned first luminescence unit is driven according to above-mentioned first square-wave signal; One second data signal according to above-mentioned data stream produces one second square-wave signal, wherein above-mentioned second square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal; And drive above-mentioned second luminescence unit according to above-mentioned second square-wave signal.
The invention enables the probability of each time point generation electric current in the display cycle comparatively average, it is thus possible to reduce the momentary load caused on the power line when the same unit interval turns at luminescence unit.
Accompanying drawing explanation
Figure 1A is the schematic diagram of a luminescent system.
Figure 1B is the graph of a relation of the online electric current of power supply and time.
Fig. 2 is a schematic diagram of the drive circuit of the present invention.
Fig. 3 is an embodiment of the driving module of the present invention.
Fig. 4 is the graph of a relation of the online electric current of power supply and time.
Fig. 5 is the electric current and the graph of a relation of time that power supply is online according to another embodiment of the present invention.
Fig. 6 is the electric current and the graph of a relation of time that power supply is online according to another embodiment of the present invention.
Fig. 7 is electric current Probability Distribution figure.
Fig. 8 is a schematic diagram of the drive circuit of the present invention.
Fig. 9 is a flow chart of the driving method of the luminescence unit of the present invention.
Being simply described as follows of symbol in accompanying drawing:
100: luminescent system; Id: electric current; 110,210,310,810: drive circuit; 120,220,320,820: light emitting module; DM1 ~ DMn: drive module; ED1 ~ EDn: luminescence unit; Vp: power line; 330,830:PWM generation unit; 331,831: enumerator; 332,832: comparator; 340,840: driver element; DP: display cycle; 833:PWM buffer; 850: buffer unit; Sct: count signal; Sdt: data signal; Ssq: square-wave signal; CLK: clock signal; DL: data wire; Cv1, Cv2, Cvs, Cv2 ', Cvs ': waveform; Cp1, Cp2, Cps, Cp2 ', Cps ': waveform.
Detailed description of the invention
For making above and other objects of the present invention, feature and advantage to become apparent, cited below particularly go out preferred embodiment, and coordinate institute's accompanying drawings, be described in detail below.
Following description is carried out description of the presently preferred embodiments. Those skilled in the art should be able to know without departing under the spirit of the present invention and the premise of framework, when doing a little change, replacement and displacement. Scope of the invention is when depending on appended claim.
Fig. 2 is a schematic diagram of the drive circuit of the present invention. As shown in Figure 2, drive circuit 210 includes multiple PWM and drives module DM1 ~ DMn, in order to the multiple luminescence unit ED1 ~ EDn in driven for emitting lights module 220 respectively, wherein luminescence unit ED1 ~ EDn coupled in parallel, and each luminescence unit ED1 ~ EDn has the first end and is coupled to a power line Vp and the second end is coupled to corresponding PWM and drives module DM1 ~ DMn.According to another embodiment of the present invention, the multiple luminescence unit ED1 ~ EDn in light emitting module 220 can be coupled to corresponding PWM driving module DM1 ~ DMn by above-mentioned first end, and the second end is coupled to earth terminal.
Fig. 3 is an embodiment of the driving module of the present invention. PWM drives module 330 to determine the luminescence unit ED1 ~ EDn fluorescent lifetime in a display cycle of light emitting module 320 according to data signal Sdt. Luminescence unit ED1 ~ EDn coupled in parallel luminescence unit ED1 ~ EDn can be light emitting diode (lightemittingdiode, LED). Specifically, as it is shown on figure 3, each PWM drives module DM1 ~ DMn at least to include pulse width modulation (Pulse-widthmodulation, PWM) generation unit 330 (hereinafter referred to as PWM generation unit) and driver element 340. PWM generation unit 330 is in order to export a square-wave signal Ssq according to data signal Sdt. Driver element 340 is coupled to PWM generation unit 330, in order to according to square-wave signal Ssq driven for emitting lights unit ED1. Wherein data signal Sdt comprises the dutycycle (ratio of fluorescent lifetime and display cycle) of display cycle.
PWM generation unit 330 at least includes enumerator 331 and comparator 332. Enumerator 331 is in order to count a clock signal CLK, in order to export a count signal Sct. In embodiments of the present invention, the PWM of a part drives the enumerator 331 of module can be upper numerical expression enumerator (uptypecounter), or lower numerical expression enumerator (downtypecounter). For example, when enumerator 331 is upper numerical expression enumerator and the 1st pulse receiving clock signal CLK, the value of count signal Sct is 1. Similarly, when enumerator 331 receives the 2nd pulse of clock signal CLK, the value of count signal Sct is 2. Similarly, when enumerator 331 receives the 255th pulse of clock signal CLK, the value of count signal Sct is 255, and when enumerator 331 receives the 256th pulse of clock signal CLK, enumerator 331 is reset and the value of count signal Sct is 0.
When enumerator 331 is lower numerical expression enumerator and the 1st pulse receiving clock signal CLK, the value of count signal Sct is 255. Similarly, when enumerator 331 receives the 2nd pulse of clock signal CLK, the value of count signal Sct is 254. Similarly, when enumerator 331 receives the 255th pulse of clock signal CLK, the value of count signal Sct is 1, and when enumerator 331 receives the 256th pulse of clock signal CLK, enumerator 331 is reset and the value of count signal Sct is 0.
Comparator 332 is in order to produce square-wave signal Ssq according to count signal Sct and data signal Sdt. In embodiments of the present invention, comparator 332 has an anode and is coupled to enumerator 331 and a negative terminal is coupled to this PWM buffer so that when count signal Sct is more than this data signal, this square-wave signal is high-voltage level. When count signal Sct is less than this data signal, this square-wave signal is low voltage level.
With data signal Sdt for 04, and to have 255 unit interval UT1 ~ UT255 be example the display cycle. When unit interval UT1 ~ UT4, the count signal Sct of upper numerical expression enumerator was 001 ~ 004 (being not more than 004), and therefore square-wave signal Ssq is low voltage level. When unit interval UT5 ~ UT255, the count signal Sct of upper numerical expression enumerator is 005 ~ 255 (more than 004), and therefore square-wave signal Ssq is high-voltage level. On the contrary, when unit interval UT1 ~ UT251, the count signal Sct of lower numerical expression enumerator is 255 ~ 005 (more than 004), and therefore square-wave signal Ssq is high-voltage level.When unit interval UT252 ~ UT255, the count signal Sct of lower numerical expression enumerator was 004 ~ 001 (being not more than 004), and therefore square-wave signal Ssq is low voltage level.
Therefore, when enumerator 331 is upper numerical expression enumerator, and when the unit interval UT1 of each display cycle, almost all of luminescence unit all can be switched on so that power line Vp can produce maximum current. But, simultaneously turn on when all luminescence unit ED1 ~ EDn are all in the unit interval UT1 of each display cycle, power line Vp must provide for maximum current, and now electric current is increased to maximum current circuit will cause bad impact by zero, even thus produce noise. Therefore, in embodiments of the present invention, PWM drives module DM1 ~ DMn to be divided into multiple set, described set at least has the first set and the second set, and drive the square-wave signal of the first set and drive the first square-wave signal gathered reverse each other, the ON time and the shut-in time that make the luminescence unit of the first set and the luminescence unit of the second set are by chance contrary, and then the maximum current that script power line Vp must endure as is shared out equally each unit interval to the display cycle.
According to one embodiment of the invention, the enumerator that wherein the first set comprises is upper numerical expression enumerator, and second the enumerator that comprises of set be lower numerical expression enumerator, part luminescence unit ED1 ~ EDn will not be unlocked at unit interval UT1, reduce luminescence unit ED1 ~ EDn and cause the burden on power line Vp in the conducting of same unit interval.
For example, light emitting module 220 has luminescence unit ED1 ~ ED16 (n=16), then drive circuit 100 has 16 channels (namely driving module DM1 ~ DM16). Driving module DM1 ~ DM16 to be segmented into 2 set, the 1st set is for driving module DM1 ~ DM8, and the 2nd set is for driving module DM9 ~ DM16. The enumerator wherein driving module DM1 ~ DM8 is upper numerical expression enumerator, and the enumerator driving module DM9 ~ DM16 is lower numerical expression enumerator. What drive module is grouped into purposes of discussion, but is not limited to this. Such as, DMi (i is odd number) also can be used as the 1st set, DMj (j is even number) is used as the 2nd set.
Fig. 4 is the graph of a relation of the online electric current of power supply and time. Type of drive according to PWM, the current waveform shown in Fig. 4 is by identical with the square-wave signal of PWM or be reverse. Embodiment according to Fig. 3 of the present invention, the waveform of electric current and square-wave signal Ssq are just reverse. According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driving module DM1 ~ DMn by the first end, and the second end is coupled to earth terminal, and current waveform therein is identical with square-wave signal Ssq.
As shown in Figure 4,1st gathers in electric current produced by power line Vp such as shown in waveform Cv1, waveform Cv2 the 2nd is integrated on power line Vp produced electric current, waveform Cvs is electric current produced by the 1st set and the 2nd is integrated on power line Vp, and wherein the 1st set is all numerical expression enumerator with the enumerator of the 2nd set. Waveform Cv2 ' the 2nd is integrated on power line Vp produced electric current, and wherein the enumerator of the 2nd set is lower numerical expression enumerator, and waveform Cvs ' is the sum total of waveform Cv1 Yu waveform Cv2 '. Significantly it can be seen that, stagger the 1st set and the 2nd ON time gathered by luminescence unit is divided into the 1st set and the 2nd collection are incorporated in a turn-on cycle DP, on power line Vp, the electric current of institute's load is by certain part-time concentrated in turn-on cycle DP, then it is dispersed to whole turn-on cycle DP so that CURRENT DISTRIBUTION comparatively average (waveform Cvs ' is compared with waveform Cvs).In this embodiment, the rising edge of waveform Cv1 is positioned at the starting point of display cycle DP, and the trailing edge of waveform Cv2 ' is positioned at the end point of display cycle DP, and the trailing edge of the rising edge of waveform Cv2 ' and waveform Cv1 occurs simultaneously.
Fig. 5 is the electric current and the graph of a relation of time that power supply is online according to another embodiment of the present invention. Type of drive according to PWM, the waveform of the electric current shown in Fig. 5 is by identical with the square-wave signal of PWM or be reverse. Embodiment according to Fig. 3 of the present invention, the waveform of electric current and square-wave signal Ssq are just reverse. According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driving module DM1 ~ DMn by the first end, and the second end is coupled to earth terminal, and current waveform therein is identical with square-wave signal Ssq.
As shown in Figure 5,1st gathers in electric current produced by power line Vp such as shown in waveform Cv1, waveform Cv2 ' the 2nd is integrated on power line Vp produced electric current, waveform Cvs ' is electric current produced by the 1st set and the 2nd is integrated on power line Vp, and wherein the 1st set is all numerical expression enumerator with the enumerator of the 2nd set. In this embodiment, the rising edge of waveform Cv1 is positioned at the starting point of display cycle DP, the trailing edge of waveform Cv2 ' is positioned at the end point of display cycle DP, and the rising edge of waveform Cv2 ' is later than the rising edge of waveform Cv1, thus results in the waveform of the waveform Cvs ' representing total current. In addition, width (working cycle) can be different in the different display cycles for waveform Cv1 and Cv2 '.
The graph of a relation of the online electric current of Fig. 6 power supply according to another embodiment of the present invention and time. Type of drive according to PWM, the waveform of the electric current shown in Fig. 6 is by identical with the square-wave signal of PWM or be reverse. Embodiment according to Fig. 3 of the present invention, the waveform of electric current and square-wave signal Ssq are just reverse. According to another embodiment of the present invention, multiple luminescence unit ED1 ~ EDn can be coupled to corresponding PWM driving module DM1 ~ DMn by the first end, and the second end is coupled to earth terminal, and current waveform therein is identical with square-wave signal Ssq.
As shown in Figure 6,1st gathers in electric current produced by power line Vp such as shown in waveform Cv1, waveform Cv2 ' the 2nd is integrated on power line Vp produced electric current, waveform Cvs ' is electric current produced by the 1st set and the 2nd is integrated on power line Vp, and wherein the rising edge of waveform Cv2 ' is later than the trailing edge of waveform Cv1. In addition, width (working cycle) can be different in the different display cycles for waveform Cv1 and Cv2 '.
Fig. 7 is electric current Probability Distribution figure. As shown in Figure 7,1st gathers in electric current Probability Distribution figure produced by power line Vp such as shown in waveform Cp1, waveform Cp2 the 2nd is integrated on power line Vp produced electric current Probability Distribution figure, and wherein the 1st set is all numerical expression enumerator with the enumerator of the 2nd set. Owing to waveform Cp1 and waveform Cp2 drives corresponding luminescence unit by the starting point of display cycle DP so that electric current is all start to produce in the starting point of display cycle DP, therefore produce the probability of electric current in the starting point of display cycle DP the highest. But, end point at display cycle DP is typically not electric current so that the probability that the end point at display cycle DP produces electric current is almost nil. Waveform Cps is the Probability Distribution figure of total current produced by the 1st set and the 2nd is integrated on power line Vp. 1st set of same phase and the 2nd set common on power line Vp produced electric current Probability Distribution identical with waveform Cp1 and waveform Cp2 so that represent the 1st set and the 2nd be integrated on power line Vp produced by the Probability Distribution figure waveform Cps of total current also identical with the Probability Distribution of waveform Cp1 and waveform Cp2.
Waveform Cp2 ' the 2nd is integrated on power line Vp produced electric current Probability Distribution figure, and wherein the enumerator of the 2nd set is lower numerical expression enumerator, and waveform Cps ' is the Probability Distribution figure of total current produced by the 1st set and the 2nd is integrated into power line Vp on. Significantly it can be seen that, by luminescence unit is divided into the 1st set and the 2nd gather and utilize numerical expression enumerator and lower numerical expression enumerator to change starting point and the end point of the electric current that driver element exports respectively, the probability making each time point generation electric current in display cycle DP can be comparatively average, with the momentary load that reduction causes on power line Vp.
Fig. 8 is a schematic diagram of the drive circuit of the present invention. As shown in Figure 8, drive circuit 810 is similar to drive circuit 310, and difference is in that each PWM drives module DM1 ~ DMn to include buffer unit 850, in order to the data signal Sdt on data cached line DL, and by data signal Sdt output to PWM generation unit 830. Pulse width modulation buffer 833 (hereinafter referred to as PWM buffer) is included, in order to store the data signal Sdt coming from buffer unit 850, and by data signal Sdt input to comparator 832 in each PWM generation unit 830.
In embodiments of the present invention, comparator 832 has an anode and is coupled to this enumerator and a negative terminal is coupled to this PWM buffer 833 so that when count signal Sct is more than data signal Sdt, square-wave signal Ssq is high-voltage level. In certain embodiments, comparator 832 has an anode and is coupled to PWM buffer 833 and a negative terminal is coupled to enumerator 831 so that when data signal Sdt is more than count signal Sct, square-wave signal Ssq is high-voltage level.
Fig. 9 is a flow chart of the driving method of the present invention, as it is shown in figure 9, driving method comprises the following steps.
In step S91, described PWM drive module DM1 ~ DMn be at least divided into the first set and the second set, wherein the PWM in the first set drives the enumerator that module comprises to be upper numerical expression enumerator, and the PWM in the second set drives the enumerator that module comprises to be lower numerical expression enumerator. In step S92, the enumerator 831 in module is driven to count clock signal CLK from corresponding initial value by each PWM, in order to output count signal Sct. The comparator 832 in module is driven to produce square-wave signal Ssq according to count signal Sct and corresponding data signal Sdt in step S93, each PWM. In step S94, the driver element 810 in module is driven to drive the luminescence unit ED1 ~ EDn of correspondence respectively according to square-wave signal Ssq by each PWM.
In sum, the count mode of the enumerator 331 of enumerator the 331 and the 2nd set of the 1st set of the present invention differs, therefore reduce luminescence unit ED1 ~ EDn chance turned on together in starter unit time (such as UT1) of display cycle or last unit interval (such as UT255), reduce the load caused on power line Vp.
The foregoing is only present pre-ferred embodiments; so it is not limited to the scope of the present invention; anyone familiar with this technology; without departing from the spirit and scope of the present invention; can doing on this basis and further improve and change, therefore protection scope of the present invention ought be as the criterion with the scope that following claims defines.
Claims (14)
1. a drive circuit, it is characterised in that including:
One the oneth PWM drives module, one first data signal according to a data stream produces one first square-wave signal, in order to drive one first luminescence unit, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of above-mentioned display cycle; And
One the 2nd PWM drives module, one second data signal according to above-mentioned data stream produces one second square-wave signal, in order to drive one second luminescence unit, wherein above-mentioned second square-wave signal represents above-mentioned second luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal
Wherein, an above-mentioned PWM drives module to include one the oneth PWM generation unit, and above-mentioned 2nd PWM drives module to include one the 2nd PWM generation unit, and an above-mentioned PWM generation unit includes:
One first enumerator, in order to count a clock signal, in order to output one first count signal;And
One first comparator, in order to produce above-mentioned first square-wave signal according to above-mentioned first count signal and above-mentioned first data signal, when above-mentioned first count signal is more than above-mentioned first data signal, above-mentioned first square-wave signal is high-voltage level, when above-mentioned first count signal is less than above-mentioned first data signal, above-mentioned first square-wave signal is low voltage level
Above-mentioned 2nd PWM generation unit includes:
One second enumerator, in order to count above-mentioned clock signal, in order to output one second count signal; And
One second comparator, in order to produce above-mentioned second square-wave signal according to above-mentioned second count signal and above-mentioned second data signal, when above-mentioned second count signal is more than above-mentioned second data signal, above-mentioned second square-wave signal is high-voltage level, when above-mentioned second count signal is less than above-mentioned second data signal, above-mentioned second square-wave signal is low voltage level, and wherein above-mentioned first enumerator is upper numerical expression enumerator, and above-mentioned second enumerator is lower numerical expression enumerator.
2. a drive circuit, it is characterised in that including:
One the oneth PWM drives module, one first data signal according to a data stream produces one first square-wave signal, in order to drive one first luminescence unit, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of above-mentioned display cycle; And
One the 2nd PWM drives module, one second data signal according to above-mentioned data stream produces one second square-wave signal, in order to drive one second luminescence unit, wherein above-mentioned second square-wave signal represents above-mentioned second luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal
Wherein, an above-mentioned PWM drives module to include one the oneth PWM generation unit, and above-mentioned 2nd PWM drives module to include one the 2nd PWM generation unit, and an above-mentioned PWM generation unit includes:
One first enumerator, in order to count a clock signal, in order to output one first count signal; And
One first comparator, in order to produce above-mentioned first square-wave signal according to above-mentioned first count signal and above-mentioned first data signal, when above-mentioned first data signal is more than above-mentioned first count signal, above-mentioned first square-wave signal is high-voltage level, when above-mentioned first data signal is less than above-mentioned first count signal, above-mentioned first square-wave signal is low voltage level
Above-mentioned 2nd PWM generation unit includes:
One second enumerator, in order to count above-mentioned clock signal, in order to output one second count signal; And
One second comparator, in order to produce above-mentioned second square-wave signal according to above-mentioned second count signal and above-mentioned second data signal, when above-mentioned second data signal is more than above-mentioned second count signal, above-mentioned second square-wave signal is high-voltage level, when above-mentioned second data signal is less than above-mentioned second count signal, above-mentioned second square-wave signal is low voltage level, and wherein above-mentioned first enumerator is upper numerical expression enumerator, and above-mentioned second enumerator is lower numerical expression enumerator.
3. drive circuit according to claim 1 and 2, it is characterised in that the rising edge of above-mentioned second square-wave signal is later than the trailing edge of above-mentioned first square-wave signal.
4. drive circuit according to claim 1 and 2, it is characterised in that an above-mentioned PWM drives module also to include:
One first driver element, is coupled to an above-mentioned PWM generation unit, drives above-mentioned first luminescence unit according to above-mentioned first square-wave signal, and above-mentioned 2nd PWM drives module also to include:
One second driver element, is coupled to above-mentioned 2nd PWM generation unit, drives above-mentioned second luminescence unit according to above-mentioned second square-wave signal.
5. drive circuit according to claim 1 and 2, it is characterized in that, above-mentioned first luminescence unit and above-mentioned second luminescence unit coupled in parallel, and the first end of above-mentioned first luminescence unit and above-mentioned second luminescence unit is coupled to a power line, second end of above-mentioned first luminescence unit is coupled to an above-mentioned PWM and drives module, and the second end of above-mentioned second luminescence unit is coupled to above-mentioned 2nd PWM and drives module.
6. drive circuit according to claim 1 and 2, it is characterised in that an above-mentioned PWM drives module also to include:
One first buffer unit, in order to receive above-mentioned first data signal, and exports above-mentioned first data signal to an above-mentioned PWM driving module, and above-mentioned 2nd PWM drives module also to include:
One second buffer unit, in order to receive above-mentioned second data signal, and exports the extremely above-mentioned 2nd PWM driving module of above-mentioned second data signal.
7. drive circuit according to claim 6, it is characterised in that an above-mentioned PWM generation unit also includes:
One the oneth PWM buffer, is coupled between above-mentioned first buffer unit and above-mentioned first comparator, and in order to store above-mentioned first data signal, and above-mentioned 2nd PWM generation unit also includes:
One the 2nd PWM buffer, is coupled between above-mentioned second buffer unit and above-mentioned second comparator, in order to store above-mentioned second data signal.
8. drive circuit according to claim 7, it is characterized in that, above-mentioned first comparator has an anode and is coupled to above-mentioned first enumerator, and one negative terminal be coupled to an above-mentioned PWM buffer, make when above-mentioned first count signal is more than above-mentioned first data signal, above-mentioned first square-wave signal is high-voltage level, and above-mentioned second comparator has an anode and is coupled to above-mentioned second enumerator, and one negative terminal be coupled to above-mentioned 2nd PWM buffer, make when above-mentioned second count signal is more than above-mentioned second data signal, above-mentioned second square-wave signal is high-voltage level.
9. drive circuit according to claim 7, it is characterized in that, above-mentioned first comparator has an anode and is coupled to an above-mentioned PWM buffer, and one negative terminal be coupled to above-mentioned first enumerator, make when above-mentioned first data signal is more than above-mentioned first count signal, above-mentioned first square-wave signal is high-voltage level, and above-mentioned second comparator has an anode and is coupled to above-mentioned 2nd PWM buffer, and one negative terminal be coupled to above-mentioned second enumerator, make when above-mentioned second data signal is more than above-mentioned second count signal, above-mentioned second square-wave signal is high-voltage level.
10. drive circuit according to claim 1 and 2, it is characterised in that above-mentioned first luminescence unit and above-mentioned second luminescence unit are light emitting diode.
11. a driving method, it is characterised in that being applicable to drive one first luminescence unit and one second luminescence unit, above-mentioned driving method includes:
One first data signal according to a data stream produces one first square-wave signal, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of a display cycle;
Above-mentioned first luminescence unit is driven according to above-mentioned first square-wave signal;
One second data signal according to above-mentioned data stream produces one second square-wave signal, wherein above-mentioned second square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal;And
Above-mentioned second luminescence unit is driven according to above-mentioned second square-wave signal,
Wherein, the step producing above-mentioned first square-wave signal and above-mentioned second square-wave signal includes:
By numerical expression rolling counters forward one clock signal on, in order to output one first count signal;
By the above-mentioned clock signal of numerical expression rolling counters forward once, in order to output one second count signal;
Relatively above-mentioned first count signal and above-mentioned first data signal, to produce above-mentioned first square-wave signal, when above-mentioned first count signal is more than above-mentioned first data signal, above-mentioned first square-wave signal is high-voltage level, when above-mentioned first count signal is less than above-mentioned first data signal, above-mentioned first square-wave signal is low voltage level; And
Relatively above-mentioned second count signal and above-mentioned second data signal, to produce above-mentioned second square-wave signal, when above-mentioned second count signal is more than above-mentioned second data signal, above-mentioned second square-wave signal is high-voltage level, when above-mentioned second count signal is less than above-mentioned second data signal, above-mentioned second square-wave signal is low voltage level.
12. a driving method, it is characterised in that being applicable to drive one first luminescence unit and one second luminescence unit, above-mentioned driving method includes:
One first data signal according to a data stream produces one first square-wave signal, wherein above-mentioned first square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of a display cycle, and the rising edge of above-mentioned first square-wave signal is positioned at the starting point of a display cycle;
Above-mentioned first luminescence unit is driven according to above-mentioned first square-wave signal;
One second data signal according to above-mentioned data stream produces one second square-wave signal, wherein above-mentioned second square-wave signal represents above-mentioned first luminescence unit in the fluorescent lifetime of above-mentioned display cycle, the trailing edge of above-mentioned second square-wave signal is positioned at the end point of above-mentioned display cycle, and the rising edge of above-mentioned second square-wave signal is later than the rising edge of above-mentioned first square-wave signal; And
Above-mentioned second luminescence unit is driven according to above-mentioned second square-wave signal,
Wherein, the step producing above-mentioned first square-wave signal and above-mentioned second square-wave signal includes:
By numerical expression rolling counters forward one clock signal on, in order to output one first count signal;
By the above-mentioned clock signal of numerical expression rolling counters forward once, in order to output one second count signal;
Relatively above-mentioned first count signal and above-mentioned first data signal, to produce above-mentioned first square-wave signal, when above-mentioned first data signal is more than above-mentioned first count signal, above-mentioned first square-wave signal is high-voltage level, when above-mentioned first data signal is less than above-mentioned first count signal, above-mentioned first square-wave signal is low voltage level; And
Relatively above-mentioned second count signal and above-mentioned second data signal, to produce above-mentioned second square-wave signal, when above-mentioned second data signal is more than above-mentioned second count signal, above-mentioned second square-wave signal is high-voltage level, when above-mentioned second data signal is less than above-mentioned second count signal, above-mentioned second square-wave signal is low voltage level.
13. the driving method according to claim 11 or 12, it is characterised in that the rising edge of above-mentioned second square-wave signal is later than the trailing edge of above-mentioned first square-wave signal.
14. the driving method according to claim 11 or 12, it is characterised in that above-mentioned first luminescence unit and above-mentioned second luminescence unit are light emitting diode.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW247359B (en) * | 1993-08-30 | 1995-05-11 | Hitachi Seisakusyo Kk | Liquid crystal display and liquid crystal driver |
| CN1758306A (en) * | 2004-06-30 | 2006-04-12 | 佳能株式会社 | Driving circuit of display element, image display apparatus, and television apparatus |
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| JP2002096503A (en) * | 1999-12-22 | 2002-04-02 | Fuji Photo Film Co Ltd | Multichannel pulse width modulator and down counter |
| JP2008009398A (en) * | 2006-05-29 | 2008-01-17 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display, light source device and light source control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW247359B (en) * | 1993-08-30 | 1995-05-11 | Hitachi Seisakusyo Kk | Liquid crystal display and liquid crystal driver |
| CN1758306A (en) * | 2004-06-30 | 2006-04-12 | 佳能株式会社 | Driving circuit of display element, image display apparatus, and television apparatus |
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