CN103905157B - The cumulative of part parallel input moves to left QC-LDPC encoders in deep space communication - Google Patents
The cumulative of part parallel input moves to left QC-LDPC encoders in deep space communication Download PDFInfo
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Abstract
The present invention provides part parallel in a kind of deep space communication input it is cumulative move to left QC LDPC encoders, the encoder include 12 prestore the generator polynomial look-up table of all circular matrix generator polynomials in all yards of class generator matrixes, 12 to message segment and generator polynomial bit carry out scalar multiplication 2048 binary multipliers, 12 to sum of products shift register content carry out mould 2 plus 2048 binary adders, 12 storages are by 2048 bit shift registers of the sum of ring shift left 1.Finally, verification data is contained in 12 shift registers.All yards of class QC LDPC codes in part parallel input coding device compatibility CCSDS deep space communication systems provided by the invention, have many advantages, such as that few register, simple in structure, small power consumption, at low cost, working frequency is high, handling capacity is big.
Description
Technical field
The present invention relates to field of channel coding, more particularly to part parallel inputs in a kind of CCSDS deep space communications system
It is cumulative to move to left QC-LDPC encoders.
Background technology
Low-density checksum (Low-Density Parity-Check, LDPC) code be efficient channel coding technology it
One, and quasi-cyclic LDPC (Quasi-Cyclic LDPC, QC-LDPC) code is a kind of special LDPC code.The life of QC-LDPC codes
All it is the array being made of circular matrix at matrix G and check matrix H, has the characteristics that stages cycle, therefore be referred to as QC-LDPC
Code.The first trip of circular matrix is footline ring shift right 1 as a result, remaining each row is all the knot of its lastrow ring shift right 1
Fruit, therefore, circular matrix are characterized by its first trip completely.In general, the first trip of circular matrix is referred to as its generator polynomial.
CCSDS deep space communication standards use the QC-LDPC codes of system form, and the left-half of generator matrix G is one
Unit matrix, right half part are by a × c b × b rank circular matrixes Gi,j(0≤i<a,a≤j<T, t=a+c) constitute array,
As follows：
Wherein, I is b × b rank unit matrixs, and 0 is b × b rank full null matrix.Continuous b rows and the b row of G are known respectively as block
Row and block row.By formula (1) it is found that G has a blocks row and t blocks row.Enable circular matrix Gi,jFirst trip gi,jIt is its generator polynomial.
CCSDS deep space communication standards use 9 kinds of QC-LDPC codes, there is c=12.Fig. 1 give parameter a, b under different code class π and
t。
For CCSDS deep space communication standards, generator matrix G corresponds to code word v=(s, p), and the corresponding preceding a blocks row of G are letters
Cease vector s=(e0,e1,…,ea×b-1), corresponding rear c blocks row are verification vector p=(d0,d1,…,dc×b-1).It is with b bits
One section, information vector s is divided into a sections, i.e. s=(s0,s1,…,sa-1)；Verification vector p is divided into c sections, i.e. p=(p0,
p1,…,pc-1).By v=sG it is found that-a sections of verification vectors of jth meet
pj-a=s0G0,j+s1G1,j+…+siGi,j+…+sa-1Ga-1,j (2)
Wherein, 0≤i<A, a≤j<T, t=a+c.It enablesWithIt is generator polynomial g respectivelyi,jRing shift right n and cycle
Move to left n results, wherein 0≤n≤b.So, i-th on the right of formula (2) equal sign deployable to be
Currently, QC-LDPC codes it is widely used be that accumulator (Type-I Shift- are added based on c I type shift register
Register-Adder-Accumulator, SRAA-I) circuit serial encoder.Fig. 2 is the function of single SRAA-I circuits
Block diagram, information vector s are serially sent into the circuit by turn.When with SRAA-I circuits to verify section pj-a(a≤j<When t) being encoded,
Generator polynomial look-up table prestores all generator polynomials of the jth block row of generator matrix G, and accumulator is cleared initially
Change.When the 0th clock cycle arrives, shift register loads the 0th piece of row of G from generator polynomial look-up table, jth block arranges
Generator polynomialInformation bit e0 moves into circuit, and with the content of shift registerCarry out scalar multiplication, productAdd with 0 mould 2 of content of accumulator, andIt is stored back to accumulator.When the 1st clock cycle arrives, shift register
Ring shift right 1, content becomesInformation bit e1 moves into circuit, and with the content of shift registerCarry out scalar
Multiply, productWith the content of accumulatorMould 2 adds, andIt is stored back to accumulator.It is above-mentioned move to right-- multiply-add-deposits
Storage process continues down.At the end of the b-1 clock cycle, information bit eb-1Circuit is had been moved into, accumulator is deposited at this time
Storage is part and s0G0,j, this is message segment s0To pj-aContribution.When b-th clock cycle arrives, shift register is from life
The 1st piece of row of G, the generator polynomial of jth block row are loaded at multinomial look-up tableRepeat it is above-mentioned move to right-- multiply-add-deposits
Storage process.When message segment s1 is moved fully into circuit, accumulator storage is part and s0G0,j+s1G1,j.It repeats the above process,
Circuit is moved into until entire information vector s is all serial.At this point, that accumulator storage is verification section pj-a.Use c SRAA-I
Circuit can constitute serial encoder shown in Fig. 3, it finds out c verification section simultaneously within a × b clock cycle.The program needs
Want 2 × c × b register, c × b two inputs and door and c × b two input XOR gate, it is also necessary to which c a × b bits ROM is deposited
Store up the generator polynomial of circular matrix.
For compatible 9 kinds of code classes, the existing solution of QC-LDPC encoders is to be based on 12 in CCSDS deep space communication standards
A SRAA-I circuits.There are two disadvantages for the program：First, needing 49152 registers, cause the power consumption of circuit big, of high cost；
Second is that serial input information bit, loaded in parallel generator polynomial, need 24577 connecting lines.So many line can cause
The circuit structure of encoder is complicated, working frequency is low, handling capacity is small.
Invention content
The existing implementation of multi-code class QC-LDPC encoders there are power consumptions big, cost in CCSDS deep space communication systems
Disadvantage high, circuit structure is complicated, working frequency is low, handling capacity is small, for these technical problems, the present invention provides a kind of bases
In the cumulative part parallel input coding device moved to left.
As shown in figure 5, in CCSDS deep space communication systems part parallel input cumulative to move to left QC-LDPC encoders main
It is made of 4 parts：Generator polynomial look-up table, b binary multiplier, b binary adders and shift register.Coding
5 steps of process point are completed：1st step resets shift register R0,R1,…,R11；2nd step, input information section si(0≤i<a)；3rd
Step, generator polynomial look-up table L0,L1,…,L11A, a+1 in output code class π generator matrixes i-th piece of row of G respectively ..., t-1 blocks
The generator polynomial bit of row, these generator polynomial bits pass through b binary multiplier M respectively0,M1,…,M11With information
Section siCarry out scalar multiplication, b binary multiplier M0,M1,…,M11Product pass through b binary adder A respectively0,
A1,…,A11With shift register R0,R1,…,R11Content be added, b binary adder A0,A1,…,A11And recycled
It moves to left the result after 1 and is stored in shift register R respectively0,R1,…,R11；4th step, repeats the 3rd step b times；5th step is step with 1
The long value for incrementally changing i, repeats the 2nd~4 step a times, is finished until entire information vector s is inputted, at this point, shift register
R0,R1,…,R11Storage is verification section p respectively0,p1,…,p11, they constitute verification vector p=(p0,p1,…,p11)。
Part parallel input coding device provided by the invention is simple in structure, all codes in compatible CCSDS deep space communication systems
The QC-LDPC codes of class can reduce register and line under conditions of keeping coding rate, reduce power consumption and cost, improve work
Working frequency and handling capacity.
Advantage about the present invention can be further understood with method by following detailed description and accompanying drawings.
Description of the drawings
Fig. 1 summarizes the parameter a and c of 9 kinds of code class QC-LDPC code generator matrixes in CCSDS deep space communication systems；
Fig. 2 is the functional block diagram that I type shift registers add accumulator SRAA-I circuits；
Fig. 3 is the QC-LDPC serial encoders being made of c SRAA-I circuit；
Fig. 4 is the functional block diagram of the multiply-add shift register MASR circuits inputted parallel；
What Fig. 5 was that the MASR circuits inputted parallel by 12 are constituted a kind of inputting QC- based on the cumulative part parallel moved to left
LDPC encoder.
Specific implementation mode
Presently preferred embodiments of the present invention is elaborated below in conjunction with the accompanying drawings, so that advantages and features of the invention can be more
It is easy to be readily appreciated by one skilled in the art, apparent is explicitly defined to be made to protection scope of the present invention.
Enable generator polynomial gi,j=(gi,j,0,gi,j,1,…,gi,j,b-1), then Gi,jIt can be considered unit matrix ring shift right version
This weighted sum, i.e.,
Gi,j=gi,j,0Ir(0)+gi,j,1Ir(1)+…+gi,j,b-1Ir(b-1) (4)
So, i-th on the right of formula (2) equal sign deployable to be
Since by siBy its ring shift left b-n, i.e., ring shift right n is equivalent toSo formula (5) can change
It is written as
Compared with formula (3), the remarkable advantage of formula (6) is the parallel input information bits of segmentation, serially loads generator polynomial
gi,j, it is not necessarily to ring shift right generator polynomial gi,j.Formula (6) is the process that a-multiply-add-is moved to left-stored, in fact current parallel defeated
Multiply-add shift register (Multiplier-Adder-Shift-Register, the MASR) circuit entered.Fig. 4 is inputted parallel
The functional block diagram of MASR circuits, information vector s are one section with b bits and are sent into the circuit parallel.When electric with the MASR inputted parallel
Road is to verifying section pj-a(a≤j<When t) being encoded, generator polynomial look-up table prestores the jth block row of generator matrix G
All generator polynomials, shift register are cleared initialization.When the 0th clock cycle arrives, message segment s0Circuit is moved into,
Generator polynomial look-up table exports the generator polynomial g of the 0th piece of row of G, jth block row0,jThe 0th bit g0,j,0, and and information
Section s0Carry out scalar multiplication, product g0,j,0s0With 0 mould 2 of content plus and g of shift register0,j,0s0The result (0 that ring shift left is 1
+g0,j,0s0)l(1)It is stored back to shift register.When the 1st clock cycle arrives, generator polynomial look-up table exports g0,jThe 1st
A bit g0,j,1, and with message segment s0Carry out scalar multiplication, product g0,j,1s0With the content (0+g of shift register0,j,0s0)l(1)Mould
2 add, and (0+g0,j,0s0)l(1)+g0,j,1s0The result ((0+g of ring shift left 10,j,0s0)l(1)+g0,j,1s0)l(1)Displacement is stored back to post
Storage.Above-mentioned-multiply-add-moves to left-and storing process continues down.At the end of the b-1 clock cycle, shift register is deposited
Storage is part and s0G0,j, this is message segment s0To pj-aContribution.When b-th of clock cycle arrives, message segment s1Move into electricity
Road repeats above-mentioned-multiply-add-and moves to left-storing process.When generator polynomial look-up table has exported g1,jThe last one bit
g1,j,b-1When, shift register storage is part and s0G0,j+s1G1,j.It repeats the above process, until entire information vector s is complete
Portion moves into circuit parallel.At this point, that shift register storage is verification section pj-a。
What Fig. 5 gave that the MASR inputted parallel by 12 constitutes a kind of inputting QC- based on the cumulative part parallel moved to left
LDPC encoder, by four kinds of generator polynomial look-up table, b binary multipliers, b binary adders and shift register
Function module forms.Generator polynomial look-up table L0,L1,…,L11Prestore all yards of classes generator matrix G a, a+1 respectively ...,
All circular matrix generator polynomials in t-1 blocks row.Generator polynomial look-up table L0,L1,…,L11The generator polynomial of output
Bit respectively with message segment si(0≤i<A) scalar multiplication is carried out, this 12 scalar multiplications pass through b binary multiplier M respectively0,
M1,…,M11It completes.B binary multiplier M0,M1,…,M11Product respectively with shift register R0,R1,…,R11Content
It is added, this 12 nodulo-2 additions pass through b binary adder A respectively0,A1,…,A11It completes.B binary adder A0,
A1,…,A11And shift register R is stored in by the result after ring shift left 1 respectively0,R1,…,R11。
Generator polynomial look-up table L0,L1,…,L11Store the circular matrix in all yards of class QC-LDPC code generator matrixes
Generator polynomial.L0~L11All generator polynomials in all yards of class generator matrix G a~t-1 blocks row are stored respectively, for
Any block arranges, and stores the 0th, 1 successively ..., the corresponding generator polynomial of a-1 block rows.
QC-LDPC coding methods are inputted based on the cumulative part parallel moved to left the present invention provides a kind of, it is compatible with CCSDS
9 kinds of code class QC-LDPC codes, coding step are described as follows in deep space communication standard：
1st step resets shift register R0,R1,…,R11；
2nd step, input information section si(0≤i<a)；
3rd step, generator polynomial look-up table L0,L1,…,L11A, a in output code class π generator matrixes i-th piece of row of G respectively
The generator polynomial bit of+1 ..., t-1 block row, these generator polynomial bits pass through b binary multiplier M respectively0,
M1,…,M11With message segment siCarry out scalar multiplication, b binary multiplier M0,M1,…,M11Product pass through b binary systems respectively
Adder A0,A1,…,A11With shift register R0,R1,…,R11Content be added, b binary adder A0,A1,…,A11
And shift register R is stored in by the result after ring shift left 1 respectively0,R1,…,R11；
4th step, repeats the 3rd step b times；
5th step incrementally changes the value of i with 1 for step-length, repeats the 2nd~4 step a times, until entire information vector s is inputted
It finishes, at this point, shift register R0,R1,…,R11Storage is verification section p respectively0,p1,…,p11, they constitute verification to
Measure p=(p0,p1,…,p11)。
It is not difficult to find out from above step, entire cataloged procedure needs a × b clock cycle altogether, and 12 are based on existing
The serial encoding method of SRAA-I circuits is identical.
The existing solution of QC-LDPC encoders needs 49152 registers, 24576 in CCSDS deep space communication standards
A two input and door and 24576 two input XOR gates, and the present invention needs 24576 registers, 24576 two inputs and doors
With 24576 two input XOR gates.Two kinds of coding methods expend identical quantity with door and XOR gate, but present invention saves
50% register.
Existing solution needs 24577 line connection shift registers and generator polynomial look-up table, and the present invention is only
Need 2060 connecting lines.
To sum up, for the encoder of 9 kinds of QC-LDPC codes in CCSDS deep space communication standards, with existing solution phase
Than the present invention maintains identical coding rate, has saved the register of half, has greatly simplified circuit connection, has knot
Structure is simple, small power consumption, the advantages that at low cost, working frequency is high, handling capacity is big.
One of the above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto,
Any technical person familiar with the field within the technical scope disclosed by the invention, the change that can be expected without creative work
Change or replace, should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with claims
Defined by subject to protection domain.
Claims (3)
1. the cumulative of part parallel input moves to left QC-LDPC encoders, the generator matrix G of QC-LDPC codes in a kind of deep space communication
It is divided into a blocks row and t blocks row, it is by a × c b × b rank circular matrixes G that rear c blocks, which arrange corresponding part generator matrix,i,jThe battle array of composition
Row, gi,jIt is circular matrix Gi,jGenerator polynomial, wherein t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<A, a
≤j<T, CCSDS deep space communication standard use the QC-LDPC codes of 9 kinds of different code class π, π is 0 respectively, 1,2,3,4,5,6,7,
8, for this 9 kinds different code class quasi-cyclic LDPC codes, there is a c=12, the corresponding parameter a of 9 kinds of different code classes is 8 respectively, 8,8,
16,16,16,32,32,32, the corresponding parameter b of 9 kinds of different code classes be 2048 respectively, 512,128,1024,256,64,512,
128,32, the corresponding parameter t of 9 kinds of difference code classes is 20,20,20,28,28,28,44,44,44 respectively, generator matrix G correspondence codes
The corresponding preceding a blocks row of word v=(s, p), G are information vector s, and corresponding rear c blocks row are verification vector p, with b bits for one
Section, information vector s are divided into a sections, i.e. s=(s0,s1,…,sa-1), verification vector p is divided into c sections, i.e. p=(p0,
p1,…,p11), which is characterized in that the encoder includes with lower component：
Generator polynomial look-up table L0,L1,…,L11, a, a+ in all yards of class QC-LDPC code generator matrixes G that prestore respectively
1 ..., the circular matrix generator polynomial of t-1 blocks row；
B binary multiplier M0,M1,…,M11, respectively to message segment and generator polynomial look-up table L0,L1,…,L11Output
Bit carries out scalar multiplication；
B binary adder A0,A1,…,A11, respectively to b binary multiplier M0,M1,…,M11Sum of products displacement post
Storage R0,R1,…,R11Content carry out mould 2 plus；
Shift register R0,R1,…,R11, b binary adder A are stored respectively0,A1,…,A11And by ring shift left 1
Result afterwards and final verification section p0,p1,…,p11。
2. the cumulative of part parallel input moves to left QC-LDPC encoders in a kind of deep space communication according to claim 1,
It is characterized in that, the generator polynomial look-up table L0~L11It stores respectively in all yards of class generator matrix G a~t-1 blocks row
All generator polynomials arrange any block, store the 0th, 1 successively ..., the corresponding generator polynomial of a-1 block rows.
3. the cumulative of part parallel input moves to left QC-LDPC coding methods, the generator matrix of QC-LDPC codes in a kind of deep space communication
G points arrange for a blocks row and t blocks, and it is by a × c b × b rank circular matrixes G that rear c blocks, which arrange corresponding part generator matrix,i,jIt constitutes
Array, gi,jIt is circular matrix Gi,jGenerator polynomial, wherein t=a+c, a, b, c, i, j and t are nonnegative integer, 0≤i<
A, a≤j<T, CCSDS deep space communication standard use the QC-LDPC codes of 9 kinds of different code class π, π is 0 respectively, 1,2,3,4,5,6,
7,8, for this 9 kinds different code class quasi-cyclic LDPC codes, there is a c=12, the corresponding parameter a of 9 kinds of different code classes is 8 respectively, 8,
8,16,16,16,32,32,32, the corresponding parameter b of 9 kinds of different code classes be 2048 respectively, 512,128,1024,256,64,512,
128,32, the corresponding parameter t of 9 kinds of difference code classes is 20,20,20,28,28,28,44,44,44 respectively, generator matrix G correspondence codes
The corresponding preceding a blocks row of word v=(s, p), G are information vector s, and corresponding rear c blocks row are verification vector p, with b bits for one
Section, information vector s are divided into a sections, i.e. s=(s0,s1,…,sa-1), verification vector p is divided into c sections, i.e. p=(p0,
p1,…,p11), which is characterized in that the coding method includes the following steps：
1st step resets shift register R0,R1,…,R11；
2nd step, input information section si, wherein 0≤i<a；
3rd step, generator polynomial look-up table L0,L1,…,L11A, a+ in output code class π generator matrixes i-th piece of row of G respectively
The generator polynomial bit of 1 ..., t-1 block row, these generator polynomial bits pass through b binary multiplier M respectively0,
M1,…,M11With message segment siCarry out scalar multiplication, b binary multiplier M0,M1,…,M11Product pass through b binary systems respectively
Adder A0,A1,…,A11With shift register R0,R1,…,R11Content be added, b binary adder A0,A1,…,A11
And shift register R is stored in by the result after ring shift left 1 respectively0,R1,…,R11；
4th step, repeats the 3rd step b times；
5th step incrementally changes the value of i with 1 for step-length, repeats the 2nd~4 step a times, is finished until entire information vector s is inputted,
At this point, shift register R0,R1,…,R11Storage is verification section p respectively0,p1,…,p11, they constitute verification vector p=
(p0,p1,…,p11)。
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| US6674807B1 (en) * | 1999-01-21 | 2004-01-06 | Samsung Electronics Co., Ltd. | Communication apparatus and method for a CDMA communication system |
| CN101335596A (en) * | 2006-06-14 | 2008-12-31 | 北京新岸线移动多媒体技术有限公司 | Low density parity check code implementing apparatus |
| CN103248372A (en) * | 2013-04-19 | 2013-08-14 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic LDPC serial encoder based on ring shift left |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6674807B1 (en) * | 1999-01-21 | 2004-01-06 | Samsung Electronics Co., Ltd. | Communication apparatus and method for a CDMA communication system |
| CN101335596A (en) * | 2006-06-14 | 2008-12-31 | 北京新岸线移动多媒体技术有限公司 | Low density parity check code implementing apparatus |
| CN103248372A (en) * | 2013-04-19 | 2013-08-14 | 荣成市鼎通电子信息科技有限公司 | Quasi-cyclic LDPC serial encoder based on ring shift left |
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