CN103905137A - Synchronous pulse jitter suppression method and system based on FPGA - Google Patents

Abstract

The invention discloses a synchronous pulse jitter suppression method and system based on an FPGA. Reaching time of external pulses is recorded and buffered onto a BlockRAM of an FPGA sheet, then, next synchronous pulse reaching time is predicated, and a local synchronous pulse is triggered to be generated according to the next synchronous pulse reaching time, so that jitter removal is realized, shortening of capturing time and high jitter restriction can be realized at the same time, and the jitter performance and the stability of regenerated synchronous pulses are improved. The method and system are suitable for occasions which are used for processing low and medium frequence synchronous signals and are high in instantaneity requirement.

Description

Lock-out pulse jitter suppression method and system based on FPGA

Technical field

The present invention relates to a kind of lock-out pulse jitter suppression method and system based on FPGA, belong to data acquisition, communication and technical field of measurement and test.

Background technology

At present, time-sharing multiplex digital communication network extremely relies on synchronizing signal, if larger shake occurs the synchronizing signal of local recovery, just may cause that in some cases the deterioration of equipment performance causes data sampling to be made mistakes, and occurs communication error code.In cascaded communication system, synchronization jitter can make the signal after regeneration produce a position modulation, it not only makes the decision instant signal-to-noise ratio degradation of regenerating, but also be reflected in the signal after regeneration, pass to next repeater, shake down accumulates along relaying chain, thereby has limited communication distance, the existence of timing jitter, makes receiver synchro system can not follow the tracks of exactly and catch the timing information that receives signal.So, in order to reduce the error rate of system, just must adopt various effective ways to suppress the generation of timing jitter.

In Industry Control and power automation field, for the various asynchronous events of synchronous recording or semaphore, need to carry out synchro measure to the data acquisition unit of different physical distribution, and the shake of lock-out pulse can cause accurate measurement error to increase, synchro measure loses reference significance.In addition, even if shake, uniformly-spaced to being sent synchronization frame by synchronizer, because the reasons such as the aging and shake of crystal and link transmission also can be introduced randomized jitter, still need taken measures to eliminate in reference synchronization source by synchronizer side.

The several different methods having occurred for solving problem that above-mentioned synchronization jitter brings, main manifestations is as follows:

1) stability of raising pulse generation and transmission circuit, in order to reduce the variation in pulse duration and cycle, the pulse generating circuit of source must adopt high stability crystal, want to produce to there is the pulse train of stablizing bandwidth and cycle simultaneously, guarantee that lock-out pulse transmits shake from source to destination end simultaneously;

2) by the method for VCO and software calibration, take the voltage-controlled crystal (oscillator) (VCO) of high stable as local frequency source, by measuring the cycle of external sync pulse, circular error is carried out being converted to after Kalman filtering to the input value of DAC, adjust the output frequency of local crystal oscillator, thereby obtain long-term and all good frequency marking of short-term stability, the frequency that is used as rear class sync pulse regeneration loop produces local synchronization pulse;

3) digital phase-locked loop, utilizes phase detectors to detect phase difference between pulse of input pulse and output and by loop filter, phase difference is accumulated to peace and slides into and control digital controlled oscillator and realize jitter elimination.

Although the inhibition method of above-mentioned synchronization jitter, can eliminate a part of delay variation in external synchronization signal effectively, respectively have shortcoming, method 1) transmit leg base must adopt high stable time, guarantee the low jitter of transmitting procedure simultaneously, difficulty is larger; Method 2) need the complicated circuit such as VCO and DAC, cost is higher and comprise that based on Kalman filtering algorithm matrix inversion operation and matrix connect the iterative process such as multiplication, and computing is comparatively complicated, is difficult to realize on FPGA platform; Method 3) using in the scheme of phase-locked loop or use simple monocycle scheme, cause realizing between short pull-in time and narrower loop bandwidth, arrive simultaneously optimum, the scheme that uses complicated dicyclo to add VCXO makes whole cost and complexity rising reliability decrease, and, all phase-locked loops are all introduced negative feedback loop without exception, cause the loop-locking time elongated, affect real-time.

Therefore, finding a kind of method of effective anti-synchronization jitter, is current urgent problem.

Summary of the invention

The deficiency and the defect that exist in order to overcome prior art, lock-out pulse jitter suppression method and system based on FPGA provided by the invention, by first recording external pulse due in, and be buffered in Block RAM on FPGA sheet, then predict next synchronous pulse due in, and trigger according to this this new earth pulse, realize jitter elimination, meet and shorten pull-in time and high jitter suppression simultaneously, have a good application prospect.

The present invention realizes as follows:

Step (1), detects the rising edge of outer lock-out pulse by marginal detector, and in the time that rising edge arrives, records the value of current free-running operation timer, and this value is stabbed to t as current time _n, write BlockRAM on the sheet of FPGA;

Step (2), after external synchronization signal rising edge, takes out tectonic sequence { t by the timestamp recording in BlockRAM _n;

Step (3), chooses { t _nt ₀, t ₁, t ₂..., t _nn+1 observation data altogether, structure difference sequence { Δ t _n, make Δ t _n=t _n-t _n-1, utilize { Δ t _naverage estimate the interval of incoming sync pulse

Step (4), chooses sequence { t _nt ₁, t ₂..., t _nn observation data builds consensus sequence { t altogether _{s_n}, make t _{s_1}=t ₁=t _{m_1}+ ε ₁,

wherein, t _{m_1}for corresponding t ₁time the outer lock-out pulse benchmark moment, ε ₁ε _nfor t _{s_1}t _{s_n}with respect to t _{m_1}randomized jitter, and with { t _{s_n}estimation of Mean benchmark moment of going out main equipment lock-out pulse

Step (5), builds Linear Estimation equation according to the lock-out pulse interval of having estimated

with the outer lock-out pulse benchmark moment

predict new lock-out pulse due in

Step (6), will

deduct the output register that needs to write after side-play amount output comparator;

Step (7), output comparator is the timer of more local free-running operation and the value of output register constantly, once the two is consistent, the pulse of triggering synchronous impulse regenerator broadening output local synchronization.

The aforesaid lock-out pulse jitter suppression method based on FPGA, is characterized in that: step (3) is chosen { t _nt ₀, t ₁, t ₂..., t _nn+1 observation data altogether, builds difference sequence { Δ t _n, and utilize formula (1) to estimate the interval of incoming sync pulse

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{\Δ}{t}_i=\frac{1}{n}[(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})]=\frac{(t_n-t_0)}{n}---\left(1\right).$

The aforesaid lock-out pulse jitter suppression method based on FPGA, is characterized in that: step (4) is according to sequence { t _{s_n}average, utilize formula (2) estimation main equipment lock-out pulse that the moment occurs

The system of moving the above-mentioned lock-out pulse jitter suppression method based on FPGA, is characterized in that: be included in build in fpga chip with lower member,

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse;

Timestamp record and parameter calculator, for recording the interval of outer lock-out pulse due in the outer lock-out pulse of estimation

with the benchmark moment of outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for stabbing memory time data;

Local free-running operation timer, forms for generation of timestamp and participation output trigger impulse;

Synchronous fallout predictor, by the interval of the incoming sync pulse of estimating

there is the moment with main equipment lock-out pulse

predict new lock-out pulse due in and carry out as required phase shift;

Output comparator, by continuous comparison

with local free-running operation timer, in the time that the two is consistent, export synchronous trigger impulse;

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator;

The input input outer synchronous signal of described marginal detector, the output of marginal detector is connected with timestamp record and parameter calculator, described timestamp record and parameter calculator are connected with BlockRAM, local free-running operation timer respectively, the parameter output of described timestamp record and parameter calculator is connected with synchronous fallout predictor, output comparator and sync pulse regenerator in turn, described local free-running operation timer is also connected with output comparator, the pulse of described sync pulse regenerator broadening output local synchronization.

The invention has the beneficial effects as follows:

1. simple in structure, there is no feedback loop;

2. jitter suppression algorithm is realized by pure hardware, fast to the disturbance response time;

3. the drift of local clock relative reference clock and the impact of deviation have been estimated simultaneously;

4. tracking velocity is fast, both can genlocing after incoming sync pulse quantity exceedes data window;

5. utilize open loop dynamic prediction method, system is all under any circumstance stable;

6. the lock-out pulse of regeneration shake very little (<10ns).

Accompanying drawing explanation

Fig. 1 is the oscillogram that lock-out pulse arrives three kinds of situations of synchronous recipient's appearance.

Fig. 2 is the flow chart of the lock-out pulse jitter suppression method based on FPGA of the present invention.

Fig. 3 is the system block diagram of the lock-out pulse jitter suppression system based on FPGA of the present invention.

Embodiment

Below in conjunction with Figure of description, the invention will be further described.Following examples are only for technical scheme of the present invention is more clearly described, and can not limit the scope of the invention with this.

As shown in Figure 3, lock-out pulse jitter suppression system of the present invention, all utilize the Resources on Chip of FPGA to build, comprise marginal detector, timestamp record and parameter calculator, synchronously along fallout predictor, BlockRAM, local free-running operation timer, output comparator and sync pulse regenerator parts

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse;

Timestamp record and parameter calculator, for recording the interval of outer lock-out pulse due in the outer lock-out pulse of estimation

with the benchmark moment of outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for stabbing memory time data;

Local free-running operation timer, forms for generation of timestamp and participation output trigger impulse;

Synchronous fallout predictor, by the interval of the incoming sync pulse of estimating

there is the moment with main equipment lock-out pulse

predict new lock-out pulse due in

and carry out as required phase shift;

Output comparator, by continuous comparison with local free-running operation timer, in the time that the two is consistent, export synchronous trigger impulse;

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator,

The input input outer synchronous signal of marginal detector, the output of marginal detector is connected with timestamp record and parameter calculator, timestamp record and parameter calculator are connected with BlockRAM, local free-running operation timer respectively, the parameter output of timestamp record and parameter calculator is connected with synchronous fallout predictor, output comparator and sync pulse regenerator in turn, local free-running operation timer is also connected with output comparator, the pulse of sync pulse regenerator broadening output local synchronization.

Lock-out pulse jitter suppression method of the present invention, realize based on following temporal model, as shown in Figure 1, in figure, (a) represents benchmark lock-out pulse, (b), (c), (d) have demonstrated lock-out pulse and have arrived three kinds of situations that synchronous recipient occurs, the phase place that wherein (b) represents is leading, (c) represent that phase place lags behind, (d) represent that sync interval changes, assumes synchronization pulse produces equipment (hereinafter to be referred as main equipment) with interval (T _s) transmission lock-out pulse, corresponding moment t _{m_0}, t _{m_1}, t _{m_2}..., t _{m_n}, t _{m_n+1}..., t _{m_n+k-1}..., respectively corresponding moment t the synchronous recipient's (hereinafter to be referred as from equipment) of synchronizing signal quilt recovers ₀, t ₁, t ₂..., t _n, t _n+1..., t _n+k-1, lock-out pulse arrives the mixing that may show as during from equipment side as a kind of three kinds of situations of (b), (c), (d) that Fig. 1 enumerates or three kinds,

General hypothesis main equipment and from comprising a randomized jitter and constant offset between equipment, because fixing synchronously differing relatively easily measured and compensation, so it is 0 not affect Time-Series analysis that the present invention supposes the constant offset between master-slave equipment, temporal model can represent by simplification expression formula below:

t ₀＝t _{m_0}+ε ₀，

t ₁＝t _{m_1}+ε ₁＝t _{m_0}+T _s+ε ₁，

t ₂＝t _{m_2}+ε ₂＝t _{m_1}+T _s+ε ₂，….

t _n＝t _{m_n}+ε _n＝t _{m_1}+(n-1)T _s+ε _n，….

t _n+k＝t _{m_n+k}+ε _n+k＝t _{m_1}+(n+k-1)T _s+ε _n+k，….

Obviously ε ₀, ε ₁..., ε ₂..., ε _n..., ε _n+ka stochastic variable, sequence { t _nlinear growth in time, further, by continuous slippery sequence { t _ndata window, adopt up-to-date observation data to estimate can also effectively reduce the impact bringing of drifting about of principal and subordinate both sides' crystal from the new synchronization point of equipment.

Obtaining of timestamp is by realizing at the timer that builds an edge sense circuit and a free-running operation from the FPGA of equipment, in the time that synchronous edge detecting circuit detects a rising edge of external synchronization signal, the count value that just reads immediately local timer is stabbed as current time, and write inner BlockRAM, obtain thus one group of time stamp data, be designated as: t ₀, t ₁, t ₂..., t _n, t _n+1..., t _n+k-1, after external synchronization signal rising edge, the timestamp recording in BlockRAM is taken out to tectonic sequence { t _n;

Sequence { t _nalways take certain synchronization point of corresponding main equipment as benchmark linear growth, further build difference sequence { Δ t _nand consensus sequence { t _{s_n},

If Δ t _k=t _k-t _k-1, difference sequence { Δ t _nbe expressed as follows;

Δt ₁＝t ₁-t ₀＝T _s+(ε ₁-ε ₀)，

Δt ₂＝t ₂-t ₁＝T _s+(ε ₂-ε ₁)，

Δt ₃＝t ₃-t ₂＝T _s+(ε ₃-ε ₂)，…

Δt _n＝t _n-t _n-1＝T _s+(ε _n-ε _n-1)，…

Establish again t _{s_k}=t _k-kT _s, consensus sequence { t _{s_n}be expressed as follows:

t _{s_1}＝t ₁＝t _{m_1}+ε ₁，

t _{s_2}＝t ₂-T _s＝t _{m_1}+ε ₂，…

t _{s_n}＝t _n-(n-1)T _s＝t _{m_1}+ε _n，…

Wherein, t _{m_1}for corresponding t ₁time the outer lock-out pulse benchmark moment, ε ₁ε _nfor t _{s_1}t _{s_n}with respect to t _{m_1}randomized jitter, obviously difference sequence { Δ t _nthat average is T _srandom sequence, and consensus sequence { t _{s_n}that average is t _{m_1}random sequence, therefore available sequences { t _{s_n}average substitute main equipment lock-out pulse occur the moment

estimation, and with sequence { Δ t _naverage substitute interval to incoming sync pulse

estimation, obtain according to formula (1), (2),

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{t}_i=\frac{1}{n}[(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})]=\frac{(t_n-t_0)}{n}---\left(1\right)$

By choosing { t _nt ₀, t ₁, t ₂..., t _nn+1 observation data altogether, builds sequence { Δ t _nestimation sync interval

choose wherein from t ₁, t ₂..., t _nn observation data builds sequence { t altogether _{s_n}estimate main equipment lock-out pulse datum mark

build Linear Estimation equation

according to the lock-out pulse interval of having estimated

with the outer lock-out pulse benchmark moment

predict new lock-out pulse due in

(as needs phase shift can be calculating deduct again the phase-shift value of an expectation); Will

write the output register of output comparator.

Further, output comparator passes through ceaselessly the relatively current count value of output register and local timer, comparator trigger impulse in the time that the two is consistent, and sync pulse regeneration circuit is exporting local synchronization pulse after further trigger impulse broadening.Owing to directly not using external sync pulse, but utilized local clock signal estimation and recovered synchronizing signal by the method for Linear Estimation, so the shake of the synchronizing signal of regeneration is very little, time delay is adjustable.

The present invention is by having constructed two sequence { Δ t _nand { t _{s_n}simplify smoothing processing algorithm, but below in the time of specific implementation, some must be paid attention to:

(1). for avoid makeing mistakes in transmitting procedure and make mistakes in the time that device synchronization pulse edge recovers, before execution smoothing algorithm, should reject obviously abnormal point of interval;

(2). smooth effect and from the equipment output tracking time when length of data window can directly affect system and starts.While realization, can consider to adopt the method that becomes data window length, be W if establish the storage depth capacity of BlockRAM design, and current effective timestamp quantity is k, and the length n that constructs sequence of differences can consider to determine in the following method:

$n=\left\{\begin{array}{cc}k& k<W\\ W& k>=W\end{array}\right.$

(3). the bit wide that is used as the timer of local time stamp should be relevant with main equipment lock-out pulse interval and local crystal frequency with the BlockRAM storage depth of design, and while at least guaranteeing to record W timestamp while realization, the backrush phenomenon that makes zero does not appear in timer.

More than show and described basic principle of the present invention, principal character and advantage.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (4)

1. the lock-out pulse jitter suppression method based on FPGA, is characterized in that: comprises the following steps,

Step (1), detects the rising edge of outer lock-out pulse by marginal detector, and in the time that rising edge arrives, records the value of current free-running operation timer, and this value is stabbed to t as current time _n, write BlockRAM on the sheet of FPGA;

Step (2), after external synchronization signal rising edge, takes out tectonic sequence { t by the timestamp recording in BlockRAM _n;

Step (3), chooses { t _nt ₀, t ₁, t ₂..., t _nn+1 observation data altogether, structure difference sequence { Δ t _n, make Δ t _n=t _n-t _n-1, utilize { Δ t _naverage estimate the interval of incoming sync pulse

Step (4), chooses sequence { t _nt ₁, t ₂..., t _nn observation data builds consensus sequence { t altogether _{s_n}, make t _{s_1}=t ₁=t _{m_1}+ ε ₁, wherein, t _{m_1}for corresponding t ₁time the outer lock-out pulse benchmark moment, ε ₁ε _nfor t _{s_1}t _{s_n}with respect to t _{m_1}randomized jitter, and with { t _{s_n}estimation of Mean benchmark moment of going out main equipment lock-out pulse

Step (5), builds Linear Estimation equation

according to the lock-out pulse interval of having estimated

with the outer lock-out pulse benchmark moment

predict new lock-out pulse due in

Step (6), will

deduct the output register that needs to write after side-play amount output comparator;

Step (7), output comparator is the timer of more local free-running operation and the value of output register constantly, once the two is consistent, the pulse of triggering synchronous impulse regenerator broadening output local synchronization.

2. the lock-out pulse jitter suppression method based on FPGA according to claim 1, is characterized in that: step (3) is chosen { t _nt ₀, t ₁, t ₂..., t _nn+1 observation data altogether, builds difference sequence { Δ t _n, and utilize formula (1) to estimate the interval of incoming sync pulse

${\hat{T}}_s=\frac{1}{n}\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}\mathrm{\&Delta;}{t}_i=\frac{1}{n}[(t_1-t_0)+(t_2-t_1)+...+(t_n-t_{n-1})]=\frac{(t_n-t_0)}{n}---\left(1\right).$

3. the lock-out pulse jitter suppression method based on FPGA according to claim 1, is characterized in that: step (4) is according to sequence { t _{s_n}average, utilize formula (2) estimation main equipment lock-out pulse that the moment occurs

4. the system of the operation lock-out pulse jitter suppression method based on FPGA claimed in claim 1, is characterized in that: be included in build in fpga chip with lower member,

Marginal detector, is used for detecting the rising edge triggered time stamp record simultaneously of outer lock-out pulse;

Timestamp record and parameter calculator, for recording the interval of outer lock-out pulse due in the outer lock-out pulse of estimation

with the benchmark moment of outer lock-out pulse

BlockRAM, is positioned at RAM resource on FPGA sheet, is used for stabbing memory time data;

Local free-running operation timer, forms for generation of timestamp and participation output trigger impulse;

Synchronous fallout predictor, by the interval of the incoming sync pulse of estimating

there is the moment with main equipment lock-out pulse

predict new lock-out pulse due in

and carry out as required phase shift;

Output comparator, by continuous comparison

with local free-running operation timer, in the time that the two is consistent, export synchronous trigger impulse;

Sync pulse regenerator, broadening output local synchronization pulse under the triggering of output comparator;

The input input outer synchronous signal of described marginal detector, the output of marginal detector is connected with timestamp record and parameter calculator, described timestamp record and parameter calculator are connected with BlockRAM, local free-running operation timer respectively, the parameter output of described timestamp record and parameter calculator is connected with synchronous fallout predictor, output comparator and sync pulse regenerator in turn, described local free-running operation timer is also connected with output comparator, the pulse of described sync pulse regenerator broadening output local synchronization.

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