CN103904032B - Flash memory cell and preparation method thereof - Google Patents
Flash memory cell and preparation method thereof Download PDFInfo
- Publication number
- CN103904032B CN103904032B CN201210576659.2A CN201210576659A CN103904032B CN 103904032 B CN103904032 B CN 103904032B CN 201210576659 A CN201210576659 A CN 201210576659A CN 103904032 B CN103904032 B CN 103904032B
- Authority
- CN
- China
- Prior art keywords
- grid structure
- preparation
- contact hole
- separation layer
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 239000010410 layer Substances 0.000 claims abstract description 82
- 238000000926 separation method Methods 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 230000008021 deposition Effects 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 8
- 239000007792 gaseous phase Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000001936 parietal effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000008034 disappearance Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a kind of flash memory cell and preparation method thereof. Wherein, this preparation method is included in and on substrate, forms grid structure and between grid structure, form contact hole, and the preparation of contact hole comprises the following steps: on the substrate with grid structure, deposition forms interlayer dielectric layer and photoresist; Interlayer dielectric layer to the first height and position taking photoresist between mask etching grid structure, and make to remain between grid structure part interlayer dielectric layer; Then deposition forms separation layer; Separation layer between etching removal grid structure and residual interlayer dielectric layer; And filled conductive material forms contact hole between grid structure. By interlayer dielectric layer etching to the first height and position, and make to remain part interlayer dielectric layer between grid structure, deposition forms separation layer. The existence of this separation layer can not be etched protective side wall layer excessively in the preparation process of contact hole, thereby has avoided the phenomenon being short-circuited between contact hole and control gate.
Description
Technical field
The present invention relates to semiconductor devices and manufacturing technology field thereof, in particular to a kind of flash memory cell and preparation thereofMethod.
Background technology
Great scale integrated circuit technique resolution ratio will develop into below 0.18 micron at present, i.e. the ratio of the degree of depth to width or diameterExample is increasing, and metal and semi-conductive contact hole are also more and more less, and the manufacture craft of contact hole becomes one of maximum difficult point.
In order to overcome more and more less live width and to prevent contact hole generation aligning mistake, many semiconductor elements can adopt certainly conventionallyAim at the design of contact hole. Particularly in flash element, by the source/drain in substrate and the bit line electricity that is formed on substrate topProperty connects, and conventionally uses the design of self-aligned contacts window, and self-aligned contacts window is formed between two adjacent grid structures. LogicalNormal flash memory cell comprises and is arranged on the grid structure on substrate and is arranged on the contact hole between grid structure, wherein, and gridElectrode structure comprises division center and is arranged on the side wall layer of division center both sides, and division center comprises and is successively set on from bottom to up instituteState floating boom, insulating barrier and control gate on substrate. But, in the manufacturing process of flash memory, in high density storage unit area,Adopt self aligned method to make contact hole, because contact hole is less, or etching extent control inaccuracy, in the preparation of contact holeIn process, also can cause gate lateral wall layer disappearance to a certain degree, expose part control gate, thereby cause contact hole and control gateBetween be short-circuited.
Summary of the invention
The present invention aims to provide a kind of flash memory cell and preparation method thereof, to solve in prior art in self aligned method systemDo easily to cause the technical problem being short-circuited between contact hole and control gate in the process of contact hole.
To achieve these goals, according to an aspect of the present invention, provide a kind of preparation method of flash memory cell. ShouldMethod is included in and on substrate, forms grid structure and between grid structure, form contact hole, and the preparation of contact hole comprises the following steps:On the substrate with grid structure, deposition forms interlayer dielectric layer and photoresist; Taking photoresist between mask etching grid structureInterlayer dielectric layer to the first height and position, and make to remain between grid structure part interlayer dielectric layer; Then deposition form everyAbsciss layer; Separation layer between etching removal grid structure and residual interlayer dielectric layer; And between grid structure filled conductiveMaterial forms contact hole.
Further, grid structure comprises division center and is arranged on the side wall layer of division center both sides, division center comprise underSupreme floating boom, insulating barrier and the control gate being successively set on substrate, the first height and position is positioned at control gate lower surface placeBelow horizontal plane.
Further, separation layer forms by deposition of dielectric materials.
Further, dielectric material is silicon nitride, silica or silicon oxynitride.
Further, the thickness of separation layer is 100 ~ 200 dusts.
Further, separation layer is by chemical vapour deposition (CVD), plasma enhanced chemical gaseous phase deposition and/or high-density plasmaChemical gaseous phase deposition forms.
Further, the conductive material of formation contact hole is tungsten.
According to another aspect of the present invention, provide a kind of flash memory cell. This flash memory cell comprises and being arranged on substrateGrid structure and be arranged on the contact hole between grid structure, wherein, grid structure comprises division center and is arranged on centerThe side wall layer of structure both sides, division center comprises the floating boom, insulating barrier and the control gate that are successively set on from bottom to up on substrate,The arranged outside of the corresponding control gate of side wall layer has separation layer.
Further, separation layer is formed by dielectric material.
Further, dielectric material is silicon nitride, silica or silicon oxynitride.
Further, the thickness of separation layer is 100 ~ 200 dusts.
Apply technical scheme of the present invention, the interlayer dielectric layer substep in the preparation process of contact hole between grid structure is removed,And first by interlayer dielectric layer etching to the first height and position of this part, and make to remain between grid structure part interlayer dielectricLayer, deposition forms separation layer. The existence of this separation layer can not be etched protective side wall layer excessively in the preparation process of contact hole,Thereby avoid the phenomenon being short-circuited between contact hole and control gate. In addition, due to also residual between grid structure after etching firstLeave part interlayer dielectric layer, when etching is removed the separation layer between grid structure in subsequent step like this, remain part folderLayer dielectric layer can protect substrate can not damaged by overetch.
Brief description of the drawings
The Figure of description that forms the application's a part is used to provide a further understanding of the present invention, schematic reality of the present inventionExecute example and explanation thereof for explaining the present invention, do not form inappropriate limitation of the present invention. In the accompanying drawings:
Fig. 1 to Fig. 6 shows the preparation flow figure according to the flash memory cell of the embodiment of the present invention.
Detailed description of the invention
It should be noted that, in the situation that not conflicting, the feature in embodiment and embodiment in the application can combine mutually.Describe below with reference to the accompanying drawings and in conjunction with the embodiments the present invention in detail.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " above" etc., be used for describing as the spatial relation of a device shown in the figure or feature and other devices or feature. Should manageSeparate, space relative terms is intended to comprise the difference in using or operating except the described in the drawings orientation of deviceOrientation. For example, if the device in accompanying drawing is squeezed, be described as " above other devices or structure " or " at other devices orOn structure " device after will be positioned as " other devices or structure below " or " other devices or construct under ". Thereby,Exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation. This device also can otherDifferent modes location (90-degree rotation or in other orientation), and make corresponding to the space relative descriptors that used hereExplain.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention. But, these exemplary embodimentsCan be implemented by multiple different form, and should not be interpreted as being only limited to the embodiments set forth herein. Be to be understood that, provide these embodiment be for make of the present invention disclose thorough and complete, and by the structure of these exemplary embodimentsThink fully to convey to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expanded the thickness in layer and region, andAnd use identical Reference numeral to represent identical device, thereby will omit description of them.
A kind of typical embodiment according to the present invention, provides a kind of preparation method of flash memory cell. This preparation method comprisesOn substrate, form grid structure and between grid structure, form contact hole 70, the preparation of contact hole 70 comprises the following steps:There is deposition on the substrate of grid structure and form interlayer dielectric layer 50 and photoresist; Taking photoresist between mask etching grid structureInterlayer dielectric layer 50 to first height and positions, and make to remain between grid structure part interlayer dielectric layer 50; Then deposit shapeBecome separation layer 60; Separation layer 60 between etching removal grid structure and residual interlayer dielectric layer 50; And at grid structureBetween filled conductive material form contact hole 70. " the first height and position " alleged in the present invention refers to energy in the process of etchingEnough ensure side wall layer sufficiently complete form, the height and position that interlayer dielectric layer 50 is etched. The existence of this separation layer 60 will be protectedSide wall layer 40 can not be etched excessively in the preparation process of contact hole 70, thus avoided contact hole 70 and control gate 30 itBetween the phenomenon that is short-circuited. In addition, owing to also remaining part interlayer dielectric layer 50 between grid structure after etching first, like thisWhen etching is removed the separation layer 60 between grid structure in subsequent step, remain part interlayer dielectric layer 50 and can protect liningThe end, can not damaged by overetch. Conventionally, in the substrate of flash memory, can also have cobalt silicide, if substrate is damaged by overetch,In the follow-up operation that need to enter boiler tube, cobalt silicide can spread, boiler tube environment and semiconductor devices are polluted,By remaining part interlayer dielectric layer 50, the protection of substrate is just avoided in the present invention the appearance of this technical problem.
Preferably, grid structure comprises division center and is arranged on the side wall layer 40 of division center both sides, division center comprise underSupreme floating boom 10, insulating barrier 20 and control gate 30, the first height and positions that are successively set on substrate are positioned at control gate 30 timesBelow the horizontal plane at place, surface. Etching in this degree, both can ensure to facilitate the integrality of side wall layer 40 again rearWhen etching is removed the separation layer 60 between grid structure in continuous step, remain part interlayer dielectric layer 50 and can protect substrate notCan be damaged by overetch, this residual fraction interlayer dielectric layer 50 can be removed completely simultaneously.
As long as the separation layer in the present invention 60 can play the protection of offside parietal layer 40, so more more fine and close when deposition formsGood, and the phenomenon that can not make to be short-circuited between grid structure and contact hole 70, preferably, separation layer 60 passes through deposit dielectric materialMaterial forms, and like this, even offside parietal layer 40 has caused certain damage in etching process first, has the isolation of dielectric materialThe contact hole 70 of follow-up formation also not can and grid structure between be short-circuited. Preferably, dielectric material is selected from silicon nitride, oxidationSilicon or silicon oxynitride, these material compactness are high, good insulation preformance. Preferably, the thickness of separation layer 60 is 100 ~ 200 dusts,Effectively isolated insulation, is unlikely to again to affect the filling of contact window and tungsten. Separation layer 60 in the present invention can be by existingThe whole bag of tricks in technology forms, preferably, separation layer 60 by chemical vapour deposition (CVD), plasma enhanced chemical gaseous phase deposition,And/or high-density plasma chemical gaseous phase deposition forms. Contact hole 70 in the present invention, can select general conductive material to form,Preferably, the conductive material of contact hole 70 is tungsten, because tungsten has reasonable fillibility, price is also relatively cheap.
According to the present invention, a kind of typical embodiment, provides a kind of flash memory cell. This flash memory cell comprises and being arranged onGrid structure on substrate and be arranged on the contact hole 70 between grid structure, wherein, grid structure comprises division center and establishesPut the side wall layer 40 in division center both sides, division center comprises the floating boom 10, the insulating barrier that are successively set on from bottom to up on substrate20 and control gate 30, the arranged outside of the corresponding control gate 30 of side wall layer 40 has separation layer 60. The existence of this separation layer 60 willProtective side wall layer 40 can not be etched excessively in the preparation process of contact hole 70, thereby has avoided contact hole 70 and control gate 30Between the phenomenon that is short-circuited.
Like this, even offside parietal layer 40 has caused certain damage in etching process first, there is the isolation of dielectric material follow-upForm contact hole 70 also not can and grid structure between be short-circuited. Preferably, dielectric material be selected from silicon nitride, silica orSilicon oxynitride, these material compactness are high, good insulation preformance.
Preferably, the thickness of separation layer 60 is 100 ~ 200 dusts, effectively isolated insulation, be unlikely to again to affect contact window andThe filling of tungsten.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for those skilled in the art, the present invention can have various modifications and variations. Within the spirit and principles in the present invention all, any amendment of doing, etc.With replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. a preparation method for flash memory cell, is included in and on substrate, forms grid structure and form between described grid structureContact hole (70), is characterized in that, the preparation of described contact hole comprises the following steps:
On the described substrate with described grid structure, deposition forms interlayer dielectric layer (50) and photoresist;
Described interlayer dielectric layer (50) taking described photoresist between grid structure described in mask etching is to the first height positionPut, and make to remain between described grid structure the described interlayer dielectric layer of part (50);
Then deposition forms separation layer (60);
Etching is removed separation layer (60) between described grid structure and residual described interlayer dielectric layer (50); And
Between described grid structure, filled conductive material forms described contact hole (70).
2. preparation method according to claim 1, is characterized in that, described grid structure comprises division center and is arranged on instituteState the side wall layer (40) of division center both sides, described division center comprises and is successively set on from bottom to up floating on described substrateGrid (10), insulating barrier (20) and control gate (30), described the first height and position is positioned at described control gate (30) following tableBelow the horizontal plane at face place.
3. preparation method according to claim 1, is characterized in that, described separation layer (60) is by deposition of dielectric materials shapeBecome.
4. preparation method according to claim 3, is characterized in that, described dielectric material is silicon nitride, silica or nitrogenSilica.
5. preparation method according to claim 1, is characterized in that, the thickness of described separation layer (60) is 100～200 dusts.
6. preparation method according to claim 1, is characterized in that, described separation layer (60) is by chemical vapour deposition (CVD) shapeBecome.
7. preparation method according to claim 6, is characterized in that, described separation layer (60) is by plasma enhancingGaseous phase deposition forms.
8. preparation method according to claim 7, is characterized in that, described separation layer (60) is by high-density plasmaGaseous phase deposition forms.
9. preparation method according to claim 1, is characterized in that, the conductive material that forms described contact hole (70) is tungsten.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210576659.2A CN103904032B (en) | 2012-12-26 | 2012-12-26 | Flash memory cell and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210576659.2A CN103904032B (en) | 2012-12-26 | 2012-12-26 | Flash memory cell and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103904032A CN103904032A (en) | 2014-07-02 |
| CN103904032B true CN103904032B (en) | 2016-05-04 |
Family
ID=50995293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210576659.2A Active CN103904032B (en) | 2012-12-26 | 2012-12-26 | Flash memory cell and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103904032B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336702B (en) * | 2014-08-01 | 2019-04-09 | 上海格易电子有限公司 | A kind of fill method of flash memory interlayer dielectric layer |
| CN105575783B (en) * | 2014-10-09 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic device |
| CN105655343A (en) * | 2016-03-03 | 2016-06-08 | 上海格易电子有限公司 | Flash memory and manufacturing method thereof |
| CN107421655B (en) * | 2017-07-05 | 2020-02-21 | 中国科学院苏州生物医学工程技术研究所 | Even-order Lamb wave generating device and temperature detection system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6228738B1 (en) * | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Methods of forming capacitors structures and DRAM cells |
| CN1677678A (en) * | 2004-03-29 | 2005-10-05 | 力晶半导体股份有限公司 | Flash memory unit and mfg. method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100543471B1 (en) * | 2003-12-30 | 2006-01-20 | 삼성전자주식회사 | Method of forming contact structure of a nor-type flash memory cell |
-
2012
- 2012-12-26 CN CN201210576659.2A patent/CN103904032B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6228738B1 (en) * | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Methods of forming capacitors structures and DRAM cells |
| CN1677678A (en) * | 2004-03-29 | 2005-10-05 | 力晶半导体股份有限公司 | Flash memory unit and mfg. method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103904032A (en) | 2014-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103681687B (en) | Three-dimensional semiconductor devices and its manufacture method | |
| CN107919362A (en) | Semiconductor storage unit | |
| CN104347592A (en) | Semiconductor device with air gap and method for fabricating the same | |
| CN105321874A (en) | Self-aligned double patterning | |
| CN103904032B (en) | Flash memory cell and preparation method thereof | |
| KR20140077501A (en) | Resistance Memory Device and Fabrication Method Thereof | |
| CN106206445A (en) | The forming method of memory construction | |
| CN102117776A (en) | Stacked capacitor structure of embedded type grid word line device and manufacturing method of capacitor | |
| US8183146B2 (en) | Manufacturing method for a buried circuit structure | |
| CN104051331B (en) | Damascus semiconductor device of 3D array and forming method thereof | |
| CN103178019A (en) | Method for manufacturing word lines of embedded flash memory | |
| CN104377202A (en) | Embedded storage component and manufacturing method thereof | |
| CN110085737A (en) | Magnetic random access memory and preparation method thereof | |
| CN102969447A (en) | Method for forming conductive plug on surface of magnetic tunnel junction (MTJ) | |
| CN104377160B (en) | Metal interconnector structure and process thereof | |
| US10475808B2 (en) | Three dimensional memory device and method for fabricating the same | |
| CN103165518B (en) | Manufacturing method of interconnected structure | |
| CN102543878B (en) | Manufacturing method of storage | |
| CN106611709B (en) | A kind of semiconductor devices and preparation method thereof, electronic device | |
| CN112635659B (en) | Semiconductor structure and forming method thereof | |
| TW202207370A (en) | Semiconductor device with landing pad of conductive polymer and method for fabricating the same | |
| KR20110001136A (en) | Method for manufacturing semiconductor device | |
| CN101211919A (en) | Semiconductor device | |
| US20130119545A1 (en) | Semiconductor device and method for forming the same | |
| CN105514027B (en) | Semiconductor devices and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |