CN103887277B - Packaging Structure And Method Of Assembling A Packaging Structure - Google Patents
Packaging Structure And Method Of Assembling A Packaging Structure Download PDFInfo
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- CN103887277B CN103887277B CN201310584975.9A CN201310584975A CN103887277B CN 103887277 B CN103887277 B CN 103887277B CN 201310584975 A CN201310584975 A CN 201310584975A CN 103887277 B CN103887277 B CN 103887277B
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Abstract
The present invention relates a packaging structure and a method of assembling a packaging structure. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.
Description
Technical field
The present invention relates to encapsulating structure.More particularly it relates in the respective active table of the first and second chips
There is the encapsulating structure of directly electrical connection between face and at least one of first and second chips and common chip between.
Background technology
With complementary metal oxide semiconductors (CMOS)（CMOS）The diminution of device size, chip packaging method is studied with raising
Systematic function.In some cases, chip-stack includes multiple chips of arranged side-by-side to form module, and module side arranges public
Common chip.The block is connected to into wiring board then along the block side relative with common chip.
Including common chip and to be arranged side-by-side the chip-stack of multiple chips of setting in, substantial amounts of silicon is packed simultaneously
Interconnection.However, passing through public（That is, push up）The interconnection of chip is intersected by turning（corner crossing）The restriction of density.Separately
Outward, because the direction of power transmission is vertical orientated along the vertical length of each in multiple chips, common chip is arrived
Power conveying also has challenge.
The content of the invention
According to one embodiment of present invention, there is provided a kind of encapsulating structure, and the encapsulating structure includes first and the
Two chips, at least one surface of each in the first and second chips is active surface；And common chip, first and
At least one of two chips are electrically interconnected the common chip.The respective active surface of first and second chip with
It is electrically interconnected directly with one another and relative to the common chip horizontal orientation in arranging face-to-face.
According to another embodiment, there is provided a kind of encapsulating structure, and the encapsulation include the first and second chips, first
And second each in chip include four side walls there are two apparent surfaces and extend between two apparent surfaces
Body, at least one of each two apparent surfaces in the first and second chips are active surfaces；And common core
At least one of piece, respective side wall of the first and second chips are electrically interconnected the common chip.Described first and
The respective active surface of two chips be electrically interconnected directly with one another and laterally takes relative to the common chip with being arranged face-to-face
To.
According to another embodiment, there is provided a kind of encapsulating structure, and the encapsulating structure includes the first and second chips
Group, each chipset at least includes the first and second chips, and each in the first and second chips of each chipset is extremely
A few surface is active surface, and the respective active surface of the first and second chips of each chipset is arranging face-to-face that
This is directly electrically interconnected；And bonding layer, the first and second chipsets are attached to each other by bonding layer.
According to another embodiment, there is provided a kind of encapsulating structure, and the encapsulating structure includes the first and second chips
Group, each chipset includes at least the first and second chips, and each in the first and second chips of each chipset is extremely
A few surface is active surface, and the respective active surface of the first and second chips of each chipset is arranging face-to-face that
This is directly electrically interconnected；And bonding layer, the first and second chipsets are attached to each other by bonding layer.
According to another embodiment, there is provided a kind of method of assembled package structure, it includes arranging direct face-to-face
The respective active surface of the first and second chips is electrically interconnected, by the respective side wall of at least one of the first and second chips
Common chip is electrically interconnected, and relative to the respective active surface of the chip of common chip horizontal orientation first and second.
Other feature and advantage will be recognized that by the technology of the present invention.Other embodiments of the invention and aspect are at this
In be described in detail and be considered a part of the claimed invention.Advantage for a better understanding of the present invention and spy
Levy, with reference to description and accompanying drawing.
Description of the drawings
The purport for being considered as the present invention is pointed out and claimed to description claims at the conclusion.By subsequently contact
The detailed description of accompanying drawing is readily apparent that the foregoing and other advantages of the present invention.
Fig. 1 shows the perspective view of the encapsulating structure according to embodiment；
Fig. 2 shows the side view of the encapsulating structure of Fig. 1 that power conversion chip is faced upwards；
Fig. 3 shows the perspective view of the chipset according to embodiment；
Fig. 4 shows the perspective view of the chipset of the Fig. 3 with additional filler thing；
Fig. 5 shows the top view of the encapsulating structure according to another embodiment；
Fig. 6 shows the perspective view of the encapsulating structure according to another embodiment；
Fig. 7 shows the top view of the chipset with the first and second chips and additional chips；
Fig. 8 shows the perspective view of the first process operation for assembled package structure；
Fig. 9 shows the perspective view operated for the second processing of assembled package structure；
Figure 10 shows the perspective view of the 3rd process operation for assembled package structure；And
Figure 11 shows the perspective view operated for the fourth process of assembled package structure.
Specific embodiment
In the such as chip-stack of 4Di chip-stacks, form be with commonly（Top）Multiple chips of chip arranged side-by-side
Substantial amounts of silicon is packed and interconnects the area multiplication for providing about 8.5X or bigger, with for 4Di chip-stacks and public
The 57.6k connections of both power and communications between chip.However, the interconnection through common chip intersects density restriction by turning
And because it is that the vertical length direction of each is vertical orientated along multiple chips that power is transported, to the work(of common chip
Rate is transported and faced the challenge.
According to the embodiments described herein, there is provided a kind of chip-stack and be presented as 4Di chip-stacks, it include with
At least active surface is to active surface（I.e., face-to-face）Packet is arranged and with the conducting element for arranging between them（For example
Little pitch microprotrusion or micro-force sensing）Multiple chips.This is in chip pair（Or, more specifically, two or more chips point
Group）Between relatively high bandwidth is provided connects and can be used in, for example, power conversion either memory chip or is included
Chip such as decoupling capacitor or the integrated passive devices of inducer is attached to processor chips.Also effectively multiplication can for this
The active region of the chip being closely electrically interconnected with other modules.In addition, chip-stack provides each chip pair or 30 or more multicore
At least 28.8k connections of the chip chamber of piece centering, the total connection for use in chip-stack is at least 864k.In addition, facing core
The use of piece pair is favourable, because being symmetrical arranged so that any stress induced bending is compensated for.
With reference now to Fig. 1 and 2, there is provided encapsulating structure 10 is used as exemplary chip-stack.Encapsulating structure 10 at least includes one
Pair or multipair first chip 11, the second chip 12 and in some cases, common chip 12, itself and one or more chips pair
The first and second chips 11 and 12 of each at least one can connect.In first and second chips 11 and 12 at least one
It is individual including at least one of voltage conversion device 14, control device 15 and storage component part 16.The He of first and second chip 11
At least one of 12 also include power conversion chip 17, its be configured to convert input voltage into first voltage range with to
Another second voltage scope of powering and convert input voltage in first and second chips 11 and 12 is with using public
Power to common chip 13 during chip 13 altogether.
First chip 11 include with therein at least one be active surface 112 two apparent surfaces 111 and four
First chip body 110 of side wall 113.Four side walls 113 extend between two apparent surfaces 111.Second chip 12 is similarly
Including second chip body of two apparent surfaces 121 and four side walls 123 for wherein at least one being active surface 122
120.Equally, four side walls 123 extend between two apparent surfaces 121.Though it is shown that the first and second chips 11 and 12
It is rectangle, it shall be understood that this is exemplary and it is likely to be other configurations.For exemplary rectangle situation, the
One and second chip 11 and 12 be oriented to and make one in side wall 113 and 123 to be " top " side wall 113,123 and relative one
It is " bottom " side wall 113,123.
For every a pair of chips, each side wall 113 and at least one of 123 of the first and second chips 11 and 12（That is,
" top " side wall 113,123）For example, by 25 microns（μm）Pitch turning intersects electrical interconnection（Or be at least configured to be electrically interconnected）
To the active surface 130 of common chip 13.That is, in a particular configuration, only in the first chip 11 or the He of the second chip 12
Intersected by 25 microns of pitch turnings between common chip 13 and turning is provided intersects, thus only one chip be directly connected to it is public
Chip 13, other chips are connected indirectly to common chip 13.
In addition, the respective active surface 112 and 122 of the first and second chips 11 and 12 is set with active surface to active table
Put（It is hereinafter referred to " face-to-face " to arrange）Directly it is electrically interconnected to each other.The respective active table of the first and second chips 11 and 12
Plane horizontal orientation of the face 112 and 122 relative to the active surface 130 of common chip 13.Can serve as a contrast in the encapsulation of such as first order
Bottom（Referring to the label 201 of Fig. 6）With the respective opposite side wall 113 and 123 of the first and second chips 11 and 12（That is, " bottom " side
Wall 113 and 123）Between controlled collapse chip connection is provided（C4）Array 20.There is provided wider pitch turning to intersect, e.g., from about
100 microns of pitch, so that the active surface 112 and 122 of the first and second chips 11 and 12 is electrically interconnected to the correspondence He of downside wall 113
123 and C4 arrays 20.
Bending in of first and second chips 11 and 12 can be by the another of the first and second chips 11 and 12
Bending in one is compensated for.Alternatively, bending can pass through the first and second chips 11 and 12 in another be corrected or
Tensioning.
At least one microprotrusion 18 or micro-force sensing can be distributed between the first and second chips 11 and 12.In order to clear
With succinct purpose, the embodiment of non-limiting microprotrusion 18 will be described here, it is not intended that limiting or exclusive.Can be with
Microprotrusions 18 are provided with such as 50 μm pitch and microprotrusion can serve as electric conductor, by the electric conductor by the first and second chips
11 and 12 respective active surface 112 and 122 is directly electrically interconnected mutually.According to embodiment, microprotrusion 18 can be with 75 μm
Pitch is inserted between the first and second chips 11 and 12 and common chip 13.
For one embodiment, wherein at least one of the first and second chips 12 and 13 includes power conversion chip 17,
It is configured to change input voltage to first and second or the voltage range of more with respectively to the first and second chips
Another and common chip 13 in 11 and 12 is powered, first and second or more voltage ranges can be independent.In addition,
It should be understood that using this arrangement, very little will be had in the microprotrusion 18 between the first and second chips 11 and 12 being electrically interconnected
Resistive voltage（I×R）Loss.For common chip 13, " top " edge along respective active chip surface 112 or 122 is carried
Voltage supplied either power transition region 131 and on the respective active chip surface 112 or 122 of power conversion chip 17
There is provided under region 131 for engagement in the face of chip（the facing chip）Power transition region 132
（Referring to Fig. 2）.Therefore, can be intersected by corresponding turning to the electric current of the transmission of common chip 13 and microprotrusion 18 is transmitted.Electricity
Pressure converter part 14 and control device 15 can be used as such as switching capacity power supplys or step-down controller power supply.
According to embodiment, the first and second chips 11 and 12 can be provided in the form of chip pair.Can be by by chip
It is bonded together or by the way that single chip is bonded together to form chip pair.It is high that chip connection method is adapted to die yield
Situation because the defective chip on any chip can cause the chip pair of defect.Using single chip technology, Ke Yicong
Each initial wafer selects known good chip and is subsequently assembled.According to assembling yield, expect be assembled into chip-stack
（That is, 4Di modules）Front test chip pair.By causing a chip at least on a yardstick another can be slightly less than in list
This point is realized in only chip technology, and this can cause to produce the probe lining that can be used to test.Then, subsequently by other
Silicon " implant " section fills probe liner.By falling and using TCA from a chip cutting by edge（Interim chip attachment；
In small size liner）Type joint liner exposes test pads and subsequently backfills silicon will pass through the chip section for removing cutting
" implant " section, the variant of this technique can be used for chip engagement situation.Implant edge should be slightly inside the bottom chip edge of than
To allow the accurate assembling of 4Di chip-stacks.
Fig. 3 and 4 shows the embodiment of above-mentioned technique.Specifically, Fig. 3 and 4 shows that chip can be used as demonstration to 30
Property chipset provide.As shown in figure 3, one of the first and second chips 11 and 12 can be less than first at least one yardstick
With the second chip 11 and 12 another.That is, the first chip 11 can be more shorter than the second chip 12 on vertical scale, this conduct
First chip 11 is manufactured to be different from the second chip 12 so as to the short result of the chip 12 of the first chip 11 to the second or conduct
The result that the end section of the first chip 11 is cut off.In either case, the expose portion 21 of the second chip 12 can serve as
Probe or test pads.Once completing detection or testing, implant 22 can be added to the first chip 11 to cover the
The expose portion 21 of two chips 12, as shown in Figure 4.
According to alternative embodiment, can be without the implant 22 of Fig. 4.Conversely, with reference to Fig. 5, the exposure of the second chip 12
Part 21 may be electrically coupled to another neighbouring chip to 30 another second chip 12 complementary expose portion 21.Such as Fig. 5
Shown, at the complementary expose portion 21 of respective second chip 12, two chips are formed to 30 cooperations and overlapped（lap joint）
35.In given encapsulating structure, this arrange each chip can be repeated to 30 so as to formed multiple overlap joints 35 and so as to
The width of given encapsulating structure, active region and total connection is corresponding increases.
With reference to Fig. 6, encapsulating structure 10 can also include carrier chip 40.Carrier chip 40 can be by as having such as 75
The conducting element of the microprotrusion 18 of μm pitch is electrically interconnected the He of respective " bottom " side wall 113 to the first and second chips 11 and 12
123 such that it is able at both places of respective " top " and " bottom " side wall 113 and 123 using 25 μm of pitch turnings intersections so as to the envelope that doubles
The quantity of the possible connection that assembling structure 10 is provided.Carrier chip 40 can be formed and can be limited silicon hole by silicon（TSV）
And further include to be electrically connected to the conducting element of the first and second chips by TSV.Can be in encapsulating structure 10 and first
C4 arrays 20 are provided on " bottom " surface of carrier chip 40 between level package substrate 201.TSV's in carrier chip 40 makes
With the simplification allowed using more inexpensive material and first order package substrate.
Still referring to Fig. 6, and according to another embodiment, encapsulating structure 10 can include " T " adapter 50.These " T " are even
Connecing device 50 can be along respective " top " and/or " bottom " of neighbouring one of the first and/or second chip 11 and 12（That is, it is long）
Side wall 113 and 123 is arranged and is configured to supply and vertically and horizontally connects." T " adapter 50 can by with one or
The multi-layer ceramics of the wiring on multiple surfaces, the glass/silicon insert of two or more engagements are formed.In this embodiment,
" T " adapter 50 can be used for substituting in active chip surface 112 and 122 and the active surface 130 towards common chip 13
" top " side wall 113 and 123 between " turning intersection " and on active chip surface 112 and 122 and towards carrier chip 40
Turning between " bottom " side wall 113 and 123 intersects." T " adapter 50 can provide electrical connection between adjacent chip is to 30
（That is, level connection joint）And/or in chip to 30 and common plunger tip piece 13 either carrier chip 40 or if there is no support core
Electrical connection is provided between package substrate 201 during piece 40（That is, the combination of horizontal and vertical connection）." T " adapter 50 can be even
Chip is connected to 30（112 or 122）Respective active surface, they adjacent to common chip 13 active surface 130 and make
The active surface 130 of common chip 13 is connected to the microprotrusion 18 or C420 of suitable dimension and pitch.Similar connection can be with
It is fabricated onto carrier chip 40 or package substrate 201.
Although the chipset for being described above and illustrating in figs. 1-6 is generally referred to as chip to 30 or referred to as first He
I and chip 11 and 12, it shall be understood that this embodiment only demonstrate and there may be in given chipset two or
Other settings of more chips.That is, with reference to Fig. 7, given chipset can include the first and second chips 11 and 12 and
Individual or multiple additional chips 60.This additional chip 60 can be arranged between the first and second chips 11 and 12 and by shape
Become restriction TSV61, it is possible to communicating between the first and second chips 11 and 12.In any case, should also be bright
White encapsulating structure 10 generally includes the list in multiple chipsets and encapsulating structure 10 of the length arrangement along common chip 13
Solely chipset can include the chip of varying number.
With reference to Fig. 8-11, optional encapsulating structure 1000（Referring to Figure 11）Can be formed by chipset, wherein each chip
Group includes two the first chips 1100 and two the second chips 1200.The technique of the such configuration of assembling is described below.
Start, as shown in figure 8, the first chip 1100 and the second chip 1200 are electrically interconnected to form first by microprotrusion 18
To 70, as mentioned above.First chip 1100 and the second chip 1200 is rotated relatively to each other 90 degree and shape is essentially rectangular（Though
So do not require so）.This defines expose portion 21 in the relative distal end of the second chip 1200, wherein the second chip 1200
Opposite proximal end extend beyond the side wall of the first chip 1100.As shown in figure 9, subsequently insertion block 71 is attached to the second chip 1200
Expose portion 21.For up to 100-200 μm of pitch, can provide convex containing the solder with above-mentioned similar pitch characteristic
Play 72 or the insertion block 71 of other electric connectors.Insertion block 71 can be by the glass with conductive via, with conductive via
Silicon, the ceramics with conductive via, PCB/ Organic substances lamination/flexible body（flex）, etc. formed.
With reference to Figure 10, the second couple 80 for the first and second chips 1100 and 1200 being mutually electrically interconnected by microprotrusion 18 can
To be attached on first pair 70.The expose portion 21 of second chip 1200 of second pair 80 passes through solder bump 72 or other are electrically connected
Connect device and be connected to insertion block 71.Thermal bonding layer 81 is formed between first and second pairs 70 and 80 two the first chips 1100.
Thermal bonding layer can be solder layer, filling hot adhesion agent, such as silver epoxy（epoxy）Or with such as low-melting-point metal
Or the particles filled epoxy resin of thermal conducting of alloy.It is alternatively possible in first and second pairs 70 and 80 non-active master meter
Fluid passage and dielectric fluid are formed on face can be flow through for cooling purposes.As shown in figure 11, the technique can continue with
For other right.
The encapsulating structure 1000 illustrated in Fig. 8-11 allows to be electrically connected to form core by between all chips in stacked
Piece lamination and do not use silicon hole." bottom " chip faces down towards lower surface or in " top " chip of " bottom " chip centering
Expose portion 21 can be installed to package substrate 2010 and provide power and communication to chip-stack using C42000.Insertion block 71
Can be including the flexible connection 710 at other in being attached to package substrate 2010 or system, so as to directly to lamination
In chip to power and communication is provided and by chip and insertion block relatively low in lamination.
For example, as shown in figure 11, insertion block 71 can include being attached to the flexibility of package substrate 2010 on one or more
Connection 710.In addition, one or more insertion blocks 71 can include that being attached to other insertion blocks 71 or the flexible of system unit connects
Connect 710.System unit can including but not limited to, wiring board, storage component part, power supply, input/output（I/O）Device
And/or electric to optic converter.
This is that the term for using is only used for describing the purpose of specific embodiment and is not intended to limit the present invention.As here
Use, except otherwise singulative " one " " one " being clearly indicated in non-content and " this " is intended to also include most forms.Also
It should be understood that term " including " and/or "comprising", when using in this description, refer specifically to state feature, integer, step,
Operation, the presence of element and/or part, but be not excluded for one or more features, integer, step, operation, element and/or its
The presence or addition of group.
Corresponding structure in the following claims, material, effect and all instruments or step add function element
Equivalent be intended to include for reference to any knot of other claimed element perform functions of other special requirement protections
Structure, material and effect.Description of the invention is given for illustrating and describing purpose and be not intended to exhaust or limit this
It is bright in disclosed form.Those skilled in the art should be understood that perhaps under the scope and spirit of the present invention without departing from description
Many modifications and variations.Embodiment is selected and described preferably to explain the principle and practical application of the present invention, and is caused
Others skilled in the art understand that the present invention for the embodiment with various modifications is suitable for desired specific use
On the way.
Although describing embodiments of the invention, it will be understood by those skilled in the art that the present and the future, at this
Various improvement and enhancing can be carried out in the range of the subsequently appended claim of invention.These claim should be understood dimension
Hold the appropriate protection of the invention to describing first.
Claims (30)
1. a kind of encapsulating structure, including：
First and second chips, wherein first and second chip is rotated relatively to each other 90 degree at least one yardstick；
At least one surface of each in first and second chip is active surface；And
At least one of common chip, described first and second chip are electrically interconnected the common chip；
The respective active surface of first and second chip be electrically interconnected directly with one another and relative to institute with being arranged face-to-face
State common chip horizontal orientation.
2. encapsulating structure according to claim 1, wherein the bending in first and second chip is described
Bending in another in first and second chips is compensated for.
3. encapsulating structure according to claim 1, wherein at least one of described first and second chip include voltage or
At least one in power conversion apparatus, control device and storage component part.
4. encapsulating structure according to claim 1, is additionally included in the microprotrusion or micro- arranged between first and second chip
At least one in connection, the respective active surface is directly electrically interconnected by the microprotrusion or micro-force sensing.
5. encapsulating structure according to claim 1, wherein in first and second chip is at least one yardstick
Less than another in first and second chip.
6. encapsulating structure according to claim 1, also including carrier chip, first and second chip is electrically interconnected to the load
Body chip.
7. encapsulating structure according to claim 1, wherein first and second chip each be quantitatively plural number and
There is provided in the form of the chipset that the length along the common chip is arranged.
8. encapsulating structure according to claim 7, wherein one or more in the chipset include additional chip.
9. encapsulating structure according to claim 6, wherein adjacent chips group are electrically interconnected by overlapping.
10. a kind of encapsulating structure, including：
First and second chips, each in first and second chip includes thering is two apparent surfaces and described
The body of the four side walls extended between two apparent surfaces, wherein first and second chip is relative at least one yardstick
90 degree mutually rotating；
At least one of described two apparent surfaces of each in first and second chip are active surfaces；And
At least one of common chip, respective side wall of first and second chip are electrically interconnected the common core
Piece；
The described respective active surface of first and second chip be electrically interconnected directly with one another and relative with being arranged face-to-face
In the common chip horizontal orientation.
11. encapsulating structures according to claim 10, wherein the bending in first and second chip is by institute
State in the first and second chips another in bending compensate for.
12. encapsulating structures according to claim 10, wherein at least one of described first and second chip include voltage or
At least one in person's power conversion apparatus, control device and storage component part.
13. encapsulating structures according to claim 10, be additionally included between first and second chip arrange microprotrusion or
At least one in person's micro-force sensing, the respective active surface is directly electrically interconnected by the microprotrusion or micro-force sensing.
14. encapsulating structures according to claim 10, wherein in first and second chip is at least one yardstick
Upper another less than in first and second chip.
15. encapsulating structures according to claim 10, also including carrier chip, first and second chip is electrically interconnected and arrives described
Carrier chip.
16. encapsulating structures according to claim 10, wherein first and second chip each be quantitatively plural number simultaneously
And provided in the form of the chipset that the length along the common chip is arranged.
17. encapsulating structures according to claim 16, wherein one or more in the chipset include additional chip.
18. encapsulating structures according to claim 16, wherein adjacent chips group are electrically interconnected by overlapping.
A kind of 19. encapsulating structures, including：
At least chipset of the first and second chips, wherein first and second chip at least one yardstick relative to each other
It is rotated by 90 °；
At least one surface of each of first and second chip of each chipset is active surface；And
At least one of common chip, described first and second chip of each of the chipset are electrically interconnected described
Common chip；
The respective active surface of first and second chip of each of the chipset is straight each other to arrange face-to-face
Connect electrical interconnection and relative to the common chip horizontal orientation.
A kind of 20. encapsulating structures, including：
First and second chipsets, each chipset at least includes the first and second chips, wherein first and second chip
90 degree are rotated relatively to each other at least one yardstick；
At least one surface of each of first and second chip of each chipset is active surface；
The respective active surface of first and second chip of each of the chipset is straight each other to arrange face-to-face
Connect electrical interconnection；
Bonding layer, first and second chipset is attached to each other by the bonding layer；And
Insertion block, respective at least one active surface of each of first and second chip of each chipset passes through
The insertion block interconnection.
21. encapsulating structures according to claim 20, also including package substrate, bottom chipset is interconnected to the package substrate.
A kind of 22. methods of assembled package structure, including：
To arrange the respective active surface that the first and second chips are directly electrically interconnected face-to-face, wherein first and second core
Piece is rotated relatively to each other 90 degree at least one yardstick；
At least one of respective side wall by first and second chip is electrically interconnected to common chip；And
Relative to the described respective active surface of the first and second chips described in the common chip horizontal orientation.
23. methods according to claim 22, also include being supported by the bending in first and second chip
Repay in first and second chip another in bending.
24. methods according to claim 22, also have voltage or power conversion apparatus, control device, include including being formed
In at least one first and second chip in the passive device or storage component part of capacitor or inducer at least
It is a kind of.
25. methods according to claim 22, are additionally included between first and second chip and arrange microprotrusion or micro-force sensing
At least one of.
26. methods according to claim 22, are also included compared with first and second chip, reduce described the
One and second size on another at least one yardstick in chip.
27. methods according to claim 22, also include for described first and the second chip being electrically connected to carrier chip.
28. methods according to claim 22, also include being carried in the form of the chipset that the length along the common chip is arranged
For multiple first and second chips.
29. methods according to claim 28, wherein one or more in the chipset include additional chip.
30. methods according to claim 28, are also included by the neighbouring chipset of overlap joint electrical connection.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/721,991 US8916959B2 (en) | 2012-12-20 | 2012-12-20 | Packaging structure |
| US13/721,991 | 2012-12-20 | ||
| US13/968,099 | 2013-08-15 | ||
| US13/968,099 US8927336B2 (en) | 2012-12-20 | 2013-08-15 | Packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103887277A CN103887277A (en) | 2014-06-25 |
| CN103887277B true CN103887277B (en) | 2017-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310584975.9A Expired - Fee Related CN103887277B (en) | 2012-12-20 | 2013-11-19 | Packaging Structure And Method Of Assembling A Packaging Structure |
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| CN (1) | CN103887277B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737192A (en) * | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004303884A (en) * | 2003-03-31 | 2004-10-28 | Seiko Epson Corp | Method of manufacturing three-dimensional mounted module and three-dimensional mounted module obtained thereby |
| US7009296B1 (en) * | 2004-01-15 | 2006-03-07 | Amkor Technology, Inc. | Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die |
| US8247895B2 (en) * | 2010-01-08 | 2012-08-21 | International Business Machines Corporation | 4D device process and structure |
| US8330262B2 (en) * | 2010-02-02 | 2012-12-11 | International Business Machines Corporation | Processes for enhanced 3D integration and structures generated using the same |
| US8390109B2 (en) * | 2011-02-17 | 2013-03-05 | Oracle America, Inc. | Chip package with plank stack of semiconductor dies |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5737192A (en) * | 1993-04-30 | 1998-04-07 | The United States Of America As Represented By The Secretary Of The Air Force | Density improvement in integration modules |
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| CN103887277A (en) | 2014-06-25 |
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